Strain Gauges Patents (Class 148/DIG159)
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Patent number: 6001666Abstract: This invention relates to the manufacture of a strain gauge sensor using the piezoresistive effect, comprising a structure (1) made of a monocrystalline material acting as support to at least one strain gauge (2) made of a semiconducting material with a freely chosen doping type. The strain gauge (2) is an element made along a crystallographic plane determined to improve its piezoresistivity coefficient. The structure (1) is a structure etched along a crystallographic plane determined to improve its etching. The strain gauge (2) is fixed to the structure (1) by bonding means capable of obtaining said sensor.Type: GrantFiled: March 24, 1997Date of Patent: December 14, 1999Assignee: Commissariat a l'Energie AtomiqueInventors: Bernard Diem, Sylvie Viollet-Bosson, Patricia Touret
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Patent number: 5932048Abstract: A method of direct-bonding semiconductor wafers limits the time interval between a bonding step and a bonding anneal step or performs a baking step between the bonding and bonding anneal steps at a predetermined temperature for a predetermined time interval to prevent the formulation of voids on the edge regions of the wafers. The method for fabricating laminated semiconductor wafers includes a bonding step to fit together two polished semiconductor wafers by bonding jigs, and a succeeding bonding anneal step to laminate the wafers. In the method the bonding anneal step is preferably carried out within an hour following the bonding step; or a baking step at a predetermined temperature for a predetermined time interval is carried out between the bonding step and the bonding anneal step. Further, the method can prevent heavy metal impurities attached to the surface of the wafer from diffusing into the wafer by baking the wafer for over 5 minutes at above 100.degree. C.Type: GrantFiled: June 25, 1997Date of Patent: August 3, 1999Assignee: Komatsu Electronic Metals Co., Ltd.Inventors: Hiroshi Furukawa, Hirotaka Kato, Hiroaki Yamamoto, Kazuaki Fujimoto
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Patent number: 5804457Abstract: In a force sensor, a resonator is mounted by means of a dielectric layer on a bending element. Deformation of the bending element changes the resonant frequency of the resonator.Type: GrantFiled: June 5, 1996Date of Patent: September 8, 1998Inventors: Gerhard Benz, Franz Laermer, Andrea Schilp, Erich Zabler, Jurgen Schirmer, Werner Uhler
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Patent number: 5769991Abstract: A method of wafer bonding with less elongation and contraction of wafers at the time of and after the bonding of the wafers is disclosed. In the method of wafer bonding, wafers are bonded together with sticking force of their surfaces to form a bonded wafer. The bonding is done by selecting the pressure of the gas between the wafers to be lower than the atmospheric pressure, for instance, and also selecting the kind of gas between the wafers to H.sub.2, for instance.Type: GrantFiled: February 23, 1994Date of Patent: June 23, 1998Assignee: Sony CorporationInventors: Yoshihiro Miyazawa, Yasunori Ohkubo
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Patent number: 5723353Abstract: An acceleration sensor is composed of a three-layer system. The acceleration sensor and conductor tracks are patterned out of the third layer. The conductor tracks are electrically isolated from other regions of the third layer by recesses and electrically insulated from a first layer by a second electrically insulating layer. In this manner, a simple electrical contacting is achieved, which is configured out of a three-layer system.Type: GrantFiled: February 12, 1996Date of Patent: March 3, 1998Assignee: Robert Bosch GmbHInventors: Horst Muenzel, Dietrich Schubert, Alexandra Boehringer, Michael Offenberg, Klaus Heyers, Markus Lutz
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Patent number: 5700702Abstract: Manufacturing method for an acceleration sensor on silicon, whereby, following the manufacture of the doped regions required for the electronic function elements, a polysilicon layer is deposited. The polysilicon layer is structured such that a portion of this polysilicon layer forms an electrode (for example, the emitter electrode (9) and the collector electrode (10) of a transistor) and a sensor layer (17) provided as sensor element.Type: GrantFiled: July 17, 1996Date of Patent: December 23, 1997Assignee: Siemens AktiengesellschaftInventors: Helmut Klose, Markus Biebl, Thomas Scheiter, Christofer Hierold
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Patent number: 5648300Abstract: A method of manufacturing a cantilever drive mechanism arranged in such a manner that a cantilever portion, in which a piezoelectric layer is disposed between electrode layers, and a circuit portion, which is positioned adjacent to the cantilever portion and which drives the cantilever, are formed on the same substrate. The method includes the steps of first forming the circuit portion and then forming the cantilever portion after the circuit portion has been formed.Type: GrantFiled: November 18, 1994Date of Patent: July 15, 1997Assignee: Canon Kabushiki KaishaInventors: Masaru Nakayama, Osamu Takamatsu, Takayuki Yagi, Keisuke Yamamoto, Takehiko Kawasaki, Yasuhiro Shimada, Yoshio Suzuki
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Patent number: 5549785Abstract: A method of producing a semiconductor dynamic sensor which features an improved sensitivity yet having a small size while avoiding damage to the thin distortion-producing portion. A resist film 49 is photo-patterned on the front main surface of the semiconductor substrate 41 except for the region where the upper isolation grooves are to be formed prior to forming the lower isolation groove 10 by the first etching of the back main surface of the semiconductor substrate 41 (which includes the epitaxial layer 42). Unlike the prior art, therefore, there is no need to spin-coat the front main surface of the semiconductor substrate 41 with the resist film 49 which is followed by photo-patterning after a predetermined region of the semiconductor substrate 41 has been reduced in thickness by the first etching. Therefore, damage therefore to the thin portion by the vacuum chucking the wafer during the spin-coating of the resist film is avoided.Type: GrantFiled: September 14, 1993Date of Patent: August 27, 1996Assignee: Nippondenso Co., Ltd.Inventors: Minekazu Sakai, Tsuyoshi Fukada, Masakazu Terada, Shinsuke Watanabe, Minoru Nishida
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Patent number: 5525549Abstract: A method for producing a semiconductor device that is capable of solving problems related to dicing a metal thin film used for electrochemical etching. According to the method, an n type epitaxial thin layer is formed on a p type single-crystal silicon wafer. An n.sup.+ type diffusion layer is formed in a scribe line area on the epitaxial layer. An n.sup.+ type diffusion layer is formed in an area of the epitaxial layer which corresponds to a predetermined portion of the wafer. An aluminum film is formed over the diffusion layers. The aluminum film has a clearance for passing a dicing blade. Portions of the wafer are electrochemically etched by supplying electricity through the aluminum film and the diffusion layers, to leave portions of the epitaxial layer. The wafer is diced into chips along the scribe line area. Each of the chips forms a separate semiconductor device.Type: GrantFiled: April 21, 1993Date of Patent: June 11, 1996Assignee: Nippondenso Co., Ltd.Inventors: Tsuyoshi Fukada, Yoshimi Yoshino, Yukihiko Tanizawa
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Patent number: 5510276Abstract: A process for producing a pressure transducer or sensor using the silicon-on-insulator method is provided. The process includes the following steps: (a) producing a monocrystalline silicon film (44) on a silicon substrate (6) at least locally separated from the latter by an insulating layer (42), (b) producing an opening (24) in the silicon film down to the insulating layer, (c) partially eliminating the insulating layer via the opening in order to form the diaphragm in the silicon film, and (d) resealing the opening (26).Type: GrantFiled: December 15, 1993Date of Patent: April 23, 1996Assignee: Commissariat a l'Energie AtomiqueInventors: Bernard Diem, Marie-Therese Delaye
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Patent number: 5484745Abstract: A method for forming at least one corrugation member in a semiconductor material, contains the step of: forming a semiconductor material layer onto a substrate, masking a first surface of the semiconductor material, etching the first surface to form first cavity thereon, removing a mask from the semiconductor material, masking the first surface and second surface of the semiconductor material, etching the second surface to form second cavity thereon, the second cavity being defined into the first cavity, removing the mask from the semiconductor material, depositing a specified masking material selected in accordance with a characteristic of the substrate onto the semiconductor material, etching an unmasked portion of the semiconductor material and depositing the same material as the abovementioned specified masking material selected in accordance with a characteristic of the substrate onto the semiconductor material and the specified masking material which has been deposited onto the semiconductor to form theType: GrantFiled: October 26, 1993Date of Patent: January 16, 1996Assignee: Yazaki Meter Co., Ltd.Inventor: Sean S. Cahill
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Patent number: 5383993Abstract: In a method of bonding semiconductor substrates, a plurality of the semiconductor substrates are first prepared. Surfaces of the semiconductor substrates are mirror-polished. The mirror-polished surface of at least one of the semiconductor substrates is then provided with a hydrophilic property in such a way that an oxide layer is formed on the mirror-polished surface by exposing the mirror-polished surface to an atmosphere of at least one of an oxygen ion and an oxygen radical. A water molecule is then adhered to the mirror-polished surface. The semiconductor substrates then contact with each other through the mirror-polished surface. The contacted semiconductor substrates are then heated. According to such a method of bonding, the semiconductor substrates are strongly bonded to each other with hardly an unbonded region even if the semiconductor substrates are heated at a low temperature.Type: GrantFiled: September 10, 1993Date of Patent: January 24, 1995Assignee: Nippon Soken Inc.Inventors: Mitsutaka Katada, Kazuhiro Tsuruta, Seiji Fujino, Michitoshi Onoda
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Patent number: 5310450Abstract: A method of making acceleration sensors with integrated measurement of internal pressure includes connecting multiple plates to each other, thereby defining internal cavities. The tightness of these connections or bonds is checked and controlled during the manufacturing process. The plates define membrane portions adjacent each cavity, the membranes deforming in accordance with the internal pressure in the adjacent cavity. Preferably, the internal pressure of the sensor is measurable by detecting deformation of a sensor wall which defines a membrane.Type: GrantFiled: June 17, 1992Date of Patent: May 10, 1994Assignee: Robert Bosch GmbHInventors: Michael Offenberg, Martin Willmann
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Patent number: 5169472Abstract: Multi-layer silicon structures particularly micromechanical sensors, can be made by cleaning and polishing respective surfaces of two silicon wafers, assembling the wafers together under clean room conditions and adhering them together by temperature treatment. This method is improved by the pretreatment of the wafer surfaces using fuming nitric acid (e.g., 100% HNO.sub.3), rinsing with de-ionized water, drying, and temperature treatment at a lower temperature than was previously thought necessary, namely between 100.degree. and 400.degree. C. This has the advantage that such gentler treatment preserves previously-applied integrated circuit structures, which can therefore be applied before the wafer assembly steps. The method is particularly suitable for producing pressure sensors having a pressure-responsive silicon membrane, and an evaluation circuit integrated on the silicon wafer.Type: GrantFiled: March 14, 1991Date of Patent: December 8, 1992Assignee: Robert Bosch GmbHInventor: Herbert Goebel
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Patent number: 5164339Abstract: Method for producing a low stress silicon oxynitride microstructure on a semiconductor substrate at temperatures not higher than 500.degree. C. The method is particularly adapted for forming integrated silicon sensors where the oxynitride microstructure is fabricated on a substrate under conditions which do not harm the integrated circuit electronics.Type: GrantFiled: May 28, 1991Date of Patent: November 17, 1992Assignee: Siemens-Bendix Automotive Electronics L.P.Inventor: George E. Gimpelson
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Patent number: 5155061Abstract: A method for fabricating an all silicon absolute pressure sensor employing silicon-on-insulator structures. More particularly, a method for fabricating an all silicon absolute pressure sensor based upon an ungated metal-oxide semiconductor field-effect transistor which offers a high degree of immunity to temperature effects, increased reliability, minimal substrate parasitics, reduced manufacturing variations from device to device, as well as inexpensive and simple fabrication.Type: GrantFiled: June 3, 1991Date of Patent: October 13, 1992Assignee: Allied-Signal Inc.Inventors: James M. O'Connor, John B. McKitterick
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Patent number: 5110373Abstract: A method for fabricating a silicon membrane with predetermined stress characteristics. A silicon substrate is doped to create a doped layer as thick as the desired thickness of the membrane. Stress within the doped layer is controlled by selecting the dopant based on its atomic diameter relative to silicon and controlling both the total concentration and concentration profile of the dopant. The membrane is then formed by electrochemically etching away the substrate beneath the doped layer.Type: GrantFiled: August 9, 1990Date of Patent: May 5, 1992Assignee: Nanostructures, Inc.Inventor: Philip E. Mauger
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Patent number: 5059556Abstract: Method for relieving stress in silicon microstructures by forming a silicide on the microstructures. Sensors comprising a stress-relieved silicon microstructure are also described.Type: GrantFiled: March 16, 1990Date of Patent: October 22, 1991Assignee: Siemens-Bendix Automotive Electronics, L.P.Inventor: Duane T. Wilcoxen
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Patent number: 4878957Abstract: A dielectrically isolated semiconductor wafer substrate includes first and second semiconductive layers bonded to each other by a direct bonding technique in such a manner that an insulative layer is sandwiched therebetween. The first semiconductive layer is a first silicon layer having a (100) or (110) crystal surface orientation, while the second semiconductive layer is a second silicon layer having a (111) crystal surface orientation. Thereafter, a peripheral portion of the resultant substrate is removed, and a substrate of a slightly smaller size is obtained which is provided with an additionally formed new orientation flat.Type: GrantFiled: March 30, 1989Date of Patent: November 7, 1989Assignee: Kabushiki Kaisha ToshibaInventors: Yoshihiro Yamaguchi, Kiminori Watanabe, Akio Nakagawa, Kazuyoshi Furukama, Kiyoshi Fukuda, Katsujiro Tanzawa
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Patent number: 4704186Abstract: A plurality of first cavities is formed in the planar surface of a silicon substrate. A first oxide region of predetermined thickness is formed in each of the first cavities such that each of the first oxide regions has a surface which is coplanar with the substrate surface. A layer of monocrystalline silicon is then epitaxially deposited over the planar first oxide region/substrate surface. Second cavities are then formed through the monocrystalline silicon layer and into the substrate adjacent the first oxide regions, extending to a depth equal to approximately one-half that of the first oxide regions. The second cavities are then thermally oxidized so as to form second oxide regions therein, these second oxide regions being coplanar with the first oxide regions. Silicon is next epitaxially deposited on those portions of the monocrystalline silicon layer remaining on the first oxide regions so as to yield a continuous monocrystalline silicon sheet over the first and second oxide regions.Type: GrantFiled: February 19, 1986Date of Patent: November 3, 1987Assignee: RCA CorporationInventor: Lubomir L. Jastrzebski
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Patent number: 4670969Abstract: A method of making a silicon diaphragm pressure sensor includes forming an oxide film on one surface of a monocrystalline silicon substrate. A polycrystalline silicon layer is formed on the oxide film. The oxide film may be partly removed before the formation of the polycrystalline silicon layer. The polycrystalline silicon layer is heated and melt to recrystallize the same, thereby converting the polycrystalline silicon layer into a monocrystalline silicon layer. On the monocrystalline silicon layer may be epitaxially grown an additional monocrystalline silicon layer. By using the oxide film as an etching stopper, a predetermined portion of the substrate is etched over a range from the other surface of the substrate to the oxide film, thereby providing a diaphragm of the pressure sensor.Type: GrantFiled: January 25, 1985Date of Patent: June 9, 1987Assignee: Hitachi, Ltd.Inventors: Kazuji Yamada, Yutaka Kobayashi, Kanji Kawakami, Satoshi Shimada, Masanori Tanabe, Shigeyuki Kobori
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Patent number: 4665610Abstract: A semiconductor pressure transducer includes a silicon substrate, a recessed portion in a major surface of the substrate, and a multiple level diaphragm overlying the recessed portion. A selectively etchable spacer material is employed when fabricating the diaphragm by forming successive layers of diaphragm material over the spacer material. Holes through the diaphragm are filled with the selectively etchable material thereby allowing the etching of the spacer material. Support posts can be provided in the recessed portion to help support the diaphragm.Type: GrantFiled: April 22, 1985Date of Patent: May 19, 1987Assignee: Stanford UniversityInventor: Phillip W. Barth
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Patent number: 4638552Abstract: A method of manufacturing a semiconductor substrate having a modified layer therein comprises the steps of mirror-polishing one surface of each of first and second semiconductor plates, forming a modified layer on at least one of the polished surfaces of the first and second semiconductor plates, and bonding the polished surfaces of the first and second semiconductor plates with each other in a clean atmosphere.Type: GrantFiled: February 14, 1985Date of Patent: January 27, 1987Assignee: Kabushiki Kaisha ToshibaInventors: Masaru Shimbo, Kiyoshi Fukuda, Yoshiaki Ohwada
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Patent number: 4523964Abstract: The invention relates to a process for producing silicon diaphragm pressure transducers, and to pressure transducers so produced, which will operate in high temperature applications above 150.degree. C. by properly insulating the strain gauges from the diaphragm. This is achieved by utilizing two properly oriented silicon wafers which are joined together by a two-step diffusion technique, which includes the diffusion bonding of one boron doped wafer surface into the other wafer surface previously oxide coated, at greatly reduced pressures and temperatures than heretofore used. This simultaneous diffusion takes place because of prior contouring or the forming of relief channels into one of the bonded surfaces, and because only one joined surface is oxide coated, thus reducing process times substantially. That is, there is a continuous diffusion of boron into the boron oxide coated surface resulting in a boron rich layer of great uniformity.Type: GrantFiled: March 30, 1983Date of Patent: June 18, 1985Assignee: Becton, Dickinson and CompanyInventors: L. Bruce Wilner, Herbert V. Wong
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Patent number: 4510671Abstract: A transducer structure is disclosed which comprises a single crystal semiconductor diaphragm dielectrically isolated by a layer of silicon dioxide from a single crystal gage configuration. The methods depicted employ high dose oxygen which is ion implanted into a monocrystalline wafer to form a buried layer of silicon dioxide with the top surface of the wafer being monocrystalline silicon. An additional layer of silicon is epitaxially grown on the top surface of the wafer to enable the etching or formation of a desired gage pattern.Type: GrantFiled: November 21, 1983Date of Patent: April 16, 1985Assignee: Kulite Semiconductor Products, Inc.Inventors: Anthony D. Kurtz, Timothy A. Nunn, Joseph R. Mallon