Tapered Edges Patents (Class 148/DIG161)
  • Patent number: 5937309
    Abstract: A method for fabricating a shallow trench isolation (STI) structure in a semiconductor substrate. A stop layer is formed on the substrate and a first sacrificial layer is formed on the stop layer. The first sacrificial layer and the stop layer are defined to form an opening on the substrate. A conformal second sacrificial layer with rounded corners is formed on the substrate. The second sacrificial layer, the first sacrificial layer, and a portion of the substrate are anisotropically removed to form a trench in the substrate using the stop layer as a removal stop layer. The substrate is over removed using the stop layer as a mask layer so that spacers of the second sacrificial layer are remained on the substrate to cover portions of sidewalls of the stop layer.
    Type: Grant
    Filed: February 1, 1999
    Date of Patent: August 10, 1999
    Assignee: United Semiconductor Corp.
    Inventor: Shu-Ya Chuang
  • Patent number: 5874317
    Abstract: A method of fabricating an integrated circuit with trenches, without parasitic edge transistors, for isolating FET transistors from each other without degrading the FETs operating characteristics by junction leakage, breakdown or shorting, when a metal silicide is used in the source/drain regions. A silicon wafer is formed with sidewalls on the sides of each area in which a groove is to be etched. In etching the silicon, the sidewalls define the lateral dimension of the trenches. After the trenches are etched, the sidewalls are removed and the trenched are filled with an insulating material using a high density plasma reactor, such as an electron cyclotron resonance (ECR) plasma reactor. This type of reactor simultaneously deposits and sputter etches so that silicon edges at the base of the now removed sidewalls become tapered at an angle of about 45.degree. during deposition.
    Type: Grant
    Filed: June 12, 1996
    Date of Patent: February 23, 1999
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Andre Stolmeijer
  • Patent number: 5849611
    Abstract: A wiring formed on a substrate is oxidized and the oxide is used as a mask for forming source and drain impurity regions of a transistor, or as a material for insulating wirings from each other, or as a dielectric of a capacitor. Thickness of the oxide is determined depending on purpose of the oxide.In a transistor adapted to be used in an active-matrix liquid-crystal display, the channel length, or the distance between the source region and the drain region, is made larger than the length of the gate electrode taken in the longitudinal direction of the channel. Offset regions are formed in the channel region on the sides of the source and drain regions. No or very weak electric field is applied to these offset regions from the gate electrode.
    Type: Grant
    Filed: May 31, 1995
    Date of Patent: December 15, 1998
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Akira Mase, Masaaki Hiroki, Yasuhiko Takemura, Hongyong Zhang, Hideki Uochi
  • Patent number: 5811342
    Abstract: A method for forming a semiconductor device with a graded lightly-doped drain (LDD) structure is disclosed. The method includes providing a semiconductor substrate (10) having a gate region (14 and 16) thereon, followed by forming a pad layer (18) on the substrate and the gate region. Next, ions are implanted into the substrate, and a spacer (22) is formed on sidewalls of the gate region, wherein the first spacer has a concave surface inwards on a surface of the first spacer. Finally, ions are further implanted into the substrate using the gate region and the spacer as a mask, thereby forming a graded doping profile (20) in the substrate.
    Type: Grant
    Filed: January 26, 1998
    Date of Patent: September 22, 1998
    Assignee: Texas Instruments - Acer Incorporated
    Inventor: Shye-Lin Wu
  • Patent number: 5801083
    Abstract: A method for forming insulator filled, shallow trench isolation regions, with rounded corners, has been developed. The process features the use of a polymer coated opening, in an insulator layer, used as a mask to define the shallow trench region in silicon. After completion of the shallow trench formation the polymer spacers are removed, exposing a region of unetched semiconductor, that had been protected by the polymer spacers, during the shallow trench dry etching procedure. The sharp corner, at the intersection between the shallow trench and the unetched region of semiconductor, is then converted to a rounded corner, via thermal oxidation of exposed silicon surfaces. The polymer spacers also eliminate the top corner wraparound.
    Type: Grant
    Filed: October 20, 1997
    Date of Patent: September 1, 1998
    Assignee: Chartered Semiconductor Manufacturing, Ltd.
    Inventors: Bo Yu, Qing Hua Zhong, Jian Hui Ye, Mei Sheng Zhou
  • Patent number: 5686363
    Abstract: After a polycrystalline Si layer is deposited on an insulating film covering the surface of a semiconductor substrate, a mask layer having a desired pattern is deposited on the polycrystalline Si layer. Using the mask layer as an etching mask, the polycrystalline Si layer is dry-etched by a plasma etching process. In the plasma etching process, a metal halide (such as AlCl.sub.3 and AlBr.sub.3) gas is introduced in an etching reaction chamber, or Al halide is generated by reacting halogen (Cl, Br or the like) contained in an etching gas with Al constituting the inner wall of the etching reaction chamber or an electrode. The etching process is performed while attaching an Al halide film to the etched side walls of the polycrystalline film. The polycrystalline Si film is etched in a taper shape becoming thicker at the lower portion. The Al halide can be removed easily.
    Type: Grant
    Filed: December 6, 1993
    Date of Patent: November 11, 1997
    Assignee: Yamaha Corporation
    Inventor: Suguru Tabara
  • Patent number: 5668045
    Abstract: A process for stripping the outer edge of a bonded BESOI wafer. The bonded BESOI wafer comprises a handle wafer, an oxide layer on one surface of the handle wafer, a device layer bonded to the oxide layer, and a p.sup.+ etch-stop layer on the device layer having an exposed face. The process comprises masking the exposed face of the p.sup.+ etch-stop layer, and abrading the periphery of the BESOI wafer to remove edge margins of the p.sup.+ etch-stop layer and device layer.
    Type: Grant
    Filed: November 30, 1994
    Date of Patent: September 16, 1997
    Assignee: SiBond, L.L.C.
    Inventors: David I. Golland, Robert A. Craven, Ronald D. Bartram
  • Patent number: 5658818
    Abstract: A method of forming a capacitor includes, a) providing a substrate; b) etching into the substrate to provide a depression in the substrate, the depression having a sidewall which is angled from vertical; c) providing a conformal layer of hemispherical grain polysilicon within the depression and over the angled sidewall, the layer of hemispherical grain polysilicon less than completely filling the depression; and d) ion implanting the hemispherical grain polysilicon layer with a conductivity enhancing impurity. Preferred methods of providing the depression where the substrate comprises SiO.sub.2 include a dry, plasma enhanced, anisotropic spacer etch utilizing reactant gases of CF.sub.4 and CHF.sub.3 provided to the substrate at a volumetric ratio of 1:1, and facet sputter etching.
    Type: Grant
    Filed: August 18, 1995
    Date of Patent: August 19, 1997
    Assignee: Micron Technology, Inc.
    Inventors: Salman Akram, Charles Turner, Alan Laulusa
  • Patent number: 5591675
    Abstract: An interconnecting method for a semiconductor device is disclosed in which a conductive layer containing aluminum is formed on a lower structure formed on a substrate. An insulating layer is formed on the conductive layer. A photoresist pattern for defining a portion where an opening is to be made is formed on the insulating layer. Then, the insulating layer is isotropically etched by wet etching with the photoresist pattern as an etching mask. The insulating layer remaining after the isotropical etching is taper-etched by RIE to form the opening. To ensure that the conductive layer is exposed by the opening, the resultant structure is overetched by using a mixed gas of fluorocarbon-containing gas and oxygen. This resultant structure is RIE-sputtered using fluorocarbon-containing gas such that polymer or nonvolatile by-products generated when the opening such as a via hole is formed, are completely removed.
    Type: Grant
    Filed: December 22, 1994
    Date of Patent: January 7, 1997
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-woo Kim, Joon Kim, Jin-hong Kim
  • Patent number: 5578518
    Abstract: A semiconductor device comprises a semiconductor substrate having a major surface, a trench device isolation region having a trench selectively formed to define at least one island region in the major surface of the semiconductor substrate and a filler insulatively formed within the trench, an elongated gate electrode insulatively formed over a central portion of the island region so that each of its both ends which are opposed to each other in the direction of its length overlaps the trench device isolation region, and source and drain regions formed within the island region on the both sides of the gate electrode. The surface of the trench device isolation region is formed lower than the major surface of the semiconductor substrate.
    Type: Grant
    Filed: December 15, 1994
    Date of Patent: November 26, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hidetoshi Koike, Kazunari Ishimaru, Hiroshi Gojohbori, Fumitomo Matsuoka
  • Patent number: 5541127
    Abstract: Disclosed are a semiconductor device having a sidewall insulating film free from the formation of fence-shaped residue when a conductive layer formed on the sidewall insulating film is anisotropically etched by means of plasma etching, and a method of forming the sidewall insulating film. The method of forming the sidewall insulating film includes the steps of isotropically etching an insulating film 4 formed on a polycrystalline silicon film 3 to be a gate electrode as much as a prescribed thickness, using resist as a mask, anisotropically etching the remaining part of insulating film 4 and polycrystalline silicon film 3, forming an insulating film 6 entirely over the surface, and forming a sidewall insulating film 6a on the side plane of polycrystalline silicon film 3. The resultant sidewall insulating film 6a has a cross-section reduced upwardly in width.
    Type: Grant
    Filed: May 15, 1995
    Date of Patent: July 30, 1996
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Takahiro Hoshiko, Toshiaki Ogawa
  • Patent number: 5502006
    Abstract: When taper portions of contact holes are etched to form wiring conductors in a semiconductor device, a hydrophobic insulating film having methyl groups on its surface is formed on a SiO.sub.2 film in the low pressure CVD process, using mixed gas of tetraethyl orthosilicate TEOS and ozone O.sub.3. Since the hydrophobic insulating film adheres well to a resist film, etching solution seldom soaks into between the hydrophobic insulating film and the resist film, thus wet etching is performed in the insulating film to obtain satisfactory taper portions of the contact holes.
    Type: Grant
    Filed: November 2, 1994
    Date of Patent: March 26, 1996
    Assignee: Nippon Steel Corporation
    Inventor: Yasuo Kasagi
  • Patent number: 5488001
    Abstract: In the manufacture of a liquid-crystal display or other large area electronic device, thin-film transistors are formed on a substrate (10) from a thin film (1) of disordered semiconductor material which accommodates the transistor channel regions and has a high density of trapping states. A masking pattern (13) masks areas of the semiconductor film (1) where the thin-film transistors are to be formed. The unmasked areas of the film (1) are etched away to leave the semiconductor film bodies for the transistors. The resulting transistors are found to have an undesirable leakage current through the channel region, even after adopting several prior art measures to reduce the high leakage. By implanting a dopant stripe (5) along their edges, the present invention reduces leakage currents along the edges of the channel region in the etched disordered semiconductor material (1).
    Type: Grant
    Filed: July 28, 1994
    Date of Patent: January 30, 1996
    Assignee: U.S. Philips Corporation
    Inventor: Stanley D. Brotherton
  • Patent number: 5464794
    Abstract: A new method of metallization using a new design of metal contact shape, contact/via profile, and metal lines having considerably reduced current density and improved electromigration of metal lines is achieved. Metal contacts are formed in a rectangular shape instead of a square shape with the wider side perpendicular to the current direction. Contact openings are made having concavo-concave profiles which can provide a wider conducting cross-sectional area than can conventional openings with a vertical profile near the contact bottom. Gaps are formed within wide and high current metal lines so that current density can be effectively lowered by utilizing the whole metal line uniformly.
    Type: Grant
    Filed: May 11, 1994
    Date of Patent: November 7, 1995
    Assignee: United Microelectronics Corporation
    Inventors: Water Lur, Jiun Y. Wu
  • Patent number: 5444007
    Abstract: Trenches having different profiles are formed in a material, such as a semiconductor substrate, by forming a resist pattern having windows with at least two different widths. An etchant, such as Fluorine, is implanted into portions of the semiconductor using an ion implantation technique. A tilt angle and an azimuth angle of the ion beam are chosen such that the Fluorine ions cannot pass through narrower resist windows but can pass through wider resist windows to impinge on the underlying semiconductor substrate. The semiconductor substrate is then subjected to an anisotropic etching process. Accordingly, the substrate regions exposed between the narrow-width resist windows are etched to produce trenches having highly vertical profiles. The substrate regions exposed by the wide-width resist windows, including the regions having implanted etchant ions, are preferentially etched to produce trenches having tapered profiles.
    Type: Grant
    Filed: August 3, 1994
    Date of Patent: August 22, 1995
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Masakatsu Tsuchiaki
  • Patent number: 5393682
    Abstract: A new method of forming a tapered polysilicon etching profile in the manufacture of a thin film transistor integrated circuit is described. A layer of polysilicon is deposited over the surface of a semiconductor substrate. Ions are implanted into the polysilicon layer whereby the upper half of the polysilicon layer is damaged by the presence of the ions within the layer. The polysilicon layer is anisotropically etched. The polysilicon layer is isotropically etched whereby the damaged upper portion of the layer is etched faster than is the undamaged lower portion resulting in a tapered polysilicon layer. A layer of gate oxide is deposited over the surface of the tapered polysilicon layer. Then the thin film transistor body is formed. A layer of amorphous silicon is deposited over the surface of the gate oxide layer. The amorphous silicon layer is recrystallized to yield larger grain sizes.
    Type: Grant
    Filed: December 13, 1993
    Date of Patent: February 28, 1995
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventor: Chwen-Ming Liu
  • Patent number: 5338703
    Abstract: In a method for producing a recessed gate field effect transistor including a recess in a semiconductor substrate and a gate electrode disposed in the recess, a photoresist film is applied to the semiconductor substrate and source and drain electrodes on the substrate, a first insulating film is formed on the photoresist film, a resist pattern, which has an opening for processing the first insulating film and the photoresist film are etched using the resist pattern as a mask to form an opening having a width increasing in the direction of the substrate, a second insulating film is formed on opposite side walls of the opening, the semiconductor substrate is etched using the opening narrowed by the second insulating film in the substrate to form a recess, the second insulating film is selectively removed by etching, gate metal is deposited on the photoresist and on the substrate in the recess, and unnecessary gate metal is removed by lifting-off the resist film.
    Type: Grant
    Filed: July 7, 1993
    Date of Patent: August 16, 1994
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Hiroshi Matsuoka
  • Patent number: 5284780
    Abstract: For increasing the electric strength of a semiconductor component that comprises a sequence of semiconductor layers of alternating conductivity type and which is adapted to be charged with a voltage that biases at least one of the p-n junctions that separate the layers from one another in the non-conducting direction, the carrier life is reduced only in the lateral region of the edge termination of this p-n junction. The carrier life is reduced by irradiation with electrons or protons or by introducing atoms having recombination properties.
    Type: Grant
    Filed: November 12, 1992
    Date of Patent: February 8, 1994
    Assignee: Siemens Aktiengesellschaft
    Inventors: Hans-Joachim Schulze, Heinz Mitlehner
  • Patent number: 5269880
    Abstract: A method of tapering side walls of via holes and a tapered via hole structure for an integrated circuit is provided. Via holes having steep sidewalls are provided in an insulating layer overlying a conductive layer on a substrate, with an underlying conductive layer exposed at a bottom of each via hole. A protective layer is provided over the conductive layer in each via hole, and over the sidewalls. The via holes are then tapered by argon sputter etching to remove the protective layer and part of the insulating layer from the sidewall and around the peripheral edge of each via hole, thereby smoothly tapering the sidewall and providing a via hole increasing continuously in diameter from the bottom to the upper peripheral edge of the via hole.
    Type: Grant
    Filed: April 3, 1992
    Date of Patent: December 14, 1993
    Assignee: Northern Telecom Limited
    Inventors: Gurvinder Jolly, Bud K. Yung
  • Patent number: 5225376
    Abstract: According to the principles of this invention, a polysilicon layer in a semiconductor device is shaped so that in subsequent processing steps a uniform topology is achieved. In particular, a first layer, typically polysilicon, is overlain by a second layer, typically spin-on glass, which is in turn overlain by a mask layer. An opening is formed in the mask layer and the second layer. An isotropic etchant is applied to the structure after the opening is formed. The etchant is formulated to have a differential etch rate in the first and the second layers so that the first layer after etching has an edge surface with a taper of less than 60.degree. and preferably about 45.degree..
    Type: Grant
    Filed: January 13, 1992
    Date of Patent: July 6, 1993
    Assignee: NEC Electronics, Inc.
    Inventors: Lloyd W. Feaver, Masanori Sakata
  • Patent number: 5225235
    Abstract: A semiconductor wafer on which silicon or the like is epitaxially grown and p-type or n-type impurities are doped and which has at the rear surface except for the peripheral edge portion thereof a blocking film for preventing jumping out of impurities therefrom which causes auto-doping, thereby preventing silicon particles from being produced at the peripheral surface and preventing the semiconductor wafer from being contaminated by the silicon particles during the manufacturing a semiconductor device.
    Type: Grant
    Filed: August 5, 1991
    Date of Patent: July 6, 1993
    Assignees: Osaka Titanium Co., Ltd., Kyushu Electronic Metal Co., Ltd.
    Inventors: Tetsujiro Yoshiharu, Haruo Kamise
  • Patent number: 5127885
    Abstract: Ductility of belt material is increased at least at one edge of an endless metal belt, thus reducing the likelihood of premature failure of the belt. The inner region of the belt maintains the inherent strength of the metal. The endless metal belt so formed is particularly useful as a driving member for a continuously-variable transmission.
    Type: Grant
    Filed: December 24, 1990
    Date of Patent: July 7, 1992
    Assignee: Xerox Corporation
    Inventors: William G. Herbert, Mark S. Thomas
  • Patent number: 5084409
    Abstract: Shadow masking layer (130) is undercut during etch of sidewall layer (120) thus preventing sidewall growth during growth of heteroepitaxial region (140), resulting in a planar structure with a high integrity of crystal in the grown region (140).
    Type: Grant
    Filed: June 26, 1990
    Date of Patent: January 28, 1992
    Assignee: Texas Instruments Incorporated
    Inventors: Edward A. Beam, III, Yung-Chung Kao
  • Patent number: 5045505
    Abstract: When both main surface sides of a substrate doped with an impurity at a lower concentraiton are subjected to diffusion to form a higher concentrated impurity layer on the surfaces, about a half of the thickness of the substrate is removed to expose a layer doped with the impurity at the lower concentration on one surface of the substrate. Then the exposed lower concentrated impurity layer is polished to provide the substrate for semiconductor device comprising double layers composed of higher and lower concentrated impurities.
    Type: Grant
    Filed: April 23, 1990
    Date of Patent: September 3, 1991
    Assignees: Shin-Etsu Handotai Co., Ltd., Naoetsu Electronics Company
    Inventor: Hirokazu Kimura
  • Patent number: 5041397
    Abstract: A method of forming a PSG layer on a semiconductor substrate containing semiconductor elements by chemical vapor deposition is characterized in that the concentration of the PSG layer is gradually increased from the substrate surface toward the uppermost surface of the PSG layer.
    Type: Grant
    Filed: February 3, 1989
    Date of Patent: August 20, 1991
    Assignee: SamSung Electronics Co., Ltd.
    Inventors: Nam-Yoon Kim, Si-Choon Park
  • Patent number: 5037777
    Abstract: The disclosed invention is a method for fabricating a multi-layer semiconductor device using selective planarization. In accordance with one embodiment of the invention, conductive members are formed on a substrate and a first insulating layer is deposited onto the substrate and the conductive members. A second insulating layer, which has a lower flow temperature than the flow temperature of the first layer, is deposited onto the first layer. A photoresist mask is patterned and developed to form a window which exposes an area between the conductive members. The device is preferentially etched such that only the exposed areas of the second insulating layer are removed, leaving the first insulating layer intact. An anisotropic etch is used to remove portions of the first insulating layer, leaving spacers along the edges of the conductive members. The photoresist mask is removed and a heating step is performed which flows the remaining portions of the second insulating layer, but not the first layer.
    Type: Grant
    Filed: July 2, 1990
    Date of Patent: August 6, 1991
    Assignee: Motorola Inc.
    Inventors: Thomas C. Mele, Wayne M. Paulson, Frank K. Baker, Michael P. Woo
  • Patent number: 5023197
    Abstract: A method for manufacturing a MOS transistor formed in a silicon block on insulator with convex rounded up edges, initially consisting in etching the block in a thin layer of silicon on insulator (SOI). In this method etching of the block comprises the following steps: forming at the position where it is desired to obtain the block a mask layer portion (3) having a thickness slightly higher than that of the SOI; depositing a second silicon layer (11) having a predetermined thickness; and anisotropically etching silicon until said insulator is apparent outside the mask layer portion.
    Type: Grant
    Filed: August 15, 1990
    Date of Patent: June 11, 1991
    Assignee: French State represented by the Minister of Post, Telecommunications and Space
    Inventors: Michel Haond, Jean Galvier
  • Patent number: 5021862
    Abstract: A semiconductor silicon wafer usable for integrated circuits has beveled portions unsymmetrically formed along circumferential edges of front and back surfaces thereof. An angle between an inclining surface of the beveled portion and a main surface on the back surface side is larger than that between the inclining surface of the beveled portion and the main surface on the front surface side. Therefore the circumferential edges are prevented from being chipped.
    Type: Grant
    Filed: April 6, 1990
    Date of Patent: June 4, 1991
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventor: Nobuyoshi Ogino
  • Patent number: 5001080
    Abstract: A semiconductor device including a substrate having a low substrate surface formed in the substrate with a first gentle slope from the substrate surface; a single crystalline layer formed on the low substrate surface nearly level with the substrate surface and having a gentle slope facing the first gentle slope; an optical semiconductor element is constructed using the single crystalline layer. An electronic semiconductor element is constructed using the substrate surface. A wiring layer connects electrodes of the optical semiconductor element and the electronic semiconductor element through the first and the second gentle slopes.
    Type: Grant
    Filed: October 26, 1987
    Date of Patent: March 19, 1991
    Assignee: Fujitsu Limited of 1015
    Inventors: Osamu Wada, Tatsuyuki Sanada, Shuichi Miura, Hideki Machida, Shigenobu Yamakoshi, Teruo Sakurai
  • Patent number: 4997790
    Abstract: A self-aligned contact is formed in a multi-layer semiconductor device. In one form, conductive members are formed overlying a substrate material and a first insulating layer is deposited overlying the substrate material and the conductive members. A film of material is deposited on the first insulating layer and the film of material is patterned to form a sacrificial plug in an area where a contact is to be made. A second insulating layer is deposited on the device, and the device is made substantially planar. The second insulating layer is etched back to expose the sacrificial plug. The sacrificial plug is removed by selectively etching the device such that the first and second insulating layers are left substantially unaltered. An anisotropic etch of the device is performed to expose an area of the substrate material on which a contact is to be made, and to simultaneously form sidewall spacers along edges of the conductive members.
    Type: Grant
    Filed: August 13, 1990
    Date of Patent: March 5, 1991
    Assignee: Motorola, Inc.
    Inventors: Michael P. Woo, Thomas C. Mele, Wayne J. Ray, Wayne M. Paulson
  • Patent number: 4990465
    Abstract: A method and apparatus for forming a monolithic surface emitting laser diode array by providing vertical partly light transmissive mirror surfaces opposite parabolic light reflective mirror surfaces formed adjacent the active buried layer of a heterostructure diode laser. The mirror surfaces are preferably formed using a mass-transport heating process. Other mirror shapes may be formed in accordance with the invention.
    Type: Grant
    Filed: November 1, 1989
    Date of Patent: February 5, 1991
    Assignee: Massachusetts Institute of Technology
    Inventors: Zong-Long Liau, James N. Walpole
  • Patent number: 4946800
    Abstract: The method for making an improved, surface-passivated and electrically isolated silicon device (including integrated circuit) comprises providing in a silicon wafer with a pn junction or other electronic rectifying barrier; and thermally oxidizing or ion-implanting oxygen or nitrogen into selected silicon surface regions to form electrically isolating grooves. The grooves have symmetrical, centrally rounded bottoms which are located within a few microns below the pn junction or rectifying barrier. Through these unique oxide/nitride forming conditions and curvature, symmetry, and proximity effects, novel passivation and isolation results obtain.
    Type: Grant
    Filed: August 6, 1973
    Date of Patent: August 7, 1990
    Inventor: Chou H. Li
  • Patent number: 4925809
    Abstract: A semiconductor wafer on which silicon or the like is epitaxially grown and p-type or n-type impurities are doped and which has at the rear surface except for the peripheral edge portion thereof a blocking film for preventing jumping out of impurities therefrom which causes auto-doping, thereby preventing silicon particles from being produced at the peripheral surface and preventing the semiconductor wafer from being contaminated by the silicon particles during the manufacturing of a semiconductor device.
    Type: Grant
    Filed: July 1, 1988
    Date of Patent: May 15, 1990
    Assignees: Osaka Titanium Co., Ltd., Kyushu Electronic Metal Co., Ltd.
    Inventors: Tetsujiro Yoshiharu, Haruo Kamise
  • Patent number: 4755479
    Abstract: With an increase of integration density in an integrated circuit, the channel length of MIS FET becomes shorter and shorter, which causes a hot carrier effect. To solve the problem, the doping profile of source/drain regions and doping amount must be precisely controlled such that a strong electric field is not generated in a transition region from channel to drain. To obtain this objective, the present invention discloses a method, in which reflowed sidewalls of doped silicate glass having a gentle slope are formed on both sides of a gate electrode, and the gate electrode and the sidewalls thus formed are used as a mask for ion implantation. The depth of ion implantation and the doping amount change gradually from the channel region to the drain region avoiding a generation of the strong electric field and thus alleviates the short channel trouble.
    Type: Grant
    Filed: February 4, 1987
    Date of Patent: July 5, 1988
    Assignee: Fujitsu Limited
    Inventor: Takao Miura
  • Patent number: 4705596
    Abstract: A method of planarizing a semiconductor layer by use of a plasma etch step which also etches vias having a tapered profile is made possible by selecting a conformal layer preferably of a different material than the material through which the via is to be provided such that a plasma etch will establish differing etch rates in the conformal and underlying layers.
    Type: Grant
    Filed: April 15, 1985
    Date of Patent: November 10, 1987
    Assignee: Harris Corporation
    Inventors: George E. Gimpelson, Cheryl L. Holbrook, Frederick N. Hause
  • Patent number: 4635090
    Abstract: A semiconductor device and the method of manufacturing the same are disclosed, the semiconductor device having a plurality of elements isolated by a groove having a gentle slope at the upper side wall, and a steep slope at the lower side wall. This groove provides low steps on its mouth and occupies a small area on the substrate, thus enabling an extremely high-density integrated circuit to be formed.
    Type: Grant
    Filed: May 13, 1985
    Date of Patent: January 6, 1987
    Assignee: Hitachi, Ltd.
    Inventors: Yoichi Tamaki, Tokuo Kure, Akira Sato, Hisayuki Higuchi
  • Patent number: 4630093
    Abstract: Identification of the front surface and whether the front surface has a mesa direction for wafers of compound semiconductors belonging to group III-V have a crystalline structure of the zinc blende type. The wafer has asymmetric peripheral edge with regard to a middle plane to denote the front surface. Another asymmetry as well as the edge asymmetry determines the front surface and the mesa direction on the surface. The other asymmetry is an orientation flat in a circular wafer. The asymmetry of the peripheral edge is given by the half round whose curvature changes in the direction of the thickness, two slanting parts whose lengths are different or a slanting part or a perpendicular part which are formed in succession in the direction of the thickness on the peripheral edge and so on.
    Type: Grant
    Filed: November 20, 1984
    Date of Patent: December 16, 1986
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Jun Yamaguchi, Osamu Shikatani