Abstract: A categorization of a particular semiconductor wafer based on void size is obtained from sigma data and T0.1% failure data that has been obtained from wafers subjected to isothermal testing. The sigma data and the T0.1% failure data for the particular wafer is compared to stored data corresponding to ranges for sigma and T0.1% data for each of a plurality of void categories, and the particular wafer is categorized based on the stored data. The T0.1% failure data is computed based on a T50% failure data and the sigma value, so that small sample sizes can be utilized to obtain the stored data.

Abstract: An object is to obtain a semiconductor wafer evaluation method and a semiconductor device manufacturing method having a reduced turn-around time and requiring no process apparatus and no dielectric breakdown characteristic evaluation device in evaluation of the dielectric breakdown characteristic of the oxide film. A sample wafer (1) is etched by using an SC-1 solution bath (2) to change process defects caused in the fabrication process including mirror polishing into pits. The number of pits is detected with a dust particle inspection system, and the dielectric breakdown characteristic of the sample wafer 1 can be evaluated by using the number of detected pits and previously obtained relations between the number of pits and the dielectric breakdown characteristic.

Abstract: A method for accurately and objectively evaluating stress migration effects on long term reliability of integrated circuits. A sample containing a conductive runner is fabricated according to a given fabrication process. The fabricated sample undergoes a heating step at a first temperature for a first time period to induce material interactions at an accelerated rate, followed by cooling the sample to a second temperature and maintaining the second temperature for a time of sufficient duration such that relaxation occurs. Then the sample undergoes a heating process at a third temperature for a time sufficient to nucleate a predetermined number of voids, followed by heating the sample runner at a fourth temperature, less than than the third temperature, to propagate the voids such that a maximum void size is determined. Void distribution is preferably monitored by optical and scanning electron microscopy.

Abstract: A method is described by which the mechanical strength of chips of semiconductor devices can be controlled by appropriate wafer finishing and sorted by knowledge of the finishing method and chip and wafer geometry. The control and sorting derive from a knowledge of the geometry of the striations remaining on the back of chips after the wafer-grinding finishing step.

Abstract: An arrangement and method for detecting sequential processing effects on products to be manufactured in a manufacturing process orders a first set of the products in a first specified processing sequence for a first process step in the manufacturing process. In order to prevent any positional trend created at one process step from being carried over into the next process step, the first set of the products is re-ordered into a second, different specified processing sequence for a second process step in the manufacturing process. Data regarding responses of the first set of the products to the process steps are extracted. The extracted data are correlated with the first and second processing sequences and data analysis is performed on the correlated extracted data.

Abstract: A method for co-registering a semiconductor wafer (14) undergoing work in one or more blind process modules (10), (12) requires a means (16), (18) for consistently and repeatably registering the semiconductor wafer (14) to each process module (10), (12). Given this consistent and repeatable singular wafer registration means (16), (18), the location of the coordinate axes of each process module (10), (12) is determined with respect to the position of the semiconductor wafer (14) that is registered therein.

Abstract: A method for hydrogen treatment of FETs for use in hermetically sealed packages is disclosed. FETs such as GaInAs HEMTs are treated before hermetic packaging by heating them in a hydrogen atmosphere until their drain currents degrade, and then continuing to heat them until their drain currents are restored. The HEMTs' drain currents are monitored and the process is continued until the currents stabilize. Thereafter the devices' temperature is lowered to the desired operating temperature and their drain currents are measured. If the drain currents after treatment are close enough to the current levels before treatment, the devices are selected; otherwise they are rejected.

Abstract: The evaluation of the oxide film dielectric breakdown voltage of a silicon semiconductor single crystal is caried out by cutting a wafer out of the single crystal rod, etching the surface of the wafer with the mixed solution of hydrofluoric acid and nitric acid thereby relieving the wafer of strain, then etching the surface of the wafer with the mixed solution of K.sub.2 Cr.sub.2 O.sub.7, hydrofluoric acid, and water thereby inducing occurrence of pits and scale-like patterns on the surface, determining the density of the scale-like patterns, and computing the oxide film dielectric breakdown voltage by making use of the correlating between the density of scale-like patterns and the oxide film dielectric breakdown voltage. This fact established the method of this invention to be capable of effecting an evaluation equivalent to the evaluation of the oxide film dielectric breakdown voltage of a PW wafer prepared from the single crystal rod.

Abstract: A method and apparatus for detecting the presence of gaseous impurities, notably oxygen, in a gas mixture that flows over an IC wafer in an etcher during the etching process. The method is based upon the discovery that the ratio of the etch rate of spin-on-glass material to the etch rate of other materials, such as plasma-enhanced chemical vapor deposition (PECVD oxide) materials, varies in a predictable manner with the amount of oxygen contaminating the gas mixture. The standard ratio, in the absence of oxygen, is determined for a given set of processing conditions by first etching an SOG wafer, then etching a PECVD oxide material wafer, measuring the amount of material etched in each case, and from that calculating the respective etch rates, and finally taking the ratio of the two calculated etch rates. This standard ratio is used as the benchmark for future tests.

Abstract: The present invention provides for a burn-in test which is conducted on the wafer level, before the dies are separated into individual chips and packaged. In a preferred embodiment of the invention, a series of chips are each connected to an external current, ground, and/or alternate signal source(s) for burn-in. Generally, the method herein for a burn-in of a semiconductor die comprises the step of: (a) providing an electrical connection between a die on a semiconductor wafer and an external current source; (b) heating the semiconductor wafer; and (c) applying a common signal across the electrical connection to burn in the die. A preferred method herein provides a semiconductor wafer including a multiplicity of dies and wafer level test points, at least one layer of conductive lines overlying the semiconductor wafer, a means for connecting an individual conductive line to a test point on the wafer; and a means for connecting the conductive lines to an external signal source for exercising the dies.

Abstract: The method and apparatus of this invention for evaluation of a semiconductor production process effect the determination of the shallow pit density of a silicon wafer by predetermining the correlation between the average shallow pit density on a wafer surface obtained by microscopic observation and the average magnitude of a scattered light on the wafer surface obtained by the determination with the wafer surface inspection system operated in the haze mode, determining the average magnitude on the wafer surface of a scattered light for a silicon wafer treated by a semiconductor production process under evaluation, and analyzing the data found by the determination in combination with the correlation mentioned above.

Abstract: A novel technique for the real time monitoring of ion implant doses has been invented. This is the first real-time monitor to cover the high dosage range (10E13 to 10E16 ions/sq. cm.). The underlying principle of this new technique is the increase in the resistance of a metal silicide film after ion implantation. Measurement of this increase in a silicide film that has been included in a standard production wafer provides an index for correlation with the implanted ion dose.

Abstract: An apparatus and method for rapidly changing the temperature of a semiconductor wafer, in order to perform electrical tests or stress at elevated temperature, and then cool rapidly to ambient temperature. The apparatus is comprised of a wafer support 17, capable of supporting the wafer, mounted on top of a rapid thermal processing (RTP) illuminator 20 (lamps, preferably halogen), and including one or more probe needles 22, capable of contacting the wafer to perform electrical measurements. A semiconductor wafer 16 is placed upon the wafer support 17 and the RTP illuminator 20 located beneath is activated, rapidly elevating the wafer to the desired temperature. Electrical tests may be performed as desired during the process.

Abstract: A method is provided which includes on-chip identification of individual die. The first wafer sort includes the steps of programming a plurality of dice on a wafer, programming predetermined memory memory cells on each good die to identify the wafer on which that die is located, and storing the location of each good die in a file created for each wafer. Then, the plurality of dice are subjected to predetermined conditions. In the second wafer sort, predetermined memory cells on one die are accessed to determine the associated file of that die. The associated file is then loaded. Finally, the good dice are tested. In another embodiment, the first wafer sort includes identifying the first good die on the wafer. After the next good die on the wafer is found, that die is programmed to indicate the location of the proceeding good die. This programming step is repeated until the last good die on the wafer is programmed. Once again, the wafer is subjected to adverse conditions.

Abstract: A method for manufacturing semiconductor devices according to this invention, comprises the wafer manufacturing step of forming an integrated circuit with a redundant circuit in each of a plurality of chip areas on a semiconductor wafer and also forming at least one stress testing terminal that applies a stress testing voltage or stress testing signal to the interconnections other than those for power supply in the integrated circuit for each of the chip areas or for every certain number of the chip areas, the step of, after the wafer manufacturing step, screening failures by applying a specified stress testing control signal or stress voltage to a certain number of chip areas with the stress testing terminal in contact with a contact terminal of a tester in the wafer state, the step of, after the screening step, judging whether or not the electrical characteristics of each chip area are acceptable through die sort test, the step of remedying an integrated circuit in a chip area judged to be defective in the

Abstract: The present invention provides a method for manufacturing a highly reliable semiconductor device without waste by incorporating predetermined functions into a wafer in a wafer completion process, aging the wafer in a wafer aging process, distinguishing between non-defective and defective chips in a probe inspection process, separating chips in the wafer one by one in a dicing process, sorting out the chips into non-defective and defective chips in a selection process, then analyzing failure information and feeding back the result of the analysis to the wafer completion process in a feedback process, thereby quickly analyzing and repairing a failure process on reliability in the wafer completion process.

Abstract: A method of extracting an impurity profile from a diced semiconductor chip having cellular construction. The cells are arranged in a matrix the columns and rows of which have a defined column pitch a.sub.x and a defined row spacing a.sub.y. In accordance with the method, the diced chip is bevelled from its original surface to expose the cells. The two probes of a Spreading Resistance Profile (SRP) device are then placed in contact with the dopant regions of two cells in the same row of the matrix, the distance .DELTA.X between the probes being ma.sub.x, where m is an integer, and the total resistance R.sub.T between the probes is measured. The SRP device is then stepped through a plurality of rows in the matrix, contacting cells in the same two columns as in the case of the first measurement, thereby interactively generating a plurality of total resistance R.sub.T measurements. The total resistance R.sub.T measurements are then combined to obtain the doping profile of the dopant region.

Abstract: A method and structure for protecting an integrated circuit from electrostatic discharges are disclosed. A Schottky diode (22) is connected to an input bond pad (12) and to a MOSFET transistor (17) which is desired to be protected. The normally high breakdown voltage required to drive the Schottky diode (22) into conduction is reduced by providing a trigger transistor (24) for prematurely triggering the diode (22). When the base-collector junction of the common emitter configured trigger transistor (24) is driven into avalanche breakdown by the electrostatic discharge, charged carriers (60) are generated, and attracted by the Schottky diode (22). The base (54) of the trigger transistor (24) is biased during normal operations with a supply voltage, and during electrostatic discharges to a higher voltage by an inherent Zener diode (64).

Abstract: A "smooth" fine classification of varactor diodes according to their electrical parameters is achieved in the manufacturing process to provide groups of matched varactor diodes. The diodes are matched within a predetermined tolerance limit. The dice are picked up from the silicon wafer along a meander path generally perpendicular to the temperature gradient of the diffusion process steps applied to the wafer when the diodes were formed, mounted on a lead frame, bonded, encapsulated, removed from the lead frame, and measured.

Abstract: A structure is formed on an electronic integrated circuit by altering the electrical characteristics of a diffused region of a substrate through a contact hole (window) in an insulating layer, in proportion to the size of said contact hole, such that the resistance of the diffused region is changed in a known and predictable fashion and may be measured electrically, giving indirect but accurate evidence of contact size in a completely nondestructive fashion. The measurements may be made on completed devices. Method and structure are disclosed.

Abstract: An advantageous method of fabricating lasers adapted for use in a multichannel analog optical fiber communication system, e.g., a CATV system, is disclosed. A laser generally can be used in such a communication system only if it meets, inter alia, very stringent intermodulation specifications. To identify such lasers typically requires extensive testing. It has now been discovered that certain readily determinable parameters can be used to predict the intermodulation behavior of a given device. This discovery makes possible a simpler, and therefore less costly, process of identifying suitable lasers, resulting in a more economical method of making lasers for the stated application. The method comprises measuring the light versus current (L versus I) characteristic of a given laser, determining therefrom the first, second, and possibly higher, order derivatives of L with respect to I, and determining thereform a parameter that is a predictor of the distortion behavior of the laser.

Abstract: Method of determining contaminants in a semiconductor processing apparatus in which a high purity, high carrier lifetime semiconductor test wafer is processed and the degradation of its carrier lifetime is determined.

Abstract: A method for fabricating a composite semiconductor from a plurality of substantially identical individual semiconductor devices formed on a common semiconductor wafer includes testing the devices on the wafer to generate a positional mapping of acceptable and non-acceptable devices, dividing the wafer into a plurality of areas of arbitrary size, connecting corresponding contact pads on only the acceptable devices within a given area to each other via common conductive paths which are supported on a dielectric film covering the pads, the film having appropriately located holes filled with conductive material to electrically couple the common conductive paths and the underlying contact pads of only the acceptable devices. The devices within a given area are intercoupled in a manner to form an operational array; single or multiple arrays may be coupled together to form a composite package having common external contacts and heat sink supports.

Abstract: Prior to packaging, semiconductor lasers are purged by being subjected first to high temperature and high current simultaneously so as to suppress stimulated emission and stress the shunt paths which allow leakage current to flow around the active region. A prudent, but nonessential, second step is to lower the temperature and/or current so that the lasers emit stimulated emission (preferably strongly, near the peak output power), thereby stressing the active region. Lasers subjected to such a purge exhibit stabilized degradation rates in short times (of the order of a few hours) and provide a robust population which meets the performance criteria of long lifetime systems.