V-grooves Patents (Class 148/DIG168)
  • Patent number: 5882950
    Abstract: A fabrication method for a horizontal direction semiconductor PN junction array which can be achieved when an epitaxial layer is grown by a metalorganic chemical vapor deposition (MOCVD method) by introducing (or doping) a small amount of CCl.sub.4 or CBr.sub.4 gas, includes forming a recess on an N type GaAs substrate by using a non-planar growth, performing a growth method of a P type epitaxial layer on the N type GaAs substrate by a metalorganic chemical vapor deposition method, and forming a horizontal direction PN junction array of P-GaAs/N-GaAs or P-AlGaAs/N-GaAs by introducing a gas comprising CCl.sub.4 or CBr.sub.4 .
    Type: Grant
    Filed: December 27, 1996
    Date of Patent: March 16, 1999
    Assignee: Korea Institute Of Science And Technology
    Inventors: Suk-Ki Min, Seong-Il Kim, Eun Kyu Kim
  • Patent number: 5658818
    Abstract: A method of forming a capacitor includes, a) providing a substrate; b) etching into the substrate to provide a depression in the substrate, the depression having a sidewall which is angled from vertical; c) providing a conformal layer of hemispherical grain polysilicon within the depression and over the angled sidewall, the layer of hemispherical grain polysilicon less than completely filling the depression; and d) ion implanting the hemispherical grain polysilicon layer with a conductivity enhancing impurity. Preferred methods of providing the depression where the substrate comprises SiO.sub.2 include a dry, plasma enhanced, anisotropic spacer etch utilizing reactant gases of CF.sub.4 and CHF.sub.3 provided to the substrate at a volumetric ratio of 1:1, and facet sputter etching.
    Type: Grant
    Filed: August 18, 1995
    Date of Patent: August 19, 1997
    Assignee: Micron Technology, Inc.
    Inventors: Salman Akram, Charles Turner, Alan Laulusa
  • Patent number: 5602054
    Abstract: A dielectrically isolated island architecture in which the island is contoured inwardly to form one or more projections that penetrate a well separating two regions in the island to assure that the two regions will be electrically isolated without additional processing steps.
    Type: Grant
    Filed: September 21, 1994
    Date of Patent: February 11, 1997
    Assignee: Harris Corporation
    Inventor: James D. Beasom
  • Patent number: 5501996
    Abstract: A MOSFET semiconductor, erasable programmable ROM device on a lightly doped semiconductor substrate comprising field oxide regions in the semiconductor substrate. The field oxide regions extends down into sunken regions in the substrate through the openings. At least one of the field oxide regions is removed from the substrate to provide an opened one of the sunken regions in the substrate below the removed one of the field oxide regions. Ion implanted regions lie in the substrate below the openings. A gate oxide layer over the opened sunken region, and a floating gate over the gate oxide layer. Preferably, a tunnel oxide region is formed on the surface of the device with the floating gate overlying the tunnel oxide region to form an EEPROM device. The exposed sunken region has a V-shaped cross section sunken region extending deep into the substrate.
    Type: Grant
    Filed: December 14, 1994
    Date of Patent: March 26, 1996
    Assignee: United Microelectronics Corporation
    Inventors: Sheng-Hsing Yang, Jyh-Kuang Lin
  • Patent number: 5466616
    Abstract: A method of producing a reduced-size LDMOS transistor having reduced leakage and latch-up possibility by reducing the vertical projective area of the source electrodes of the LDMOS transistor, which is done by forming first trenches to reach a substrate of the LDMOS transistor.
    Type: Grant
    Filed: April 6, 1994
    Date of Patent: November 14, 1995
    Assignee: United Microelectronics Corp.
    Inventor: Sheng-Hsing Yang
  • Patent number: 5363800
    Abstract: This invention is a method for the controlled growth of single-crystal semiconductor-device-quality films of SiC polytypes on vicinal (0001) SiC wafers with low tilt angles. Both homoepitaxial and heteroepitaxial SiC films can be produced on the same wafer. In particular, 3C-SiC and 6H-SiC films can be produced within selected areas of the same 6H-SiC wafer.
    Type: Grant
    Filed: November 9, 1992
    Date of Patent: November 15, 1994
    Assignee: The United States of America as represented by the United States National Aeronautics and Space Administration
    Inventors: David J. Larkin, Powell, J. Anthony
  • Patent number: 5318663
    Abstract: A method of thinning SOI films for providing ultra-thin active device regions having excellent thickness uniformity and further having self-aligned isolation regions between the active device regions is disclosed. A substrate having an isolation layer formed thereon and further having a single crystal silicon layer formed upon the isolation layer is first provided. A thermal oxide layer is grown upon the silicon layer, patterned in desired regions corresponding to polish stop regions positioned between predetermined active device regions, and etched. The silicon layer is thereafter etched according to the patterned thermal oxide layer with a high selectivity etch, thereby creating grooves in the silicon layer.
    Type: Grant
    Filed: December 23, 1992
    Date of Patent: June 7, 1994
    Assignee: International Business Machines Corporation
    Inventors: Taqi N. Buti, Joseph F. Shepard
  • Patent number: 5262346
    Abstract: A method of forming a SOI integrated circuit includes defining thin silicon mesas by wet etching a device layer having the <100> orientation down to the underlying insulator so that the (111) crystal planes control the lateral etching, forming a nitride bottom polish stop in the bottom of the apertures by a low temperature CVD process, with nitride sidewalls on the (111) planes of the silicon mesas being susceptible to easy removal, so that no hard material is present during a chemical-mechanical polishing step to thin the device layer down to less than 1000 .ANG., and filling the apertures with a temporary layer of polysilicon to provide mechanical support to the edges of the device layer during the polishing operation.
    Type: Grant
    Filed: December 16, 1992
    Date of Patent: November 16, 1993
    Assignee: International Business Machines Corporation
    Inventors: Ahmet Bindal, James E. Currie
  • Patent number: 5196378
    Abstract: The invention relates to a method of scribing and separating dice from each other after fabrication in a semiconductor wafer in a manner such that active circuit regions in the dice reside as near to an edge of a die as possible. The wafer is anistropically etched through the active layer and into the substrate through an opening in the mask to form a generally V-shaped channel with the dice then being separated along a vertex of the channel. The dice are then positioned to abut each other in the form of a mosaic.
    Type: Grant
    Filed: March 25, 1991
    Date of Patent: March 23, 1993
    Assignee: Texas Instruments Incorporated
    Inventors: Kenneth E. Bean, John Powell, Jack W. Freeman, Robert D. McGrath
  • Patent number: 5145795
    Abstract: An improved high frequency dielectrically isolated (DIC) transistor (100) or integrated circuit is obtained by providing a highly doped single crystal semiconductor region (112) coupled to the device reference terminal (16') and extending between front (98) and rear (61) faces of the semiconductor die. This allows the reference terminal (16', 116) to be coupled to the package ground plane without use of wire bonds, thereby lowering the common mode impedance. The desired structure is formed in connection with DIC devices (100) by etching first (66) and second (77) nested cavities into a single crystal substrate (60). The cavities (66) form protruding islands (821, 822) of single crystal semiconductor having a height (80+68) about equal the final die thickness (110) and which, after conventional DIC processing using an oxide isolation layer (86) and a poly handle (88), are exposed by grinding away the poly handle (88) to expose the highly doped, single crystal reference terminal feed-through (112).
    Type: Grant
    Filed: June 25, 1990
    Date of Patent: September 8, 1992
    Assignee: Motorola, Inc.
    Inventors: Paul W. Sanders, Bernard W. Boland
  • Patent number: 5135879
    Abstract: One embodiment of the present invention provides an EPROM array having floating gate field effect transistors formed on the sidewalls of trenches formed in a semiconducting substrate. Simultaneous with the fabrication of these trench wall transistors, column lines are formed between the trenches to the top surface and in the bottom of the trenches which extend from one end to the other of the memory array.
    Type: Grant
    Filed: May 20, 1991
    Date of Patent: August 4, 1992
    Assignee: Texas Instruments Incorporated
    Inventor: William F. Richardson
  • Patent number: 5024966
    Abstract: A silicon-based laser mounting structure is disclosed which provides improved interconnection between a semiconductor optical device, such as a laser, and an external high frequency modulation current source, by reducing the presence of parasitic inductive elements in the interconnecting network. The structure includes a stripline transmission path formed by depositing metal conductive strips on the top and bottom surfaces of a silicon substrate. The conductive strips are coupled at one end to the external modulation current source. A thin film resistor is deposited between the second end of the top conductive strip and the semiconductor optical device. This thin film resistor is utilized to provide impedance matching between the optical device and the stripline. That is, for a laser with an impedance Z.sub.L, and a stripline designed to have an impedance Z.sub.S, the resistance R is chosen such that R+Z.sub.L =Z.sub.S.
    Type: Grant
    Filed: April 16, 1990
    Date of Patent: June 18, 1991
    Assignee: AT&T Bell Laboratories
    Inventors: Norman R. Dietrich, Ralph S. Moyer, Yiu-Huen Wong
  • Patent number: 5023196
    Abstract: A MOSFET having a back-side source contact and top-side gate and drain contacts is provided by a structure comprising superposed N.sup.+, N-,P-, N.sup.+ regions arranged between top and bottom surfaces of the semiconductor die. In a preferred implementation, two trenches are etched from the top surface to the P-, N.sup.+ interface. A buried P-, N.sup.+ short is provided in one trench and a gate dielectric and gate electrode are provided over the sidewall P- region exposed in the other trench. This creates a vertical MOSFET in which the N.sup.+ substrate forms the source region shorted to the P- body region in which the channel is created by the gate. Superior performance is obtained in RF grounded-source circuit applications.
    Type: Grant
    Filed: January 29, 1990
    Date of Patent: June 11, 1991
    Assignee: Motorola Inc.
    Inventors: Robert J. Johnsen, Paul W. Sanders
  • Patent number: 4997793
    Abstract: A relatively wide scribing channel is provided between the ends of each adjacent pair of diode array areas on a wafer to expose the epitaxial layer of the wafer. A scribing groove is then scribed in the scribing channel to define a cleavage line along which the array areas are separated.
    Type: Grant
    Filed: November 21, 1989
    Date of Patent: March 5, 1991
    Assignee: Eastman Kodak Company
    Inventor: Scott D. McClurg
  • Patent number: 4914058
    Abstract: Disclosed is a process for making a DMOS, including lining a groove with a dielectric material to form an inner groove having sidewalls extending through the bottom of the first groove, and lining the inner groove with a dielectric material to obtain increased thickness of the gate dielectric on the sidewalls of the inner groove.
    Type: Grant
    Filed: December 29, 1987
    Date of Patent: April 3, 1990
    Assignee: Siliconix Incorporated
    Inventor: Richard A. Blanchard
  • Patent number: 4889827
    Abstract: A method for the manufacture of a MESFET comprising a gate that is self-aligned both with respect to the source and drain regions as well as with respect to the appertaining metallizations, whereby a first metal layer (21), a first dielectric layer (31), and a first lacquer mask layer are applied following doping of the carrier substrate. A trench producing an outer recess in the doping layer (11) is formed by anisotropic etching. A second dielectric layer is isotropically deposited and is anisotropically re-etched except for spacers (51/52) whereby an inner recess (double recess) is produced in the doping layer and, finally, the gate metal (22) is applied.
    Type: Grant
    Filed: September 22, 1988
    Date of Patent: December 26, 1989
    Assignee: Siemens Aktiengesellschaft
    Inventor: Josef Willer
  • Patent number: 4883771
    Abstract: A method of producing a semiconductor laser which comprises sequentially depositing a lower cladding layer, an active layer, and an upper cladding layer on a substrate, forming a V shaped groove in the deposited layers at least reaching the lower cladding layer, the groove extending in a direction perpendicular to the direction between the surfaces that are to become resonator end surfaces, growing a semiconductor layer having a larger energy band gap than that of the active layer in the groove while retaining the V shaped groove, and cleaving the substrate and layers along the V shaped groove.
    Type: Grant
    Filed: March 31, 1989
    Date of Patent: November 28, 1989
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hisao Kumabe, Wataru Susaki
  • Patent number: 4859621
    Abstract: A wafer with a <100> orientation comprises a strongly doped N layer (substrate), a lightly doped N layer (middle layer) and a lightly doped P layer (top layer). A strongly doped N layer (source layer) is diffused into most of the top layer. An oxide layer is grown. A V groove with a flat bottom is anisotropically etched through openings in the oxide layer. The V groove is etched through the source layer and most of the P layer. The bottom of the groove initially is at a level above the junction between the top layer and the middle layer. Exposure to beam of phosphorous ions forms a shallow implanted channel region proximate the walls of the groove. An unwanted implanted region along the bottom of the groove is also formed. A second anisotropic etch, through the same oxide mask, deepens the groove bottom to a point below the junction, removing the unwanted portion of the implanted region along the groove bottom. The implanted concentration of the channel is later reduced as the gate oxide is formed.
    Type: Grant
    Filed: February 1, 1988
    Date of Patent: August 22, 1989
    Assignee: General Instrument Corp.
    Inventor: Willem G. Einthoven
  • Patent number: 4849368
    Abstract: Disclosed is a method of producing a compound semiconductor device comprising an enhancement-mode transistor and a depletion-mode transistor, each of which has a heterojunction and utilizes a two-dimensional electron gas. The method of producing the device comprises the steps of: forming an undoped GaAs channel layer on a semi-insulating GaAs substrate; forming an N-type AlGaAs electron-supply layer so as to form the heterojunction; forming an N-type GaAs layer; forming an AlGaAs layer; selectively etching the AlGaAs layer to form a recess; performing an etching treatment using an etchant which can etch rapidly GaAs and etch slowly AlGaAs to form simultaneously grooves for gate electrodes of the enhancement-mode transistor and the depletion-mode transistor, the bottoms of the grooves being in the N-type AlGaAs layer and the distance between the bottoms being equal to the thickness of the AlGaAs layer; and forming simultaneously the gate electrodes in the grooves.
    Type: Grant
    Filed: January 21, 1988
    Date of Patent: July 18, 1989
    Assignee: Fujitsu Limited
    Inventors: Yoshimi Yamashita, Kinjiro Kosemura, Hidetoshi Ishiwari, Sumio Yamamoto, Shigeru Kuroda
  • Patent number: 4683643
    Abstract: A vertical metal oxide semiconductor field effect transistor has a trench substantially vertically formed in a major surface of a semiconductor substrate, a first conductive layer formed in a predetermined region including a side wall surface of the trench on a gate insulating film, lower and upper diffusion layers formed in the bottom of the trench and a surface layer of the semiconductor substrate, preferably a channel doped region formed in the semiconductor substrate between the upper and lower diffusion layers, and a second conductive layer formed in contact with the lower diffusion layer in the bottom of the trench and insulated from the first conductive layer so as to fill the trench. The first conductive layer serves as a gate electrode, and the diffusion layers serves as source/drain regions, respectively. A method of manufacturing the vertical MOSFET is also proposed.
    Type: Grant
    Filed: July 16, 1985
    Date of Patent: August 4, 1987
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Shigeru Nakajima, Kazushige Minegishi, Kenji Miura, Takashi Morie, Toshifumi Somatani
  • Patent number: 4670969
    Abstract: A method of making a silicon diaphragm pressure sensor includes forming an oxide film on one surface of a monocrystalline silicon substrate. A polycrystalline silicon layer is formed on the oxide film. The oxide film may be partly removed before the formation of the polycrystalline silicon layer. The polycrystalline silicon layer is heated and melt to recrystallize the same, thereby converting the polycrystalline silicon layer into a monocrystalline silicon layer. On the monocrystalline silicon layer may be epitaxially grown an additional monocrystalline silicon layer. By using the oxide film as an etching stopper, a predetermined portion of the substrate is etched over a range from the other surface of the substrate to the oxide film, thereby providing a diaphragm of the pressure sensor.
    Type: Grant
    Filed: January 25, 1985
    Date of Patent: June 9, 1987
    Assignee: Hitachi, Ltd.
    Inventors: Kazuji Yamada, Yutaka Kobayashi, Kanji Kawakami, Satoshi Shimada, Masanori Tanabe, Shigeyuki Kobori
  • Patent number: 4635090
    Abstract: A semiconductor device and the method of manufacturing the same are disclosed, the semiconductor device having a plurality of elements isolated by a groove having a gentle slope at the upper side wall, and a steep slope at the lower side wall. This groove provides low steps on its mouth and occupies a small area on the substrate, thus enabling an extremely high-density integrated circuit to be formed.
    Type: Grant
    Filed: May 13, 1985
    Date of Patent: January 6, 1987
    Assignee: Hitachi, Ltd.
    Inventors: Yoichi Tamaki, Tokuo Kure, Akira Sato, Hisayuki Higuchi
  • Patent number: 4577395
    Abstract: A method of manufacturing a semiconductor memory device having a trench memory capacitor. First masks are formed on an element forming region of a semiconductor substrate formed of the element forming region and an element isolation region. A film formed of a different material from that of the first masks is deposited and is etched by anisotropic dry etching to leave second masks around the first mask. The semiconductor substrate is selectively etched using the first and second masks as an etching mask so as to form a first groove in the element isolation region. An insulation film is buried in the first groove. A portion of the first mask, formed at least above memory capacitor forming regions in the element forming region, is removed by etching, thereby forming a third mask on a portion excluding the memory capacitor forming region.
    Type: Grant
    Filed: December 13, 1984
    Date of Patent: March 25, 1986
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tadashi Shibata
  • Patent number: 4523964
    Abstract: The invention relates to a process for producing silicon diaphragm pressure transducers, and to pressure transducers so produced, which will operate in high temperature applications above 150.degree. C. by properly insulating the strain gauges from the diaphragm. This is achieved by utilizing two properly oriented silicon wafers which are joined together by a two-step diffusion technique, which includes the diffusion bonding of one boron doped wafer surface into the other wafer surface previously oxide coated, at greatly reduced pressures and temperatures than heretofore used. This simultaneous diffusion takes place because of prior contouring or the forming of relief channels into one of the bonded surfaces, and because only one joined surface is oxide coated, thus reducing process times substantially. That is, there is a continuous diffusion of boron into the boron oxide coated surface resulting in a boron rich layer of great uniformity.
    Type: Grant
    Filed: March 30, 1983
    Date of Patent: June 18, 1985
    Assignee: Becton, Dickinson and Company
    Inventors: L. Bruce Wilner, Herbert V. Wong