Vacuum Deposition (includes Molecular Beam Epitaxy Patents (Class 148/DIG169)
  • Patent number: 5907792
    Abstract: A method of forming a silicon nitride layer or film on a semiconductor wafer structure includes forming a silicon nitride layer on the surface of a wafer structure using a molecular beam of high purity elemental Si and an atomic beam of high purity nitrogen. In a preferred embodiment, a III-V compound semiconductor wafer structure is heated in an ultra high vacuum system to a temperature below the decomposition temperature of said compound semiconductor wafer structure and a silicon nitride layer is formed using a molecular beam of Si provided by either thermal evaporation or electron beam evaporation, and an atomic nitrogen beam provided by either RF or microwave plasma discharge.
    Type: Grant
    Filed: August 25, 1997
    Date of Patent: May 25, 1999
    Assignee: Motorola,Inc.
    Inventors: Ravi Droopad, Jonathan K. Abrokwah, Matthias Passlack, Zhiyi Jimmy Yu
  • Patent number: 5834361
    Abstract: In a method of forming a II-VI compound semiconductor thin film on an InP substrate, a layer of III-V compound semiconductor mixed crystal is first formed on the InP substrate. The desorption rate of a group V element constituting the III-V compound semiconductor mixed crystal at a decomposition temperature of a native oxide layer formed on a surface of the III-V compound semiconductor mixed crystal layer is lower than a desorption rate of P of the InP substrate at a decomposition temperature of a native oxide layer formed on a surface of the InP substrate. A II-VI compound semiconductor thin film layer is formed on the first III-V compound semiconductor mixed crystal layer.
    Type: Grant
    Filed: April 10, 1996
    Date of Patent: November 10, 1998
    Assignee: NEC Corporation
    Inventors: Kouichi Naniwae, Toru Suzuki
  • Patent number: 5705408
    Abstract: A semiconductor integrated circuit device including: an off-substrate having a semiconductor surface with a plurality of steps each having a height of one monolayer and extending in one direction; a wiring layer formed on the semiconductor surface of the off-substrate and made of semiconductor material, the wiring layer including a plurality of conductive stripe regions and high resistance strip regions disposed in a stripe pattern, each stripe region extending in a direction parallel with the steps, and the conductive stripe regions and the high resistance stripe regions both having lattice structures identical to those of underlying surfaces; and semiconductor elements formed on the wiring layer and electrically connected to the conductive stripe regions, the semiconductor elements including semiconductor regions with lattice structures identical to those of the conductive stripe regions.
    Type: Grant
    Filed: September 25, 1996
    Date of Patent: January 6, 1998
    Assignee: Fujitsu Limited
    Inventors: Toshihiko Mori, Yoshiaki Nakata
  • Patent number: 5550084
    Abstract: An improved method is provided for fabricating a metal silicide upon a semiconductor substrate. The method advantageously places a film of metal nitride upon the metal layer. The metal nitride layer and metal layer are sputter deposited within the same chamber without removing the substrate from the vacuum so as to prevent oxygen or moisture from contaminating the metal layer and causing oxides to form thereon. Furthermore, the metal nitride layer is reactively sputter deposited in a nitrogen/argon ambient to allow precise amounts of nitrogen to be deposited across uneven surface topography directly adjacent to the underlying metal layer. Excess nitrogen purposefully deposited within the metal nitride layer consumes a controlled depth of metal bond sites within the underlying metal layer so as to limit the amount of silicidation from underlying silicon or polysilicon into the metal thereby substantially eliminating or minimizing silicide shorting problems.
    Type: Grant
    Filed: January 17, 1995
    Date of Patent: August 27, 1996
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Mohammed Anjum, Ibrahim K. Burki, Craig W. Christian
  • Patent number: 5480818
    Abstract: A crystal silicon film deposited on an insulating film made of a binary system material or a binary system semiconductor film formed by an atomic layer deposition method has a grain as large as approximately 200 nm. Thus, the mobility of carriers is increased. The crystal silicon thereof is grown within a temperature range of 250.degree. C. to 400.degree. C. Accordingly, when a planar type thin film transistor, an inverted stagger type thin film transistor or a stagger type thin film transistor is formed using crystal silicon formed on these films made of a binary system material, transistor characteristics thereof are improved.
    Type: Grant
    Filed: February 9, 1993
    Date of Patent: January 2, 1996
    Assignee: Fujitsu Limited
    Inventors: Tomotaka Matsumoto, Jun Inoue, Teruhiko Ichimura, Yuji Murata, Junichi Watanabe, Yoshio Nagahiro, Mari Hodate, Kenichi Oki, Masahiro Okabe
  • Patent number: 5346851
    Abstract: A quantum effect device implementation of the Shannon Decomposition Function in the form of a Shannon Cell is provided in which a first quantum dot logic unit (50) is coupled between the X input and the output of the Shannon Cell. A second quantum dot logic unit (52) is coupled between the Y input and the output of the Shannon Cell. The control input to the Shannon Cell is coupled to both the first and second quantum dot logic units (50 and 52) such that current flows through the appropriate quantum dot logic unit (50 or 52) depending upon the logic state of the control input.
    Type: Grant
    Filed: November 20, 1992
    Date of Patent: September 13, 1994
    Assignee: Texas Instruments Incorporated
    Inventors: John N. Randall, Gary A. Frazier, Rajni J. Aggarwal
  • Patent number: 5308444
    Abstract: The invention is predicated upon the discovery by applicants that exposure of a Ge surface to arsenic produces a drastic change in the step structure of the Ge surface. Subsequent exposure to Ga and growth of GaAs produces three-dimensional growth and a high threading dislocation density at the GaAs/Ge interface. However exposure of the Ge surface to Ga does not substantially change the Ge step structure, and subsequent growth of GaAs is two-dimensional with little increase in threading dislocation density. Thus a high quality semiconductor heterostructure of gallium arsenide on germanium can be made by exposing a germanium surface in an environment substantially free of arsenic, depositing a layer of gallium on the surface and then growing a layer of gallium arsenide. The improved method can be employed to make a variety of optoelectronic devices such as light-emitting diodes.
    Type: Grant
    Filed: May 28, 1993
    Date of Patent: May 3, 1994
    Assignee: AT&T Bell Laboratories
    Inventors: Eugene A. Fitzgerald, Jr., Jenn-Ming Kuo, Paul J. Silverman, Ya-Hong Xie
  • Patent number: 5186718
    Abstract: A processing system for workpieces such as semiconductor wafers is disclosed which incorporates multiple, isolated vacuum stages between the cassette load lock station and the main vacuum processing chambers. A vacuum gradient is applied between the cassette load lock and the main processing chambers to facilitate the use of a very high degree of vacuum in the processing chambers without lengthy pump down times. Separate robot chambers are associated with the vacuum processing chambers and the load lock(s). In addition, separate transport paths are provided between the two robot chambers to facilitate loading and unloading of workpieces. Pre-treatment and post-treatment chambers may be incorporated in the two transport paths.
    Type: Grant
    Filed: April 15, 1991
    Date of Patent: February 16, 1993
    Assignee: Applied Materials, Inc.
    Inventors: Avi Tepman, Howard Grunes, Sasson Somekh, Dan Maydan
  • Patent number: 5182221
    Abstract: A method of filling a recess so that it is flat with a material by a bias ECR-CVD process is capable of depositing the recess with the material without resulting in the increase in the aspect ratio of the recess with the progress of the deposition process and without forming any voids in the material filling up the recess. A method in accordance with the present invention is characterized in that the bias ECR-CVD process is controlled so as to meet a condition expressed by: R=2y/x, where R is the deposition rate ratio, namely, the ratio of a vertical deposition rate at which the material is deposited on the vertical side surface of the recess to a deposition rate at which the material deposited on the horizontal bottom surface of the recess, x is the width of the recess and y is the depth of the recess.
    Type: Grant
    Filed: June 12, 1991
    Date of Patent: January 26, 1993
    Assignee: Sony Corporation
    Inventor: Junichi Sato
  • Patent number: 5120393
    Abstract: Flatness of atomic-accuracy is achieved in an MBE epitaxial growth process by imparting kinetic energy to atoms absorbed on a substrate by means of irradiation by ion-beam for surface bombardment. Ion-beam surface bombardment may also be used for evaluation. The molecular-beam for epitaxial growth and the ion bombardment for surface energization and surface evaluation may all be operated in a pulse mode and synchronized so that evaluation and growth are conducted alternately while growth and energization are conducted simultaneously.
    Type: Grant
    Filed: January 10, 1991
    Date of Patent: June 9, 1992
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Minoru Kubo, Tadashi Narusawa
  • Patent number: 5094974
    Abstract: For the growth of strain-layer materials and high quality single and multiple quantum wells, the instantaneous control of growth front stoichiometry is critical. The process of the invention adjusts the offset or phase of MBE control shutters to program the instantaneous arrival or flux rate of In and As.sub.4 reactants to grow InAs. The interrupted growth of first In, then As.sub.4, is also a key feature.
    Type: Grant
    Filed: February 28, 1990
    Date of Patent: March 10, 1992
    Assignee: The United States of America as represented by the Administrator of the National Aeronautics and Space Administration
    Inventors: Frank J. Grunthaner, John K. Liu, Bruce R. Hancock
  • Patent number: 5093278
    Abstract: According to this invention, a first cladding layer of a first conductivity type, an active layer, a second cladding layer of a second conductivity type, and a cap layer much more susceptible to side etching than the second cladding layer susceptible to side etching than the second cladding layer are sequentially grown on a (100) crystal plane of a semiconductor substrate of the first conductivity type, and a stripe-like mask extending in a <011> direction is formed on the grown substrate with respect to each layer of the stacked substrate. This etching is performed in a crystal orientation for forming a reverse triangular mesa. However, since the cap layer is made of a material susceptible to side etching, a rounded mesa is formed. Thereafter, when a burying layer is formed on the etched portion by a vapor phase epitaxy method, the burying layer can be made to have a flat surface depending on crystal orientations.
    Type: Grant
    Filed: September 21, 1990
    Date of Patent: March 3, 1992
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Hidenori Kamei
  • Patent number: 5080870
    Abstract: A furnace having a sublimating section, a cracking section oriented off axis to the sublimating section, and a valve for controlling flux between the sections. The valve includes an annular plug having at least one longitudinal slot. The plug is retractable from a fully closed position where the slot is completely covered, to a fully open position where the slot is completely exposed. The slot becomes increasingly exposed as the plug is moved from the fully closed position to the fully opened position, thereby increasing flux from the sublimating section to the cracking section.
    Type: Grant
    Filed: August 28, 1989
    Date of Patent: January 14, 1992
    Assignee: Board of Regents, The University of Texas System
    Inventors: Ben G. Streetman, Terry J. Mattord, Dean P. Neikirk
  • Patent number: 5028561
    Abstract: P-type doping of a molecular beam epitaxy (MBE) grown substrate composed of a Group II-VI combination is accomplished by forming a flux from a Group II-V combination, and applying the flux to the substrate at a pressure less than about 10.sup.-6 atmosphere. The Group II material is selected from Zn, Cd, Hg and Mg, the Group V material from As, Sb and P, and the Group VI material from S, Se and Te. The Group II-V dopant combination is preferably provided as a compound formed predominantly from the Group II material, and having the formulation X.sub.3 Y.sub.2, where X is the Group II material and Y is the Group V material. The doping concentration is controlled by controlling the temperature of the Group II-V combination. Metal vacancies in the lattice structure are tied up by the Group II constituent of the dopant combination, leaving the Group V dopant available to enter the Group VI sublattice and produce a p-type doping.
    Type: Grant
    Filed: June 15, 1989
    Date of Patent: July 2, 1991
    Assignee: Hughes Aircraft Company
    Inventors: G. Sanjiv Kamath, Owen K. Wu
  • Patent number: 5025751
    Abstract: A solid film forming apparatus, e.g., an MO-MBE (Metal-Organic Molecular Beam Epitaxy) apparatus, wherein evacuatable containers isolated from a growth chamber by a switching device and connected to raw material gas introduction pipings are provided between the growth chamber for a solid film, e.g., a compound semiconductor, and raw material gas introduction pipings. Growth of the solid film is controlled by opening and closing the switching device and evacuating the container at least while the switching device is closed during the growth of the solid film. An undesired influence on the growing film due to residual gas in the containers which are not used for growth can be prevented and, hence, interception and introduction of the raw material gas into the growth chamber can be performed with remarkably high controllability, and films of superior abruptness of the interface between films, e.g., the heterojunction of the compound semiconductor, can be obtained.
    Type: Grant
    Filed: June 14, 1989
    Date of Patent: June 25, 1991
    Assignee: Hitachi, Ltd.
    Inventors: Shinichiro Takatani, Shigeo Goto, Masahiko Kawata, Kenji Hiruma
  • Patent number: 5026655
    Abstract: For improvement in a transit time of electrons, there is disclosed a heterojunction field effect transistor fabricated on a semi-insulating GaAs substrate, comprising a first layer overlying the semi-insulating substrate and formed of a high-purity GaAs, a second layer overlying the first layer and formed of an n-type AlGaAs which is smaller in electron affinity than the high-purity GaAs, a source region penetrating from the first layer into the second layer so as to be in contact with the active channel layer formed in the first layer and formed of an gallium-rich AlGaAs, a drain region, and a gate electrode formed on the second layer, an energy gap takes place between the source region and the first layer due to a lower edge of the conduction band thereof higher in energy level than that of the high-purity GaAs, thereby accelerating electrons supplied from the source region to the active channel layer.
    Type: Grant
    Filed: September 21, 1989
    Date of Patent: June 25, 1991
    Assignee: NEC Corporation
    Inventor: Keiichi Ohata
  • Patent number: 5013683
    Abstract: A method for growing a superlattice structure on a substrate. First, a periodic array of monoatomic surface steps are created on the surface of the substrate at an area to have the superlattice structure grown thereon. There is apparatus for creating a beam of a material being input thereto and for selectively including or not including respective ones of a plurality of materials within the beam. The beam is directed at the steps of the substrate. Finally, logic causes control apparatus to include and not include respective ones of the materials within the beam in a pre-established pattern of time periods which will cause the materials to be deposited on the steps in a series of stacked monolayers. Tilted Superlattices (TSLs) and Coherent Tilted Superlattices (CTSLs) are created. The method can create pseudo ternary semiconductor alloys as part of a CTSL by employing at least two binary compound semiconductor alloys in the deposition process.
    Type: Grant
    Filed: January 23, 1989
    Date of Patent: May 7, 1991
    Assignee: The Regents of the University of California
    Inventors: Pierre M. Petroff, Herbert Kroemer
  • Patent number: 4977103
    Abstract: The presence of oval defects on MBE-grown compound semiconductor (e.g., GaAs, InP, or InGaAs) epitaxial layers has proven to be a serious obstacle to the use of such material for the manufacture of integrated circuits (ICs), even though the use of such material potentially could result in ICs having superior performance. One particularly prevalent type of oval defect is generally referred to as .alpha.-type. It has now been discovered that compound semiconductor epitaxial layers that are essentially free of .alpha.-type oval defects can be grown by MBE if first at least a portion of the Ga and/or In metal crucible is coated with an appropriate second metal. The second metal is chosen from the group of metals that are wetted by the first metal and that are less electronegative than the first metal. Aluminum is a currently preferred second metal.
    Type: Grant
    Filed: August 24, 1989
    Date of Patent: December 11, 1990
    Assignee: AT&T Bell Laboratories
    Inventor: Naresh Chand
  • Patent number: 4960720
    Abstract: In molecular beam epitaxial growth of GaAs substrate, a compound semiconductor thin film having Ga and As is grown by Ga beam and As beam in MBE chamber and then the substrate is transferred to an annealing chamber where the substrate is annealed under As vapor pressure. The above process is repeated to a predetermined layer level whereby it eliminates divergence from stoichiometric.
    Type: Grant
    Filed: August 24, 1987
    Date of Patent: October 2, 1990
    Inventor: Masafumi Shimbo
  • Patent number: 4939102
    Abstract: 36 We have discovered the III-V semiconductor layers with previously unattainably high effective hole concentrations can be produced by molecular growth processes (e.g. MBE) if an amphoteric dopant such as Be is used and if, during the growth of the highly doped III-V layer, the substrate is maintained at a temperature T.sub.g that is substantially lower than customarily used. For instance, a InGaAs layer with effective hole concentration 1.0.times.10.sup.20 cm.sup.-3 was grown at T.sub.g =450.degree. C., and a GaAs layer with effective hole concentration of 1.0.times.10.sup.20 cm.sup.-3 was grown at T.sub.g of 475.degree. C. The heavily doped III-V layers can be of device grade and can usefully be part of electronic devices such as high speed bipolar transistors.
    Type: Grant
    Filed: January 17, 1989
    Date of Patent: July 3, 1990
    Assignee: American Telephone and Telegraph Company
    Inventors: Robert A. Hamm, Roger J. Malik, Morton B. Panish, John F. Walker
  • Patent number: 4925810
    Abstract: A compound semiconductor device comprises a substrate formed from a single crystal of silicon, a layer of an insulator formed on a portion of a surface of the substrate, at least one layer of a high resistance compound semiconductor formed on the insulator layer, and at least one layer of a single crystal of a compound semiconductor formed on a different portion of the substrate surface from the insulator layer. The device can be manufactured by forming an insulator layer on one portion of a surface of a single crystal silicon substrate, and growing a compound semiconductor by epitaxy on the insulator layer and on the different portion from the insulator layer. One of useful applications is a hybrid semiconductor device having a compound semiconductor formed from e.g. GaAs on a silicon substrate.
    Type: Grant
    Filed: August 24, 1989
    Date of Patent: May 15, 1990
    Assignee: Kabushiki Kaisha Toyota Chuo Kenkyusho
    Inventors: Hiroyuki Kano, Takatoshi Kato, Masafumi Hashimoto
  • Patent number: 4920069
    Abstract: Submicron structure fabrication is accomplished by providing vapor chemical erosion of a compound crystal by suppressing the more volatile elements so that the less volatile element is provided with an anti-agglomeration and erosion rate limiting capability which can be followed by subsequent regrowth in the same environment. The erosion is sensitive to crystallographic orientation.
    Type: Grant
    Filed: April 15, 1988
    Date of Patent: April 24, 1990
    Assignee: International Business Machines Corporation
    Inventors: Eric R. Fossum, Peter D. Kirchner, George D. Pettit, Alan C. Warren, Jerry M. Woodall
  • Patent number: 4916089
    Abstract: In order, in the epitaxial production of semiconductor products and of articles provided with a layer, to be able to make the junction between the layers applied to the substrates atomically sharp, it is important to be able to change the gas mixture, to be introduced into a pulsed reactor or MBE reactor, rapidly, accurately and without losses in respect of quantity and of composition. To this purpose, each of the gases to be introduced into the reactor is conveyed to a separate gas pipette and thereafter the content of the gas pipette is cyclically passed, by means of a pressure differential, into the pulse reactor, with the composition of the mixture being changed per one or more cycles.
    Type: Grant
    Filed: September 2, 1988
    Date of Patent: April 10, 1990
    Assignee: Stichting Katholieke Universiteit
    Inventors: Jaap Van Suchtelen, Lodevicus J. Giling, Josephus E. M. Hogenkamp
  • Patent number: 4910167
    Abstract: A GaAs containing nucleation layer is deposited upon Si, Ge/Si, or other single crystal substrate from triethyl gallium (TEG). Deposition from TEG allows a lower deposition temperature which provides a low level of substrate contamination and improved surface morphology.
    Type: Grant
    Filed: November 13, 1987
    Date of Patent: March 20, 1990
    Assignee: Kopin Corporation
    Inventors: Jhang W. Lee, Richard E. McCullough, Jack P. Salerno
  • Patent number: 4894349
    Abstract: A process for forming a vapor-phase epitaxial growth layer on a silicon wafer having a buried layer of a high As or B concentration. This vapor-phase epitaxial growth process is performed in two steps of (i) performing a vapor-phase epitaxial growth at a relatively low temperature by using a reaction gas containing at least one kind selected from a group consisting of SiH.sub.x F.sub.4-x (x=0 to 3) and Si.sub.2 H.sub.x F.sub.6-x (x=0-5) and at least one kind selected from a group consisting of SiH.sub.4 and Si.sub.2 H.sub.6, and (ii) performing a vapor-phase epitaxial growth under a condition which allows a higher growth rate that in the step (i) by using a reaction gas containing SiH.sub.4 or Si.sub.2 H.sub.6 which may or may not be accompanied with silane fluoride.
    Type: Grant
    Filed: December 15, 1988
    Date of Patent: January 16, 1990
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshihiko Saito, Yoshiaki Matsushita
  • Patent number: 4885258
    Abstract: There is provided an improved thin-film transistor of which a principal semiconducting layer comprises a layer composed of an amorphous material prepared by (a) introducing (i) a gaseous substance containing atoms capable of becoming constituents for said layer into a film forming chamber having a substrate for thin-film transistor through a transporting conduit for the gaseous substance and (ii) a gaseous halogen series substance having a property to oxidize the gaseous substance into the film forming chamber through a transporting conduit for the gaseous halogen series oxidizing agent, (b) chemically reacting the gaseous substance and the gaseous halogen series agent in the film forming chamber in the absence of a plasma to generate plural kinds of precursors containing exited precursors and (c) forming said layer on the substrate with utilizing at least one kind of those precursors as a supplier.
    Type: Grant
    Filed: November 1, 1988
    Date of Patent: December 5, 1989
    Assignee: Canon Kabushiki Kaisha
    Inventors: Shunichi Ishihara, Hirokazu Ootoshi, Masaaki Hirooka, Junichi Hanna, Isamu Shimizu
  • Patent number: 4883770
    Abstract: A molecular beam epitaxy (MBE) process in which some portions of the substrate are shadowed by a shadow mask from receiving at least one of the molecular beams used in the MBE process. This process is capable of producing NIPI superlattices that have selective contacts that are far superior to those which can be produced at present. This technique can also produce a wide variety of NIPI devices as well as other types of IC structures.
    Type: Grant
    Filed: January 17, 1989
    Date of Patent: November 28, 1989
    Assignee: Hewlett-Packard Company
    Inventors: Gottfried H. Dohler, Ghulam Hasnain, Jeffrey N. Miller
  • Patent number: 4878956
    Abstract: Certain semiconductor device structures are described in which single crystal layers of cubic Group II fluorides cover at least part of the surface of III-V semiconductor compound. The fluoride crystal has a cubic structure and may be lattice matched or lattice mismatched to the compound semiconductor substrate depending on fluoride composition. These fluoride single crystal layers are put down by a moleuclar beam epitaxy procedure using certain critical substrate temperature ranges and a particular cleaning procedure.
    Type: Grant
    Filed: March 9, 1989
    Date of Patent: November 7, 1989
    Assignee: American Telephone & Telegraph Company AT&T Bell Laboratories
    Inventors: Wilbur D. Johnston, Jr., Charles W. Tu
  • Patent number: 4876219
    Abstract: A method of forming a semiconductor thin layer on a silicon substrate comprising the steps of depositing a first amorphous layer of a compound semiconductor (e.g., GaAs) on the silicon substrate, and growing a first epitaxial layer of the compound semiconductor on the amorphous layer, characterized in that the method comprises the steps of: after the epitaxial growth step, depositing a second amorphous layer of the compound semiconductor on the first epitaxial layer, and growing a second epitaxial layer of the compound semiconductor on the second amorphous layer. The obtained GaAs/Si substrate has a reduced dislocation density.
    Type: Grant
    Filed: March 3, 1989
    Date of Patent: October 24, 1989
    Assignee: Fujitsu Limited
    Inventors: Takashi Eshita, Fumitake Mieno, Yuji Furumura, Takuya Watanabe
  • Patent number: 4876218
    Abstract: The invention relates to a method of growing a GaAs film on the surface of a Si or GaAs substrate by exposing the growing surface of the substrate in a vacuum to at least one vapor beam containing the Ga elementary component of the GaAs compound, and to at least one vapor beam containing the As elementary component of the GaAs compound. The method is characterized by the steps of (A) growing a GaAs buffer layer by alternately applying the elements of the GaAs compound to the surface of a substrate heated to a first temperature one atom layer at a time, whereby in the formation of each atom layer the growing surface is exposed to a vapour beam containing one elementary component of the GaAs compound only; and (B) heating the substrate to a second temperature higher than the first temperature, and growing another GaAs layer on the buffer layer by applying both of the elementary components of the GaAs compound simultaneously.
    Type: Grant
    Filed: September 26, 1988
    Date of Patent: October 24, 1989
    Assignee: Oy Nokia Ab
    Inventors: Markus Pessa, Harry Asonen, Jukka Varrio, Arto Salokatve
  • Patent number: 4874438
    Abstract: An intermetallic compound semiconductor thin film comprises a single crystalline deposition thin film made of a III-V group intermetallic compound having a stoichiometry composition ratio of 1:1. When forming the III-V group semiconductor thin film by an evaporation method, a substrate temperature is initially maintained at a high level while the evaporation source temperature is gradually raised, and when the intermetallic composition of the III-V group begins to deposit on the substrate, the substrate temperature is lowered while the evaporation source temperature is maintained at the same level as existed at the time when the intermetallic compound is deposited, and the deposition time is controlled.
    Type: Grant
    Filed: November 30, 1987
    Date of Patent: October 17, 1989
    Assignee: Toyo Communication Equipment Co., Ltd.
    Inventors: Masahide Oshita, Masaaki Isai, Toshiaki Fukunaka
  • Patent number: 4870032
    Abstract: Certain semiconductor device structures are described in which single crystal layers of cubic Group II fluorides cover at least part of the surface of III-V semiconductor compound. The Fluoride crystal has a cubic structure and may be lattice matched or lattice mismatched to the compound semiconductor substrate depending on fluoride composition. These fluoride single crystal layers are put down by a molecular beam epitaxy procedure using certain critical substrate temperature ranges and a particular cleaning procedure.
    Type: Grant
    Filed: March 24, 1987
    Date of Patent: September 26, 1989
    Assignee: American Telephone and Telegraph Company, AT&T Bell Laboratories
    Inventors: Wilbur D. Johnston, Jr., Charles W. Tu
  • Patent number: 4861393
    Abstract: A molecular beam epitaxy method of growing Ge.sub.x Si.sub.1-x films on silicon substrate is described. Semiconductor heterostructures using Ge.sub.x Si.sub.1-x layers grown on either Ge or Si substrates are described.
    Type: Grant
    Filed: May 28, 1987
    Date of Patent: August 29, 1989
    Assignee: American Telephone and Telegraph Company, AT&T Bell Laboratories
    Inventors: John C. Bean, Leonard C. Feldman, Anthony T. Fiory
  • Patent number: 4855256
    Abstract: A masking layer is formed on the light-emitting mirror surface of a semiconductor laser body. The masking layer is capable of blocking light emitted from the semiconductor laser body and of being thermally melted and evaporated by exposure to the emitted light. When the masking layer is formed on the light-emitting mirror surface of the semiconductor laser body, a small light-emitting hole is defined in the masking layer by the heat of the emitted light which is effective to prevent the material of the masking layer from being evaporated on a portion of the light-emitting surface.
    Type: Grant
    Filed: February 12, 1988
    Date of Patent: August 8, 1989
    Assignees: Ricoh Company, Ltd., Hiroshi Kobayashi, Haruhiko Machida
    Inventors: Hiroshi Kobayashi, Haruhiko Machida, Makoko Harigaya, Yasushi Ide, Jun Akedo
  • Patent number: 4847216
    Abstract: The process consists of depositing at least one layer of a doped material on a heated substrate placed in an enclosure, subjecting the substrate surface to the action of a molecular flux of the material, to the action of a doping particle beam and to the action of an electron beam.
    Type: Grant
    Filed: April 18, 1988
    Date of Patent: July 11, 1989
    Assignee: Centre National d'Etudes des Telecommunications
    Inventors: Francois A. d'Avitaya, Yves Campidelli
  • Patent number: 4843029
    Abstract: A method of manufacturing a semiconductor device is described in which gaseous material is supplied into a reaction chamber containing a substrate to cause a first epitaxial layer of a first material to grow on the substrate and switching means are then operated to alter within a predetermined period the supply of gaseous material into the reaction chamber to cause a second eitaxial layer of a second material to grow on the first layer. During the predetermined period of radiant heat source is activated to radiantly heat the surface of the first layer so as to smooth the first layer on an atomic level before growth of the second layer is commenced. The radiant heat source may be a laser capable of directing one or more laser pulses at the surface to be radiantly heated.
    Type: Grant
    Filed: April 4, 1988
    Date of Patent: June 27, 1989
    Assignee: U.S. Philips Corporation
    Inventors: Bruce A. Joyce, Philip Dawson
  • Patent number: 4835114
    Abstract: This invention concerns a production method and a processing apparatus for semiconductor devices, as well as an evacuating apparatus used for the processing apparatus. According to this invention, since the evacuation system of pressure-reduction processing apparatus for conducting various wafer processings during production steps of semi-conductor devices is constituted only with oil-free vacuum pump, deleterious oil contaminations or carbonation products of oils produced from oils upon heating are not present in the pressure-reducing processing chamber as compared with conventional pressure-reducing processing apparatus using a vacuum oil pump as an evacuation pump and the production method of semiconductor devices using such apparatus.
    Type: Grant
    Filed: February 19, 1987
    Date of Patent: May 30, 1989
    Assignees: Hitachi, Ltd., Hitachi Tokyo Electronics Co., Ltd.
    Inventors: Akihiko Satou, Tadao Kusaka, Shigeo Tomiyama, Kouzi Aoki, Ichiro Gyobu, Kimio Muramatsu, Hiroaki Sakamoto, Shinjiroo Ueda, Masahiro Mase, Takashi Nagaoka
  • Patent number: 4833100
    Abstract: The present invention relates to a method for producing a semiconductor thin film, in which a single crystalline silicon film is grown on an insulative single crystalline substrate, such as a single crystalline sapphire substrate, by the molecular beam epitaxy method. Silicon molecular beams are irradiated onto the substrate under the conditions wherein a substrate temperature is kept at 700.degree. to 900.degree. C. and an intensity of the molecular beams is kept within a range from 1.times.10.sup.12 atoms/cm.sup.2 .multidot.sec to 1.times.10.sup.13 atoms/cm.sup.2 .multidot.sec to clean a surface of the substrate and then the intensity of the molecular beams is increased to form the single crystalline silicon film. Thus, the substrate can be cleaned without being defected.
    Type: Grant
    Filed: December 8, 1986
    Date of Patent: May 23, 1989
    Assignee: Kozo Iizuka, Director-General of Agency of Industrial Science and Technology
    Inventors: Hiroshi Hanafusa, Kiyoshi Yoneda, Hidenori Ogata
  • Patent number: 4833101
    Abstract: Group III-V multi-alloy semiconductors, such as ternary, quaternary, and pentanary semiconductors, grown on a binary group III-V compound semiconductor substrate, are used as an active layer in opto-devices, high electron mobility transistors, etc. A method of growing multilayers, lattice-matched to the binary substrate and having specific energy band gaps, includes a molecular beam epitaxy (MBE) process. The present invention includes growing a quaternary or pentanary semiconductor layer using a minimum number of effusion cells and eliminating readjustment of molecular beam intensities from one layer to another layer during a series of epitaxial growth steps. As an example of quaternary growth, four effusion cells are utilized and two combinations of three effusion cells are alternately operated, one including an Al effusion cell and the other including a Ga effusion cell. Each of the three effusion cells is capable of growing a ternary semiconductor lattice-matched to the substrate.
    Type: Grant
    Filed: June 29, 1988
    Date of Patent: May 23, 1989
    Assignee: Fujitsu Limited
    Inventor: Toshio Fujii
  • Patent number: 4829021
    Abstract: An injection block having a plurality of geometrically arranged injection sources for gaseous Group III metal organic compounds is oriented substantially perpendicular to the placement of at least one semiconductor wafer substrate within a vacuum reaction chamber. The injector sources are sized to provide disbursing flow of the compounds capable of depositing a layer of about 5% uniform thickness or less over substantially the entire semiconductor wafer. An injection source of Group V compounds is located centrally within the geometrically arranged injection sources for the Group III compounds. The Group V injection source is sized to supply an excess of the Group V compounds required to react with the Group III compounds in order to form Group III-V semiconductor layers on the substrate and partition the Group III sources into groups having substantially equal numbers of injection sources. An excess of Group V comounds is injected.
    Type: Grant
    Filed: December 9, 1987
    Date of Patent: May 9, 1989
    Assignee: Daido Sanso K.K.
    Inventors: Lewis M. Fraas, Paul S. McLeod, John A. Cape
  • Patent number: 4829022
    Abstract: A method of forming a III-V semiconductor on the surface of a substrate which is placed in a vacuum chamber and is heated, by supplying one element of Group III and one element of Group V of the periodic table in the form of atoms or molecules to the surface of the substrate. The supply of the element of Group V is decreased to a small quantity insufficient to form a III-V compound semiconductor at least at one period of the growth of the III-V compound, and the element of Group V in the small quantity and the element of Group III are supplied to the surface of the substrate. This method makes it possible to grow III-V compound epitaxial layers which have a high degree of purity and fewer crystal defects and in which surfaces and the interfaces of the heterojunctions are flat on an atomic scale, at a wide temperature range. The present invention can be used for the fabrication of various optical devices and super-high-speed electronic devices.
    Type: Grant
    Filed: August 5, 1987
    Date of Patent: May 9, 1989
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Naoki Kobayashi, Hideo Sugiura, Yoshiji Horikoshi
  • Patent number: 4826784
    Abstract: A method of OMCVD heteroepitaxy of III/V (GaAs) material on a patterned Si substrate is described wherein heteroepitaxy deposition occurs only on the exposed Si surfaces and nowhere else.
    Type: Grant
    Filed: November 13, 1987
    Date of Patent: May 2, 1989
    Assignee: Kopin Corporation
    Inventors: Jack P. Salerno, Jhang W. Lee, Richard E. McCullough
  • Patent number: 4824518
    Abstract: A method for the production of semiconductor devices comprising: subjecting a GaAs substrate with an oxidized film thereon to a degasification treatment, heating the substrate during a radiation treatment by a molecular beam within a pre-treatment chamber to remove the oxidized film from the substrate, and growing a phosphorous compound semiconductor layer on the substrate by molecular beam epitaxy within a growth chamber connected to the pre-treatment chamber.
    Type: Grant
    Filed: March 24, 1986
    Date of Patent: April 25, 1989
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Toshiro Hayakawa, Takahiro Suyama, Kohsei Takahashi, Saburo Yamamoto
  • Patent number: 4806502
    Abstract: A method for producing a doped semiconductor layer on a semiconductor substrate, employing particle radiation, including the steps of initially applying an adsorbed layer containing a doping substance to the semiconductor substrate; controlling the concentration of the doping substance in the adsorbed layer; growing a semiconductor layer having a crystal lattice structure on the substrate; performing a secondary implantation operation for incorporating the doping substance in the crystal lattice of the semiconductor layer; and performing a heat treatment for removing crystal lattice imperfections and incorporating the doping substance into crystal lattice positions.
    Type: Grant
    Filed: December 9, 1987
    Date of Patent: February 21, 1989
    Assignee: Licentia Patent-Verwaltungs-GmbH
    Inventors: Helmut Jorke, Horst Kibbel
  • Patent number: 4804639
    Abstract: A method of making a semiconductor laser from a gallium arsenide substrate of a first conductivity type by depositing a first layer of semiconductor material having the composition Al.sub.x Ga.sub.1-x As of first conductivity type on the substrate and a thin second layer of semiconductor material for quantum confinement having the composition In.sub.y Ga.sub.1-y As on the first layer. This layer experiences sufficient strain in the semiconductor structure so as to minimize the threshold current density. The device is completed by depositing a third layer of semiconductor material having the composition Al.sub.x Ga.sub.1-x As and of second conductivity type on the second layer, and depositing a fourth layer of semiconductor material having the composition GaAs and of second conductivity type on the third layer.
    Type: Grant
    Filed: November 4, 1987
    Date of Patent: February 14, 1989
    Assignee: Bell Communications Research, Inc.
    Inventor: Eli Yablonovitch
  • Patent number: 4786616
    Abstract: A method for epitaxially growing a layer of III-V material on a wafer of a material such as silicon comprises the steps of placing the wafer (16') in a first ultra-high vacuum chamber (11), and epitaxially growing a transition layer such as germanium on the wafer. An intermediate high vacuum chamber (13) is used to transport the wafer 16' to a second ultra-high vacuum chamber (12), and the second chamber (12) is used to epitaxially grow a layer of III-V material over the transition layer. Gate valves (33 and 15) are sequentially opened and closed to that the second vacuum chamber (12) cannot be contaminated by gases or particles from the first vacuum chamber (11). Wafer transport from chamber (11) to (13) is achieved without exposure to the atmosphere or to significant pressure changes thus avoiding the waste of transfer time or the formation of native oxide on the wafer surface.
    Type: Grant
    Filed: June 12, 1987
    Date of Patent: November 22, 1988
    Assignee: American Telephone and Telegraph Company
    Inventors: Muhammad A. Awal, El Hang Lee
  • Patent number: 4771013
    Abstract: A three dimensional, bipolar wafer process for integrating high voltage, high power, analog, and digital circuitry, and structure formed thereby includes a wafer of non-compensated epitaxial strata on a heavily donor doped monocrystalline silicon substrate of <100> crystal orientation, which is etched and with three dimensional transistors formed in it. Passivation for and contacts to said circuits are established, and the circuits are interconnected. The high voltage and high power transistors include transistors of an H-bridge circuit, including at least one set of cascode double heterojunction transistors, the analog transistors include a bipolar transistor, and the digital transistors include transistors of a I.sup.2 L circuit. One method for constructing the wafer is by sequentially epitaxially depositing each strata in an UHV silicon-based MBE apparatus.
    Type: Grant
    Filed: August 1, 1986
    Date of Patent: September 13, 1988
    Assignee: Texas Instruments Incorporated
    Inventor: Patrick A. Curran
  • Patent number: 4769338
    Abstract: There is disclosed a film field effect transistor which can be operated at fast switching rates for use, for example, in video display applications. The transistor includes a body of silicon semiconductor material having a structure more ordered than amorphous material and less ordered than single crystalline material. The source and drain of the transistor comprise rectifying contacts formed on the body of silicon semiconductor material. Also disclosed are a method of making the transistor and an electronically addressable array system utilizing the transistor to advantage.
    Type: Grant
    Filed: March 9, 1987
    Date of Patent: September 6, 1988
    Assignee: Energy Conversion Devices, Inc.
    Inventors: Stanford R. Ovshinsky, Stephen J. Hudgens
  • Patent number: 4769341
    Abstract: A semiconductor device comprising an epitaxially grown tin and Group IV compound semiconductor region on which at least one other semiconductor is grown lattice matched to the adjacent portion of the tin containing region. A large number of semiconductors may thus be grown.
    Type: Grant
    Filed: December 29, 1986
    Date of Patent: September 6, 1988
    Assignee: American Telephone and Telegraph Company, AT&T Bell Laboratories
    Inventor: Sergey Luryi
  • Patent number: RE33671
    Abstract: The mobility of a relatively narrow bandgap semiconductor material can be significantly enhanced by incorporating it into a multilayered structure (10) comprising a first plurality of relatively narrow bandgap layers (12) of the material and a second plurality of wider bandgap semiconductor layers (14) interleaved with and contiguous with the first plurality. The wide bandgap and narrow bandgap layers are substantially lattice-matched to one another, and the wide bandgap layers are doped such that the impurity concentration-thickness product therein is greater than the same product in the narrow bandgap layers. The fabrication of the structure by MBE to enhance the mobility of GaAs is specifically described. In this case, the narrow bandgap layers (12) comprise GaAs and are unintentionally doped to about 10.sup.14 /cm.sup.3, whereas the wide bandgap layers (14) comprise AlGaAs doped n-type to about 10.sup.16 to 10.sup.18 /cm.sup.3. The incorporation of this structure in an FET is also described.
    Type: Grant
    Filed: May 26, 1987
    Date of Patent: August 20, 1991
    Assignee: AT&T Bell Laboratories
    Inventors: Raymond Dingle, Charles Gossard, Horst L. Stormer