Abstract: The method in accordance with the present invention is compatible with conventional CMOS fabrication processes to form a zener diode and a lateral silicon controlled rectifier constituting an on-chip ESD protection circuit in a semiconductor substrate. The zener diode is composed of a p-type doped region and an n-type doped region, wherein one of the doped regions, formed by deep diffusing impurities from a doped polysilicon layer, is arranged between two adjacent well regions. During an ESD event, the zener diode incurs breakdown to lower the trigger voltage of the lateral SCR device to within a range of about 5-7 Volts to thereby discharge the ESD current prior to damage of an internal circuit being protected.
Abstract: In a semiconductor arrangement and a method for manufacturing a semiconductor arrangement, varying diffusion rates are attained by introducing crystal disorder structures into a silicon crystal. The semiconductor structure includes a semiconductor wafer which has a first layer and a second layer, which form a p-n junction. Because the diffusion rates vary, the gradient of the dopant concentration of the second layer in the edge area is greater (merely) than in the middle area. As a result, a breakdown of the p-n junction in the edge area is reached at higher voltages than in the middle area.
Abstract: In one embodiment, modifications to the polysilicon gate, body, source, and contact masks of a DMOS process add a source-body monocrystalline gate protection diode under the gate pad by implanting an anode region beneath the gate. The anode is connected to the gate through the gate metal in the pad. In addition to the gate-source diode, there is a connection from the drain to the gate through the anode formed by the body region beneath the gate. This embodiment includes a junction terminating field plate. The field plate creates a protection device similar to a zener diode, but exhibits a current/voltage characteristic similar to a thyristor. A significant feature of this embodiment is that the zener breakdown voltage is easily adjusted by a simple modification to the fabrication process. The field plate creates two opposing junctions with the spacing determined by the field plate length.
April 12, 1996
Date of Patent:
February 11, 1997
National Semiconductor Corporation
Daniel Calafut, Izak Bencuya, Steven Sapp
Abstract: A process for the manufacture of an integrated voltage limiter and stabilizer component in a flash EEPROM memory device comprises a step of formation of an N type lightly doped well on a single-crystal silicon substrate; a step of formation of an active area on the surface of said N type well; a step of growth of a thin gate oxide layer over said active area; a step of implantation of a first heavy dose of N type dopant into said N type well to obtain an N type region; a step of implantation of a second heavy dose, higher than said first heavy dose, of N type dopant into said N type region to obtain an N+ contact region to both the N type well and said N type region; a step of implantation of a third heavy dose, higher than said first heavy dose, of P type dopant into said N type region to form a P+ region.
Abstract: The manufacturing process comprises a first step of formation of an N type sink on a single-crystal silicon substrate, a second step of formation of an active area on the surface of said sink, a third step of implantation of N- dopant in a surface region of the sink inside said active area, a fourth step of growth of a layer of gate oxide over said region with N- dopant, a fifth step of N+ implantation inside said N- region, a sixth step of P+ implantation in a laterally displaced position with respect to said N+ region and a seventh step of formation of external contacts for said N+ and P+ regions. There is thus obtained a zener diode limiter, having a cut-off voltage which is stable over time and not much dependent on temperature and which does not require the addition of process steps with respect to those usually necessary for the accomplishment of EEPROM memory cells.
September 18, 1992
Date of Patent:
June 21, 1994
SGS-Thomson Microelelctronics s.r.l.
Paolo Cappelletti, Giuseppe Corda, Paolo Ghezzi, Carlo Riva, Bruno Vajana
Abstract: According to this invention, there is provided to a method of manufacturing semiconductor devices including the steps of ion-implanting at least one impurity selected from As, P, Sb, Si, B, Ga, and Al in a wafer prior to a predetermined manufactural process of semiconductor devices in the semiconductor wafer grown by the Czochralski technique, and thereafter annealing the wafer at a temperature of at least 900.degree. C. Nonuniformity of an impurity concentration of the wafer can be improved. The difference in characteristics among the semiconductor devices manufactured in the wafer is decreased, a product yield can be increased, and the quality of the semiconductor devices can be improved.
Abstract: The manufacturing yield and properties of Zener diodes and other PN junctions are improved by locating the main PN junction remote from the die surface and providing at least two shallower concentric P regions of lighter doping surrounding the main P region. A first shallow P region contacts the main P region and a second extends to the die edge and is separated from the first region by an annular N region. Metallization contacting the main P region extends over the first shallow P region but not over the annular N region. Contact to the N substrate is conveniently made on the rear surface of the die.
Abstract: A process for manufacturing a combination and protection diode on a substrate comprising a first, highly doped, thick N-type layer (40) and a second N-type, low doped, layer (10), comprises the following successive steps: implanting in a small surface area N-type dopants (12), carrying out a first annealing process, implanting in a second area including and surrounding the first area N-type dopants (22), carrying out a second annealing process, inplanting in a third area including the first area and at least one portion of the second area P-type dopants (32), and carrying out a third annealing process.
Abstract: High voltage (200-400 volts) Zener diodes having much improved resistance to degradation under 150.degree. C. HTRB are obtained by a junction passivation comprising a thermal oxide next to the silicon, covered by a TEOS CVD glass, a CVD nitride and a further TEOS CVD glass. Multiple Zener voltages are obtained with otherwise identical, simultaneous wafer processing steps by using epi-wafers having different epi doping and thickness. Back-side for wafer thinning is avoided.
Abstract: An improved monolithic, temperature compensated voltage- reference diode is realized by creating a tub of epitaxial semiconductor material in a substrate of opposite conductivity type and creating a voltage reference junction at a surface of the tub. The junction between the tub and the substrate forms the forward-biased, temperature compensating junction of the device. The dopant concentration is varied during growth of the epitaxial material to provide a relatively low resistivity at the voltage-reference junction and a higher resistivity at the temperature compensating junction. The method described offers significant improvement over prior methods of manufacturing such devices in the area of cost and reliability.
July 3, 1989
Date of Patent:
December 12, 1989
Bernard W. Boland, William E. Gandy, Jr., Kevin B Jackson
Abstract: A mesa Zener diode is described which is manufactured by ion implanting a region of opposite conductivity into a substrate; etching a moat in a surface of the substrate through the region of opposite conductivity; depositing an oxide layer having an opening exposing a portion of the mesa; and depositing top and bottom metals.
Abstract: In a method of electrically altering the characteristics of a semiconductor device, a lateral polysilicon zener diode's zener knee voltage may be shifted either to a higher or lower voltage. An electrical potential may be applied in the forward direction to shift the zener knee to a higher voltage level. An electrical potential may be applied in the reverse bias direction to shift the zener knee to a lower voltage. In the limit, the zener may be changed into a forward diode of reverse polarity with respect to the original zener. The electrical potential used should be of appropriate magnitude to melt the polysilicon without damage to the zener's terminals. This induces migration of the impurities causing a rediffusion of impurities thereby altering the characteristics of the diode. This method may be used to program a PROM by either converting the zener to a diode or not to program each binary bit.