Abstract: In a method of manufacturing a semiconductor device of polycide gate structure, a polysilicon layer is formed on the gate insulation film. The polysilicon layer and the gate insulation film are selectively removed to form an opening which reaches the semiconductor substrate in the polysilicon layer and the gate insulation film. After this, a silicide film is formed directly on the polysilicon layer and an exposed part of the semiconductor substrate and then ion-implantation is effected to form source and drain regions. According to the manufacturing method, since the silicide film is formed in direct contact with the semiconductor substrate, charges caused by the ion-implantation can be easily discharged into the semiconductor substrate. Therefore, no gate charge will occur. Further, the gate oxide film is prevented from being brought into contact with the masking photoresist layer by the presence of the polysilicon layer.

Abstract: The described embodiments of the present invention provide a protective layer on the surface of silicided regions and methods for its formation. In the primary described embodiment, a titanium silicide layer is formed in integrated circuitry using self-aligned techniques. Local interconnection layers may be formed using biproducts of the self-aligned titanium disilicide formation. A layer of another siliciding metal, for example platinum, is then formed overall. The platinum layer is then subjected to an annealing step which causes a portion of the silicon in the titanium disilicide layers to react with the platinum to form platinum silicide. This platinum silicide layer is formed in a self-aligned manner on the surface of the silicided regions. The platinum silicide layer serves to protect the underlying titanium disilicide layer from subsequent etching steps of other harmful processing operations.

Abstract: A process of forming a self-aligned oxide layer covering conductive structures such as MOS transistor gates above a semiconductive substrate while portions of the substrate such as source/drain regions are exposed involves forming side wall spacers against the gates, applying refractory metal to the exposed surface, heating the refractory metal so that it forms refractory silicide at regions where the refractory metal contacts the substrate, removing the unreacted refractory metal, and oxidizing the exposed refractory silicide with a low temperature wet oxidation which causes faster oxide growth above the highly doped gates than above the lightly doped source/drain regions. Subsequent etching of the differentially grown oxide layer exposes the source/drain regions while leaving protected the gate regions. Since no mask was needed for forming and patterning the gate-covering oxide, no misalignment can occur and thus no space need be allowed in the circuit layout for misalignment.

Abstract: An integrated circuit device of large scale integration and a method of manufacturing the same makes possible high density packing of circuit elements by eliminating a great number of very minute contact holes. Instead, a circuit-element connector comprised of a polycrystalline silicon wiring path is formed by selective oxidation. Impurity atoms are introduced into the semiconductor substrate through the polycrystalline silicon circuit-element connector to form a desired circuit element. A layer of high-conductive material is provided on the polycrystalline silicon layer.

Abstract: A method being capable of achieving the reduction in contact resistance between each layer when bringing a silicide layer into contact with a polycrystalline-silicon (polysilicon) layer in the manufacture of semiconductor devices. The method comprises the steps of forming a polysilicon layer and a silicide layer thereon over a partial top surface of a semiconductor substrate, forming an insulating layer over said silicide layer and the entire top surface of the substrate, forming a contact window by etching the partial area of the insulating layer over said silicide layer, and forming a polysilicon layer over the entire top surface of the substrate after performing ion-implantation through said contact window, wherein said ion-implantation is performed with N-type high doping into the silicide.

Abstract: A self-aligned salicide process produces small dimensioned semiconductor devices, for example metal oxide semiconductor (MOS) devices. An electrode is formed on the face of a semiconductor substrate, the electrode having a top and a sidewall and an insulating coating on the sidewall. Then a silicon layer and a refractory metal layer are formed on the face, top and sidewall, with one of the layers being continuous, and the other layer having a break on the sidewall. In a preferred embodiment the silicon layer is directionally applied, to form thick portions on the face and top and thin portion on the sidewall. The thin portion on the sidewall is removed and a metal layer is uniformly deposited. The substrate is heated to convert at least part of the silicon and metal layers to silicide. The silicide layer on the face is planar and does not consume the substrate at the face, allowing shallow source and drain regions to be formed.

Abstract: In a semiconductor device including a substrate of Si or polycrystalline silicon and an interlayer insulation film region, a region for interconnection with the substrate is composed of a refractory metal silicide layer, a refractory metal nitride layer, an Al or Al alloy layer, and possibly a further refractory metal nitride layer, while a region for interconnection on the interlayer insulation film on the substrate is composed of a refractory metal, or refractory metal oxide layer, a refractory metal nitride layer, an Al or Al alloy layer, and possibly a further refractory metal nitride layer, providing interconnections for integrated circuits. In the manufacture of this interconnection structure, rapid thermal annealing is performed at 600.degree.-1000.degree. C. on the refractory metal nitride layer of the region for interconnection with the substrate, followed by the formation of Al or Al alloy layer.

Abstract: A process is disclosed for the fabrication of semiconductor devices which yields a device having a very short effective channel length and having polycrystalline source and drain electrodes. In accordance with the disclosed process, a semiconductor substrate is provided having a masking element positioned on the substrate surface. A layer of polycrystalline silicon is deposited on the exposed areas of the substrate surface by the process of selective deposition. The selectively deposited polycrystalline silicon is doped with conductivity determining impurities and that impurity material is thereafter redistributed to dope the underlying substrate to form source and drain regions. The masking element is removed to expose the portion of the semiconductor surface between the source and drain regions and to allow for a subsequent optional channel implantation.

Abstract: A method of forming a bridge contact between a source diffusion region of a transfer gate FET and a polysilicon-filled trench storage capacitor electrodes of the FET. A layer of titanium is evaporated at a temperature of approximately 370.degree. C., so that the titanium has a substantially columnar grain structure and a minimum of matrix material. The bottom portions of the columnar grains have a lateral length that approximates the lateral length of the dielectric separating the source diffusion from the poly-filled trench. Thus, upon sintering at 700.degree. C. in an N.sub.2 atmosphere, titanium silicide will form over all exposed silicon regions as well as the dielectric, without shorting the FET electrodes together.

Abstract: An improved bipolar transistor of a BiCMOS integrated circuit is fabricated by utilizing a nitride layer over a thin silicon dioxide layer combined with a polysilicon layer. This bipolar structure has a self-aligned, P-type extrinsic base which results in lower base resistance and improved performance.

Abstract: A silicide layer, to improve conductivity, is formed over a first layer of polycrystalline silicon, followed by a second layer of polycrystalline silicon. This structure is then patterned to form gate regions over active areas. A layer of metal silicide is formed over the entire surface of the chip, and patterned to form local interconnect. Etching of the second metal silicide layer is stopped by the second polycrystalline silicon layer, thereby protecting the first metal silicide layer from damage.

Abstract: A monolithic integrated circuit of either the MOS or CMOS type comprises an intermediate layer of polycrystalline silicon, a layer of a silicide of a refractory metal overlying said polycrystalline silicon layer, and regions of preset area and preset paths formed in the polycrystalline silicon layer and the silicide layer; the preset area regions and preset paths forming respectively high resistivity resistances and low resistivity interconnection lines for an intermediate connection level.

Abstract: A method is provided for forming a contact plug (40) in a contact (34) on a semiconductor substrate (30). A dielectric layer (32) is applied to the substrate (30) and then etched to form the contact (34). A layer (38) is then formed over the dielectric (32) and the contact (34). The layer (38) is removed from all surfaces, except the vertical sidewalls (36) within the contact (34). A metal plug (40) is then deposited in the contact (34) forming cup-shaped layers (42). The nonselectivity of the layer (38) allows the metal of plug (40) to be applied to the contact (34) without encroaching upon the substrate (30) or forming bumps on the surface (44) of the dielectric (32).

Abstract: A metal or metal silicide layer (37) is selectively grown on a nucleating layer (28) with a predetermined pattern on an insulating layer and on a substrate below an opening in an insulating layer, to form a metal or metal silicide electrode in contact with the substrate external base (36) the opening and extending therefrom along the pattern of the nucleating layer. This process is advantageous in that a high electroconductive metal or metal silicide layer having a precise pattern can be easily formed.

Abstract: A method of fabricating a SALICIDED self aligned metal oxide semiconductor device using a disposable silicon nitride spacer, metal silicide and a single implant step for the source, drain and gate regions is disclosed. The fabrication of the device is accomplished in seven major steps: First, on a substrate having an oxide layer, an undoped polysilicon layer defining the gate region is deposited. Second, an oxide layer is grown and then a silicon nitride layer is deposited. Third, the oxide and the silicon nitride layers are selectively etched, leaving the oxide and the nitride layers on the walls of the polysilicon gate region. Fourth, a cobalt layer is deposited on the wafer and processed to form cobalt silicide, after which the cobalt that did not come in contact with the silicon or the polysilicon gate region is removed. Fifth, the nitride layer on the walls of the gate region is removed. Sixth, a single ion implant step is used to form the N-channel Transistors of the device.

Abstract: A method of selectively forming (growing or depositing) a silicon-containing metal layer on an exposed surface of a semiconductor substrate or a conductor by using a metal halide gas and a silicon hydride gas at a ratio of a flow rate of the latter gas to that of the former gas (e.g., Si.sub.n H.sub.2n+2 /WF.sub.6) of 2 or less, and setting a growth temperature at 200.degree. C. or less. When a Si.sub.3 H.sub.8 gas and a WF.sub.6 gas, in particular, are used at a ratio of the flow rates (Si.sub.3 H.sub.8 /WF.sub.6) of 1.0 or less, and the deposition temperature is set at 100.degree. C. to room temperature, a silicon-containing tungsten layer is selectively deposited (formed).

Abstract: In a method of filling a contact hole of a semiconductor device, a layer of conducting material, such as a metal silicide, is formed on side walls of the contact hole, and metal is selectively deposited on the bottom of the contact hole and on the layer of metal silicide on the side walls of the contact hole to substantially fill the contact hole. The method provides a contact structure comprising a contact region of the semiconductor device defining the bottom of the contact hole, a layer of conducting material, such as a metal silicide, on the side walls of the contact hole, and a metal plug substantially filling the contact hole. The metal plug adheres to the layer of metal silicide on the side walls of the contact hole and to the contact region defining the bottom of the contact hole.

Abstract: Disclosed is a method of fabricating a polycidegate in semiconductor device which has a step of forming a conductor film of polysilicon on a substrate, a step of forming an ion implanted layer by implanting nitrogen ions into the polysilicon conductor film, and a step of forming a low resistance conductor film of titanium on the non-monocyrstalline conductor film. When a field effect transistor is formed by this method, using titanium nitride and/or TiSi.sub.2 alloy of the polysilicon conductor and low resistance conductor of titanium by heat treatment as a gate electrode material, the thickness of the alloyed layer is uniform, and breakdown of the gate insulating film due to local diffusion of low resistance conductor is not induced. In other embodiments, oxygen ions and silicon ions are also employed to form thin layers of tunnel oxide and amorphous silicon, respectively.

Abstract: A three-layer metal contact including aluminum is provided for silicon-based semiconductor devices to minimize the effects of formation of silicon precipitates in the aluminum layer and low contact junction leakage. The metal contact comprises a first layer of a refractory metal silicide formed on a silicon surface, an intermediate layer of aluminum formed on the refractory metal silicide and a top layer of a refractory metal silicide formed on the layer of aluminum. Where contact is made to polysilicon layers forming high resistance load resistors, the metal contact of the invention prevents reduction in resistance resulting from the interdiffusion of silicon and aluminum.

Abstract: A process for forming a capping layer over a titanium silicide layer includes forming a layer of polysilicon (16) over a gate-oxide layer (14). A layer of titanium (18) is then formed over the poly layer (16) followed by deposition of a composite layer of tantalum silicide (20). The structure is then patterned and subjected to an annealing process to form a titanium silicide layer (22) covered by the capping layer (20) of tantalum silicide. The tantalum silicide provides a much higher oxidation resistant layer with the underlying titanium silicide providing the desirable conductive properties needed for long runs of interconnects on a semiconductor structure.

Abstract: Silicides are important for submicron VLSIC technology. Problems have been found in forming silicides by known techniques involving simply depositing a metal film and heating that metal to form a silicide layer. This invention solves the problems through recognition that polymeric contamination can be left on the surface from commonly-used previous reactive ion etch steps, and removes any such contamination to metal deposition by the additional step of heating in dry oxygen at a low temperature, such as 800 degrees Centigrade, before the contamination has been significantly hardened.

Abstract: A silicide base shunt 50 and method of fabricating it are disclosed for a bipolar transistor. The base shunt 50 is fabricated using the first layer metal 36, 39 as a mask to etch silicon dioxide 27 surrounding the emitter 34 to thereby expose the underlying silicon epitaxial layer 24. Nickel or copper are then deposited onto the silicon 24 to form a region of silicide 50 extending from a base contact 36 to closely proximate the emitter 34, thereby minimizing the resistance of the extrinsic base region 24 of the transistor.

Abstract: In fabricating the contact, the electrode layer of polycrystalline silicon whose rim portion is bonded via a layer portion of insulating material to the substrate, is used at least throughout the length of a part of its rim portion for the lateral delimitation of a etching process, as an etch mask, in the course of which a frame-shaped layer portion is formed underneath the rim portion of the electrode layer, and the contact area of the substrate as bordering on the layer portion is exposed. Following the deposition of a metal layer of a metal forming a silicide in a thickness smaller than the thickness of the layer portion, and the heating for forming the silicide, the metal which has so far not reacted with the silicon, is removed by using an etching agent selectively dissolving the metal.

Abstract: A MOS transistor (10) having a thicker silicide layer (50) over a gate (30) than a silicide layer (44) over source and drain regions (42) is disclosed. A process of the present invention forms a first silicide barrier (28) overlying the gate (30) when the gate is formed. Next, a first silicide formation process forms the first silicide layer (44) overlying source and drain regions (42). The silicide barrier layer (28) prevents silicide formation over the gate (30). The silicide barrier (28) is removed, and another silicide barrier (48) is formed over the first silicide layer (44). A second silicide formation process forms the second silicide layer (50) over the gate (30). The silicide barrier layer (48) prevents expansion of the first silicide layer (44).

Abstract: A method for forming a contact to a selective region of an integrated circuit characterized by the steps of: forming a layer of refractory metal over and around the selected region; forming a layer of amorphous silicon over the layer of refractory metal; patterning the amorphous silicon into an elongated strip which extends away from the selected region; annealing the integrated circuit to convert the strip of amorphous silicon into a silicide path; and removing the unreacted refractory metal. The method of the present invention can be used to extend a contact to the source, drain, or gate of a MOSFET from the top of an adjacent section of field oxide, and can also be used as a method for local interconnection of IC devices, such as CMOS devices.

Abstract: After having formed contact islands (20) comprising at least one layer of silicide (20) of titanium or cobalt, these islands are covered by a complementary metallic layer (30) obtained by selective growth of tungsten or molybdenum, which is localized at the said islands. This complementary metallic layer especially serves as a stopping layer during etching of contact openings (33) into an isolating layer (32) supporting the remaining part of the structure of interconnections.

Abstract: A method of diffusion of dopants (e.g. zinc) into III-V substrates (e.g. GaAs) using metal silicide and dopants (e.g. W.sub.x Si.sub.y :Zn) is disclosed. A cap layer (e.g. SiO.sub.2 or Si.sub.3 N.sub.4) is also used. The zinc tungsten silicide is formed by cosputtering zinc and tungsten silicide (W.sub.5 Si.sub.3). Applications include adjustment of threshold voltages in JFETs by rapid thermal pulsing of zinc into device channel regions and use of the zinc tungsten silicide as a base contact plus extrinsic base dopant source together with a nitride sidewall self-alignment.

Abstract: A method of fabricating a dielectrically-isolated structure is disclosed rein the structure includes a layer of silicide which is selectively doped, preferably using an ion implantation process. The doped silicide is then used as the diffusion source for the subsequent formation (through a heat treatment) of various active portions (collector, emitter, drain, source, for example) of a variety of high-voltage, high-speed active devices. The non-doped silicide is advantageously utilized as a low-resistance contact between the buried diffusion region and the surface electrode. In an alternative embodiment, bottom portions of the silicide contiguous to the tub are removed, leaving only vertical silicide portions adjacent to the sidewalls of the dielectrically isolated tub.

Abstract: A method for manufacturing a semiconductor device of the invention comprises the steps of(a) forming a gate insulating film on a surface of a silicon substrate, and a gate electrode on said gate insulating film;(b) forming a source region and a drain region by doping said substrate with an impurity which has a conductivity type opposite to a conductivity type of said silicon substrate;(c) forming a self-aligned insulating layer on the side walls of the gate electrode;(d) forming a self-aligned metal layer on a region on which an insulating film is not formed, the region including the source region and the drain region; and(e) forming electrodes which are connected to the source region, drain region and gate electrode.

Abstract: An integrated circuit fabrication process for improving step coverage of the metal lines and of metal layer interconnections is disclosed. A conductive polysilicon, polycide, or polycide-on-polysilicon plug is formed in contact apertures by successive silicidation sequences of silicon/refractory metal deposition and heat treatment. A preceding silicide may also be removed prior to a succeeding silicidation to reduce silicon lining.

Abstract: A silicide film of oxidized transition metal 3 formed on a transparent substrate 1 has a low reflectance and in consequence, a high resolution can be obtained and dry etching thereof can be easily done. In addition, since said silicide film 3 has good adhesion to a transparent substrate 1, fine patterns therein do not peel off at the time of rinsing the mask.

Abstract: In order to prevent diffusion of silicon from under a titanium disilicide interconnect (1) and into an overlying aluminium layer (6), the disilicide is selectively nitrided by annealing in nitrogen at the points where interconnection between the disilicide and aluminium is required via holes (4) in a silicon dioxide layer (3). The titanium nitrode contacts (5) thus formed in a truly self-aligned manner provide a good barrier to silicon diffusion while having an acceptable low resistivity.

Abstract: A method for providing platinum or tungsten silicide contacts to source, drain, gate and tub regions of a dielectrically isolated MOSFET is described. A "false" (dummy) gate is used to provide automatic self-aligned separation of the source-drain contact and the tub contact. An intermetallic forming material (refractory metal) is uniformly coated over the doped substrate on which the gate and false gate region have been formed in a spaced-apart fashion. Upon heating the intermetallic forming layer reacts with the substrate and the polysilicon gates to form intermetallic regions. The remaining portion of the intermetallic forming layer is differentially etched away from the dielectric isolation walls and the sidewall oxides on either side of the gate and false gate. Alternatively, selective deposition may be used to avoid deposition on the dielectric regions. The false gate extends laterally across the isolation tub.

Abstract: A novel MOS transistor structure comprises electrodes of metallic silicide and especially tantalum silicide. In the case of the gate electrode, the silicide is directly in contact with an insulating thin-film layer. In the case of the drain and source electrodes, the silicide is directly in contact with the monocrystalline silicon. The method of fabrication is thus simplified while avoiding the use of polycrystalline silicon.

Abstract: A transition metal silicide film 3 is formed on a transparent substrate 1, and an oxidized transition metal silicide film 4 is formed on said transition metal silicide film 3. Dry etching can be easily applied to the transition metal silicide film 3 and the oxidized transition metal silicide film 4. Since the silicified metal films have good adhesion to the transparent substrate 1, the fine patterns can hardly be detached at the time of mask rinsing. In addition, the oxidized transition metal silicide film 4 has a low reflection factor, which prevents the lowering of the resolution.

Abstract: An improved bipolar device is disclosed having a polysilicon emitter formed over a base region of a silicon substrate with oxide spacer portions formed on the sides of the emitter and metal silicide portions formed over the base region adjacent the oxide spacers whereby the use of polysilicon for the emitter results in high gain as well as vertical shrinking of the device because of the shallow diffusion of the emitter into the base and the elimination of an extrinsic base region. The use of oxide spacers and metal silicide adjacent the spacers results in a shrinkage of the horizontal spacing of the device to lower the base-emitter resistance and capacitance to thereby increase the speed of the device.

Abstract: A semiconductor device having contact windows between an aluminum or aluminum-alloy wiring layer and a diffused region in a semiconductor substrate, in which the contacts are formed by using a barrier film on a refractory metal silicide between the wiring layer and the diffused region. The barrier film comprising the refactory metal and silicon is beam annealed for a short period of time such as, 10 seconds or less, so that adverse effects of the barrier film can be prevented while an excellent electrical or ohmic contact between the wiring layer and the diffused layer can be obtained.

Abstract: A method of forming a multilayer interconnection for a semiconductor device comprising a first insulation layer deposited on a substrate having semiconductor elements, first interconnection patterns, a second insulation layer interposed between the first interconnection patterns, a third insulation layer covering the first interconnection patterns and second interconnection patterns contacted with the first interconnection patterns, wherein the first interconnection patterns are formed in such a manner by vapor phase growth process that the first interconnection patterns cover both edges of the interposed second insulation layer.

Abstract: A metallizing system for silicon surfaces consists solely of two layers of nickel and silver, respectively. Approximately 2 microns of the underlying silicon surface is removed prior to metallization to ensure removal of an oxygen-saturated layer of silicon before the nickel layer is deposited. The assembly is heated sufficiently that the nickel layer forms a nickel-silicide layer at the silicon surface. The metallizing adheres to the bare treated silicon but does not adhere to adjacent oxide coatings and easily lifts off of oxide-coated surfaces. The metallizing is solderable, makes ohmic contact to the silicon, regardless of its conductivity type and survives subsequent alloy processing temperatures.

Abstract: Contacting an underlying region (e.g., doped silicon) through an access hole in an overlying dielectric layer (e.g., p-glass) formerly required flowing the dielectric to smooth the edges of the hole, so that aluminum would deposit smoothly into the hole. The present technique smoothes the side of the hole by forming a smoothing region on the sidewall. Improved aluminum coverage results, as well as allowing a smaller contact head, if desired. Improved contact resistance can be optionally provided by depositing a more conductive layer on the underlying layer prior to forming the sidewall.

Abstract: A method for constructing titanium silicide integrated circuit gate electrodes and interconnections is disclosed. The method finds particularly useful applications in metal-oxide semiconductor integrated circuit fabrication. Following standard active and passive circuit component construction, a thin film of titanium is overlayed on the die structure covering thereby the pre-patterned polysilicon gates and interconnections. The die is then rapidly heated and baked to form a silicide layer superposing said polysilicon. The undesired titanium layer over other areas can be stripped using simple ammonium hydroxide/hydrogen etching and cleaning solution. Titanium silicide electrodes and interconnections are self-aligned and have a sheet resistance of 1 to 5 ohms per square.

Abstract: A Schottky barrier diode is made from a substrate of semiconductor material by forming, on a major surface of the wafer, a layer of dielectric material defining a restricted opening through which the semiconductor material is exposed. A metal which forms with the semiconductor material a single phase compound which is inherently stable at temperatures up to 600 deg. C. is deposited into the opening, into contact with the exposed semiconductor material. By heating the substrate and the metal deposited thereon, the metal reacts with the semiconductor material to form a body of the single phase compound. A layer of refractory metal which reacts with the dielectric material is deposited over the dielectric material and the body of single phase compound.

Abstract: A method for manufacturing a semiconductor device of the invention comprises the steps of(a) forming a gate insulating film on a surface of a silicon substrate, and a gate electrode on said gate insulating film;(b) forming a self-aligned insulating film at least on a side wall of said gate electrode;(c) forming a self-aligned metal or metal silicide film on a region on which an insulating film is not formed, said region including a source region, a drain region and a diffusion interconnection region which is an extended part of at least one of said source region and said drain region, or prospective regions for said source, drain and diffusion interconnection regions; and(d) forming said source region, said drain region and said diffusion interconnected region which is the extended part of at least one of said source region and said drain region, by doping at least one time said substrate with an impurity which has a conductivity type opposite to a conductivity type of said silicon substrate any time after st

Abstract: A method of manufacturing a semiconductor device manufactures a semiconductor device provided with plural kinds of Schottky barrier diodes having different forward voltages on one substrate. The method includes (a) a step of forming at least one Schottky barrier diode of a first kind, and (b) a step of forming at least one Schottky barrier diode of a second kind. The step (a) is performed by placing a first metal layer at a first surface part of a silicon substrate, and then by silicifying the first metal layer. The step (b) is performed by plating, at a second surface part of the silicon substrate which is different from the first surface part of the silicon substrate, a second metal layer which consists of a metal different from the metal consisting of the first metal layer and then by silicifying the second metal layer.

Abstract: A method of producing a semiconductor device, including the steps of introducing an impurity of one conductivity type into a semiconductor substrate of an opposite conductivity type having an insulating film pattern formed on a surface thereof, using the insulating film pattern as a mask to form a diffusion layer; and forming a metal film on the diffusion layer by selective vapor growth with a mixture of a metal source gas and a carrier gas used as a feed gas. The vapor growth is carried out such that the distance of entry of the metal film from the edge of the insulating film pattern to the interface between the insulating film pattern and the diffusion layer is smaller than the depth of the pn junction of the diffusion layer. The particular method makes it possible to achieve a selective vapor growth of a metal film on the diffusion layer without deteriorating the pn junction characteristics.

Abstract: The invention concerns an integrated circuit the monocrystalline or polycrystalline silicon zones of which the source, gate and drain are covered with tantalum silicide TaSi.sub.2 while the remainder of the slice is covered with portions of a layer of tantalum oxide Ta.sub.2 O.sub.5, especially on the sides of the grids of polycrystalline silicon and on the thick oxide and an aluminum alloy layer comes into contact with the tantalum silicide to form connections with the portions of tantalum silicide.

Abstract: Disclosed is the use of metal silicide (e.g. Pt-Si) contacts in boron lightly doped P.sup.- type silicon between two contiguous but not adjacent N.sup.+ type regions instead of employing the usual P.sup.+ implanted or diffused channel stoppers. The invention finds a particularly interesting application in polyimide filled deep trench isolated integrated circuits.The trench sidewalls are coated with an insulating material which is removed from the trench bottom at the all contact etch step. The Pt-Si is formed at the bottom of the trenches at the same time that the device contacts are made.

Abstract: Metal contacts and interconnections for semiconductor integrated circuits are formed by a process using direct-reacted silicide to increase step or sidewall coverage. First a thin layer of titanium or other refractory metal is deposited, extending into a contact hole, then polysilicon is deposited and a preferential etch removes all of the polysilicon except on the vertical sides of steps or apertures. A second thin layer of titanium is deposited, then a heat treatment forms silicide to create conductive sidewalls or a plug. Metal contacts then engage the direct-reacted silicide rather than relying upon step coverage.

Abstract: A vertical IGFET comprising a substantially planar silicon wafer with a source electrode on one major surface and a drain electrode on the opposite major surface is disclosed. An insulated gate electrode, which includes a conductive finger portion surrounded by an insulating layer, is internally disposed in the silicon wafer such that a predetermined voltage applied to the gate electrode will regulate a current flow between the source and drain electrodes. The device is fabricated utilizing an epitaxial lateral overgrowth technique for depositing monocrystalline silicon over the insulated gate which is disposed on a silicon substrate.

Abstract: Apart from the base fingers (10), this transistor includes a titanium silicide coating, from which the base diffusions have been formed, and a silicon nitride coating (4). The edges of sandwiches made up of bands (3) and (4) are bordered by a silica bank (7) formed automatically by deposit and anisotropic attack, without additional masking. The emitter fingers (9) are overhung by a polycrystalline silicon layer (8) from which doping of these fingers has been obtained.The possibility is also obtained, automatically and without masks alignment, of having the emitter and base fingers brought firmly together with minimum protection distances.