Abstract: A rapid curing adhesive formulation that contains 10-40 wt. % of a cyanate ester vehicle having a cyanate ester, alkylphenol and a metal curing catalyst and 60-90 wt. % of thermally and/or electrically conductive filler. The adhesive formulation has a maximum curing time of 5 minutes, preferably 2 minutes, at 200.degree. C. and is adapted for use in high speed processes for production of bonded semiconductor assemblies.

Abstract: An improved semiconductor device manufacturing system and method is shown. In the system, undesirable sputtering effect can be averted by virtue of a combination of an ECR system and a CVD system. Prior to the deposition according to the above combination, a sub-layer can be pre-formed of a substrate in a reaction chamber and transported to another chamber in which deposition is made according to the combination without making contact with air, so that a junction thus formed has good characteristics.

Abstract: A processing apparatus and method for depositing a passivating layer on a mercury-cadmium-telluride wafer utilizing a single process chamber to provide oxygen gas to the chamber with the excitation energy being provided by a remotely generated plasma in order to remove any organic residue and then supplying either a sulfide or selenide gas in combination with illuminating the wafer with an in situ generated ultraviolet energy to produce a passivating layer.

Abstract: The present invention is a method of forming large device quality single crystals of silicon carbide. The sublimation process is enhanced by maintaining a constant polytype composition in the source materials, selected size distribution in the source materials, by specific preparation of the growth surface of seed crystals, and by controlling the thermal gradient between the source materials and the seed crystal.

Abstract: During fabrication of monolithic microwave integrated circuits, active devices having sources, gates, drains, and/or Schottky barrier junctions are first provided for an epitaxial layers. Then many layers of metals and oxides are produced thereover in situ without removing the circuit from its environmental chamber. Circuit elements are then defined by processing of the many layers sequentially by photolithography and other processes from the top of the chip downward. Certain combinations of metals, oxides, and processes are selected to enable fabrication of circuits from the top down in this way. This reduces inclusion of contaminating chemical films and particles between the desired layers. Lumped and distributed capacitors, resistors, inductors, transmission lines, contacts, and complete active devices are monolithically defined, with a reduced number of process steps.

Abstract: A method for epitaxially growing a layer of III-V material on a wafer of a material such as silicon comprises the steps of placing the wafer (16') in a first ultra-high vacuum chamber (11), and epitaxially growing a transition layer such as germanium on the wafer. An intermediate high vacuum chamber (13) is used to transport the wafer 16' to a second ultra-high vacuum chamber (12), and the second chamber (12) is used to epitaxially grow a layer of III-V material over the transition layer. Gate valves (33 and 15) are sequentially opened and closed to that the second vacuum chamber (12) cannot be contaminated by gases or particles from the first vacuum chamber (11). Wafer transport from chamber (11) to (13) is achieved without exposure to the atmosphere or to significant pressure changes thus avoiding the waste of transfer time or the formation of native oxide on the wafer surface.