Abstract: A unique approach to suppressing latchup in CMOS structures is described. Atomic species that exhibit midgap levels in silicon and satisfy the criteria for localized action and electrical compatibility can be implanted to suppress the parasitic bipolar behavior which causes latchup. Reduction of minority carrier lifetime can be achieved in critical parasitic bipolar regions that, by CMOS construction are outside the regions of active MOS devices. One way to accomplish this goal is to use the source/drain masks to locally implant the minority carrier lifetime reducer (MCLR) before the source/drain dopants are implanted. This permits the MCLR to be introduced at different depths or even to be different species, of the n and p-channel transistors. Another way to accomplish this goal requires that a blanket MCLR implant be done very early in the process, before isolation oxidation, gate oxidation or active threshold implants are done.

Abstract: A method is described for manufacturing semiconductor components with short switching time, having a weakly doped semiconductor area in contact with a PN junction. In order to obtain an inhomogeneous impurity distribution in the axial direction of the semiconductor array, the following process steps are implemented:a) gold impurities are placed in the semiconductor array and homogeneously distributed there in a first diffusion process,b) a layer comprising a 3d transition metal affecting the charge carrier lifetime is deposited onto that surface side of the semiconductor array having a shorter distance from the weakly doped semiconductor area,c) the 3d transition metal is incorporated into the semiconductor array by a second diffusion process and is inhomogeneously distributed there, such that an impurity surplus is generated in a partial area of the weakly doped semiconductor area in the vicinity of the PN junction.

Abstract: A method of producing sheets of crystalline material is disclosed, as well as devices employing such sheets. In the method, a growth mask is formed upon a substrate and crystalline material is grown at areas of the substrate exposed through the mask and laterally over the surface of the mask to form a sheet of crystalline material. This sheet is optionally separated so that the substrate can be reused. The method has particular importance in forming sheets of crystalline semiconductor material for use in solid state devices.

Abstract: For increasing the electric strength of a semiconductor component that comprises a sequence of semiconductor layers of alternating conductivity type and which is adapted to be charged with a voltage that biases at least one of the p-n junctions that separate the layers from one another in the non-conducting direction, the carrier life is reduced only in the lateral region of the edge termination of this p-n junction. The carrier life is reduced by irradiation with electrons or protons or by introducing atoms having recombination properties.

Abstract: GaAs films compensated with TEOV to reduce free electron concentration are grown having superior morphology by heating the TEOV above the temperature used in the prior art, filtering the other constituents but not the TEOV, and reducing the arsenic ambient during the preliminary heating phase.

Abstract: A process is described for growing at least one layer doped with a transition element of cobalt on a substrate by introducing a source of indium, such as tri ethyl indium, (C.sub.2 H.sub.5).sub.3 In or, a source of a group V element, a source of the transition element, such as cobalt nitrosyl tricarbonyl CO(NO)(CO).sub.3, and a source of phosphorus, to the substrate heated in an inert or reducing atmosphere at a pressure substantially between 1/100 atmosphere and one atmosphere to grow at least one semi-insulating semiconductor layer on the substrate.

Abstract: High resistivity In-based compound Group III-V epitaxial layers are used to prevent substantial current flow through a region of a semiconductor device, such as a CSBH, DCPBH, EMBH or CMBH laser, a LED, a photodiode, a HBT, or a FET. Also disclosed is a hydride VPE process for making the high resistivity material doped with Fe. The Fe is supplied by a volatile halogenated Fe compound, and the extend of pyrolysis of the hydride is limited to allow transport of sufficient dopant to the growth area.

Abstract: In a method for Liquid Phase Epitaxy (LPE) of semi-insulating InP, a solution of P, Ti and a p-type dopant in molten In is cooled in a non-oxidizing ambient at a surface of a substrate to grow an epitaxial layer of doped InP on the surface. The concentration of p-type dopant in the solution is such as to provide a concentration of p-type dopant in the grown epitaxial layer greater than the aggregate concentration of any residual contaminants in the grown epitaxial layer, and the concentration of Ti in the solution is such as to provide a concentration of Ti in the grown epitaxial layer greater than the concentration of p-type dopant in the grown epitaxial layer. The required melt concentrations are determined empirically. The method can be performed at temperature below 650 degrees Celsius and is particularly suited to the LPE growth of semi-insulating InP to isolate InP-InGaAsP buried heterostructure lasers.

Abstract: A method for producing thin conductive or semiconductive layers embedded in silicon in the manufacture of structures for integrated circuits and the like. The invention is characterized by implanting metal atoms (14) in a silicon substrate (15) to a pre-determined nominal depth, and subsequently causing the implanted metal atoms to be redistributed, to form a conductive or a semiconductive layer (16), by heat-treating the silicon substrate (15).

Abstract: Semi-insulating epitaxial layers of Group III-V based semiconductor compounds are produced by an MOCVD process through the use of bis arene titanium sources, such as cyclopentadienyl cycloheptatrienyl titanium and bis (benzene) titanium.

Abstract: A semiconductor quantized layered structure comprising first and second different semiconductor materials comprising compound semiconductors from both the Group III and Group V elements and forming a plurality of alternate layers, each interfaced to its adjacent layer in a semiconductor homojunction or heterojunction. The bottom of the conduction bands of the first and second materials are at different energy levels and the tops of the valence bands of the first and second materials are at different energy levels. The bottoms of the conduction bands of the first and second materials form a plurality of serially arranged potential wells and barriers due to differences in the band structures of the different materials forming alternate layers and the interfacing of the layers forming heterojunctions so that the thinness of the layers will spatially localize electrons to obtain quantized electron states in one dimension transverse to the longitudinal extent of said layers.

Abstract: Disclosed is a structure of a semiconductor integrated circuit device including circuit elements such as a bipolar transistor and I.sup.2 L. The structure comprises a buried layer formed by the ion implantation method using an insulating layer, having a window with tapered edges at the surface of semiconductor substrate, as a mask. A part of the buried layer appears at the surface of the semiconductor substrate, thus establishing the connection of electrodes. The circuit element is formed in the region bounded by the buried layer and the window.

Abstract: An epitaxially grown high resistivity crystalline layer of gallium arsenide is produced in a reactor vessel with a predetermined amount of carbon dioxide introduced during growth of the high resistivity gallium arsenide (GaAs) crystalline layer to provide carbon as a dopant. Thus, a plurality of carbon atoms is provided in the crystal, such carbon atoms having electrons at energy levels between a valance energy band and a conduction energy band of the GaAs crystal. With these energy levels, the carbon atoms are substantially ionized at room temperature by accepting a plurality of electrons from the valance band of the GaAs. The presence of these carbon ions in the crystal compensates for a stoichiometric defect which occurs during epitaxial growth of the GaAs crystalline layer. This results in a high resistivity layer which provides a buffer layer between a GaAs substrate and an active GaAs layer.

Abstract: A semiconductor device and a method of manufacturing the same are disclosed wherein a semi-insulating film having a high trap density is formed on a semiconductor substrate so as to prevent charges from remaining in the semi-insulating film and to prevent a change in carrier density at the substrate surface upon irradiation thereof with radiation. The lifetime of minority carriers can be easily controlled without decreasing the junction breakdown voltages.

Abstract: A process is disclosed for preparing silicon wafers having a high quality, high lifetime surface layer and a bulk region characterized by a low lifetime and by a high density of precipitated oxygen gettering sites. A wafer having a relatively high concentration of interstitial oxygen is heated in a reducing ambient at a sufficiently high temperature and a sufficiently long time to cause a surface layer to be denuded of oxygen related defects and dislocations. The temperature is then ramped down to a lower temperature and the wafer is maintained at this lower temperature for a sufficient time to allow precipitation of oxygen within the bulk of the wafer.

Abstract: A method of improving field-effect transistors, and the product thereof, wherein the resistivity of the upper layer of the source-gate channel region of a GaAs field-effect transistor (FET) may be selectively raised is disclosed. Impurity ions are implanted in the source-gate channel region followed by a much shallower implantation of boron in the same region. The boron ion concentration should exceed the N+ impurity ion concentration by a factor of 2 or more.