Abstract: A method of forming shallow junctions in a CMOS transistor is disclosed. The method comprises the steps of: (a) forming a diffusion source layer on a N-well region, a P-well region, field oxide layer, and the gates of a CMOS transistor; (b) forming a photoresist layer over the P-well region; (c) carrying out p-type ion implantation to dope a part of the diffusion source layer on the P-well region; (d) removing the photoresist layer on the P-well region; (e) forming a photoresist layer over the N-well region; (f) carrying out n-type ion implantation to dope the other part of the diffusion source layer on the N-well region; (g) removing the photoresist layer on the N-well region; and (h) oxidizing the diffusion source layer and driving the ions therein into the P-well and N-well regions to form shallow junctions, respectively. The present invention has several advantages. First, it is compatible with the conventional CMOS process.

Abstract: A process for making a vertical PNP transistor and a transistor made by the process includes providing a highly doped semiconductor substrate (10) of P conductivity type. A first lightly doped P- layer (12) is epitaxially grown on the substrate (10). An N+ type buried layer impurity (18) is introduced into a surface region of the first lightly doped layer (12) that will underlie and define an island in which the vertical transistor will be constructed. A second lightly doped P- layer (16) is epitaxially grown on the first lightly doped layer (12) and the buried layer impurity (18). An N+ type isolation impurity is diffused into the second layer to form wells to laterally enclose an island (22) of the second layer (16) above the buried layer impurity (18). An N type base impurity (28) is diffused into the island (22) region of the second layer (16), and a P type emitter impurity (30) is diffused into the base region (28).

Abstract: A semiconductor deposition and oxidation process using a single furnace cycle. The temperature and gas mixture is stabilized inside the furnace prior to introduction of a dopant at a relatively low temperature. The temperature of the chamber is then ramped-up and the dopant is diffused into the wafer in an inert ambient. The temperature is then ramped-up again and oxygen is introduced to produce an oxide layer. The wafers are then removed from the furnace and any residue of the dopant within the chamber is effectively neutralized by introducing a high flow of oxygen.

Abstract: A technique for doping silicon material or other semiconductors uses gas phase dopant sources under reduced pressure in a radiantly heated, cold-wall reactor. The technique is applied to the automated integrated circuit manufacturing techniques being adopted in modern fabrication facilities. The method includes placing a substrate comprising semiconductor material on a thermally isolated support structure in a reduced pressure, cold-wall reaction chamber; radiantly heating the substrate within the reaction chamber to a controlled temperature; flowing a gas phase source of dopant at controlled pressure and concentration in contact with the substrate so that the dopant is absorbed by the substrate, and annealing the substrate. The substrate may be first coated with a layer of polycrystalline semiconductor, and then gas phase doping as described above may be applied to the polycrystalline layer.

Abstract: Very shallow electrical junctions may be formed in an oxide free surface of a semiconductor by introducing an inert or reducing gas into a vacuum processing chamber, heating the semiconductor to between 750.degree. C. and 1100.degree. C., introducing a dilute solution of a dopant gas into the chamber, and exposing the semiconductor to the gases for about 0.5 to about 100 minutes, preferably between 10 and 30 minutes. A relatively wide range of surface dopant concentrations may be achieved thereby with dopant concentration controlled independent of junction depth. Non-oxide free semiconductor surfaces may be made oxide free by first heating the semiconductor surface in the presence of the reducing gas. This technique provides uniform surface dopant concentrations and is suitable for the formation of junctions in deep trenches and other features having high aspect ratios.

Abstract: A process for the production of a low-loss optical waveguide in an epitaxial silicon film is employed to form a silicon structural element with integrated electronic components in a silicon substrate. Between the silicon substrate and the epitaxial silicon film is an insulating film. The epitaxial film consists of silicon-on-insulator (SOI) material, which is an uncommon material. In order to carry out this process relatively cheaply, a lightly doped epitaxial silicon film is applied to the silicon substrate. A substance germanium and having a refractive index with a real component higher than that of silicon is diffused into the epitaxial silicon film.

Abstract: A method is provided for diffusion doping of semiconductor chips and wafers, in particular silicon chips and wafers, at peak concentrations of greater than about 3.times.10.sup.19 atoms/cm.sup.3. The semiconducting material to be doped is placed in a furnace wherein the furnace contains an atmosphere of a carrier gas and a dopant containing gas. The doping containing gas is greater than about 0.1 volume percent of the total volume in the furnace chamber. The pressure of the composite gas is greater than about 0.1 Torr. The composite gas has an oxidizing agent concentration of less than about 1 part per million. The method permits the direct doping of a silicon surface to form a shallow n-doped region having a high peak concentration by a diffusion process thereby eliminating damage to the silicon surface from ion implantation which is the commonly used method to achieve these high doping concentrations. Since the method is nondirectional trench sidewalls can be doped at high concentrations.

Abstract: Si.sub.2 H.sub.6 and PH.sub.3 are introduced into a heated reaction tube in which a plurality of substrates are contained under vacuum pressure, thereby forming phosphor-doped silicon films on the substrates. By changing the flow of Si.sub.2 H.sub.6, a first layer consisting of a silicon film containing phosphor of low density, a second layer substantially consisting of phosphor, and a third layer consisting of substantially the same composition as that of the first layer are deposited in the order mentioned. Thereafter, the first through third layers are heated, thereby diffusing phosphor contained in the second layer. Thus, an integral film of uniform impurity density is formed from the first through third layers.

Abstract: A method of forming on a substrate a waveguide lens having a predetermined distribution of refractive index, for converging or diverging light rays which propagate through a two-dimensional waveguide formed on a surface of the substrate. The method includes a step of forming a film of a diffusion metal having a constant thickness, a step of removing local portions of said film, by using a mask so that a density of the removed local portions of the film per unit area is continuously varied, and a step of effecting thermal diffusion of the remainder of the film into the substrate. Alternatively, the method includes a step of forming a mask having a multiplicity of separate openings whose density per unit area is continuously varied, a step of exposing a multiplicity of separate exposed areas of the substrate aligned with the separate openings to a material which serves to change a refractive index of the substrate, and a step of moving the material from the surface of the substrate into its interior.

Abstract: A method for manufacturing a amorphous silicon thin film transistor comprises exposing an morphous silicon layer situated between a source electrode and a drain electrode to a gas phase atmosphere having a gas containing an impurity forming an acceptor, then activating said impurity with an electric field or light energy and doping the activated impurity into said amorphous silicon layer. The gas may be a hydrogen compound and it may include an oxidizing gas.

Abstract: An intermediate structure in the fabrication of a metal-oxide semiconductor field-effect transistor is made from a substrate of p+ silicon having an elongate insulated gate structure on its main face. First and second areas of the main face are exposed along first and second opposite sides respectively of the gate structure. Donor impurity atoms are introduced into the substrate by way of at least the first area of the main face, to achieve a predetermined concentration of electrons in a region of the substrate that is subjacent the first area of the main face. The gate structure is opague to the impurity atoms. A sidewall of silicon dioxide is formed along the first side of the gate structure, whereby a strip of the first area of the main face is covered by the sidewall and other parts of the first area remain exposed adjacent the sidewall.

Abstract: Planar diffusion sources are provided wherein the source is a wafer of inert material, preferably silicon or silicon dioxide and wherein the wafer acts as a substrate for a surface coating comprising a salt, preferably the oxide, of the dopant element. An inert oxide such as aluminum oxide or silicon dioxide may also be included in the coating. When applied to the substrate as a paste or slurry and fired to suitable temperatures, the dopant oxide coating tightly adheres to the substrate wafer. The coated diffusion source is placed alongside semi-conductor wafers in a diffusion furnace; where, at diffusion temperatures, the dopant element volatilizes and diffuses into the surface of the semi-conductor material. The diffusion source can be reused numerous times.