Diffusion Length Patents (Class 148/DIG32)
  • Patent number: 6096628
    Abstract: A semiconductor device and a method of manufacturing a semiconductor device with an effective channel length that is less than the physical gate length avoids requiring improving the masking, lithography and etching process steps by increasing the implantation energy of a pre-amorphizing implant. The pre-amorphizing implant is performed after the doping of the source and drain areas and after activation of the dopants. The implantation energy is sufficient to introduce damage into the substrate to allow for increased movement of the dopants in the substrate. Subsequent annealing steps performed during silicidation cause the source and drain areas to expand toward each other and reduce the effective channel length. This channel length reduction leads to improved device performance through higher I.sub.dsat, etc.
    Type: Grant
    Filed: November 6, 1998
    Date of Patent: August 1, 2000
    Assignee: Advanced Micro Devices, Inc.
    Inventors: David C. Greenlaw, Jan Raebiger
  • Patent number: 5401674
    Abstract: A method is provided for reducing growth of silicide and the temperatures necessary to produce silicide. Germanium is implanted at a concentration peak density depth below the midline and above the lower surface of a metal layer receiving the implant. Subsequent anneal causes germanide to occupy an area above growing silicide such that consumption of silicon atoms is reduced, and that silicide is formed to a controlled thickness.
    Type: Grant
    Filed: June 10, 1994
    Date of Patent: March 28, 1995
    Assignee: Advanced Micro Devices
    Inventors: Mohammed Anjum, Ibrahim Burki, Craig W. Christian
  • Patent number: 4965220
    Abstract: A semiconductor integrated circuit device is disclosed which comprises a bipolar transistor and a field effect transistor, in which a gate electrode of the field effect transistor and a collector electrode of the bipolar transistor are formed from a common electrode layer of a high impurity concentration, and in which the collector region of the bipolar transistor comprises a region of a high impurity concentration having a conductivity type the same as that of the collector region of the bipolar transistor.
    Type: Grant
    Filed: February 6, 1989
    Date of Patent: October 23, 1990
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroshi Iwasaki