Diffusion Thru A Layer Patents (Class 148/DIG35)
  • Patent number: 5693577
    Abstract: A sensor 20 is formed on semiconductor substrate 22. Dielectric layers 23 and 24 are formed on the face and backside of substrate 22, respectively. Metal leads 26 and 28 contact the substrate through openings in the dielectric layer 23. The leads 26 and 28 are also connected to the set of interleaved longitudinal contact fingers 27 and 29. Additionally, a pair of backside contacts 30 and 32 are formed on the dielectric layer 24. The backside contact 30 is in contact only with the metal lead 26 through a conductive region 34.
    Type: Grant
    Filed: April 12, 1996
    Date of Patent: December 2, 1997
    Assignee: Texas Instruments Incorporated
    Inventors: William R. Krenik, Mark Appleton
  • Patent number: 5674763
    Abstract: Disclosed herein is a semiconductor device comprising a semiconductor substrate, a well region provided in the surface of the substrate, a plurality of MOSFETs provided in the well region. The well region has parts having a low surface impurity concentration. Some of the MOSFETs have their channel regions provided in those parts of the well region which have the low surface impurity concentration. The other MOSFETs have their channel regions provided in other parts of the well region.
    Type: Grant
    Filed: April 25, 1995
    Date of Patent: October 7, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Souichi Sugiura, Masaru Koyanagi
  • Patent number: 5670393
    Abstract: An electrical circuit and method combine junction field effect transistors (JFET) and metal oxide semiconductor (MOS) circuits in series between V.sub.DD and ground, with a feedback of output voltage to control current from V.sub.DD to ground. The electrical circuit comprises a complementary metal oxide semiconductor (CMOS) inverter circuit with an input and an output, and a JFET having a gate coupled to the CMOS inverter for feedback to control the JFET. The JFET and CMOS circuitry is formed on a common substrate with the JFET gate junction being formed by implanting impurity dopants through a layer of gate oxide.
    Type: Grant
    Filed: July 12, 1995
    Date of Patent: September 23, 1997
    Assignee: LSI Logic Corporation
    Inventor: Ashok K. Kapoor
  • Patent number: 5587326
    Abstract: In a bipolar junction transistor of an epitaxial planar type comprising a base region, an emitter region formed in the base region, and a poly-silicon layer as an emitter poly-silicon electrode layer overlying the emitter region, the poly-silicon layer being used as an impurity diffusion source for forming the emitter region in fabrication of the transistor, the emitter poly-silicon electrode layer comprises a poly-silicon film containing an additive of one of C, O, and P overlying the emitter region and a poly-silicon layer overlying the poly-silicon film. An impurity is doped in the poly-silicon layer and is diffused into the base region through the poly-silicon film to form the emitter region in the base region in fabrication of the transistor. The poly-silicon film contains the additive and serves to prevent the poly-silicon film and the poly-silicon layer from grain growth which badly affects the impurity diffusion for forming the emitter region.
    Type: Grant
    Filed: October 23, 1992
    Date of Patent: December 24, 1996
    Assignee: NEC Corporation
    Inventor: Hisashi Takemura
  • Patent number: 5569611
    Abstract: In a method of manufacturing a bipolar transistor, an oxide film pattern is formed on an epitaxial collector layer of a first conductive type which is formed on a buried layer of the first conductive type. A selectively-ion-implanted-collector (SIC) region is then formed in the collector layer, and after that, a base layer is grown on the SIC region with an inversely graded impurity distribution profile.
    Type: Grant
    Filed: October 12, 1994
    Date of Patent: October 29, 1996
    Assignee: NEC Corporation
    Inventor: Kiyotaka Imai
  • Patent number: 5536684
    Abstract: A process for the formation of a planar epitaxial cobalt silicide and for the formation of shallow conformal junctions for use in semiconductor processing. A cobalt silicide and titanium nitride bilayer is formed. The titanium nitride layer is chemically removed. Ions with or without a dopant are then implanted into the cobalt silicide layer. During the ion implantation, at least a portion of the cobalt silicide layer is transformed into an amorphous cobalt silicon mixture while the non-amorphous portion remains single crystal. If the ion implantation contains dopants, then after the implantation is completed, both the amorphous and non-amorphous portions of the cobalt silicide layer contain the dopants. The substrate is then annealed in either an ambient comprising a nitrogen gas or in an oxidizing ambient. During the anneal, the amorphous portion of the silicon substrate recrystallizes into a single crystal cobalt silicide layer.
    Type: Grant
    Filed: June 30, 1994
    Date of Patent: July 16, 1996
    Assignee: Intel Corporation
    Inventors: M. Lawrence A. Dass, Peng Cheng, David B. Fraser
  • Patent number: 5529954
    Abstract: A semiconductor device includes a first metal film formed on a semiconductor substrate, a second metal film formed on the first metal film and containing silver as a main component, and a protective film containing a metal element of the first metal film and covering at least the upper surface of the second metal film. The protective film is formed by annealing in an atmosphere containing a predetermined element. That is, the metal element of the first metal film is diffused into the second metal film and reacts with the predetermined element in the atmosphere on the surface of the second metal film, thereby forming the protective film. Aggregation of silver is prevented in the presence of the protective film.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: June 25, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tadashi Iijima, Hisako Ono, Yukihiro Ushiku, Akira Nishiyama, Naomi Nakasa
  • Patent number: 5494852
    Abstract: A semiconductor deposition and oxidation process using a single furnace cycle. The temperature and gas mixture is stabilized inside the furnace prior to introduction of a dopant at a relatively low temperature. The temperature of the chamber is then ramped-up and the dopant is diffused into the wafer in an inert ambient. The temperature is then ramped-up again and oxygen is introduced to produce an oxide layer. The wafers are then removed from the furnace and any residue of the dopant within the chamber is effectively neutralized by introducing a high flow of oxygen.
    Type: Grant
    Filed: July 28, 1993
    Date of Patent: February 27, 1996
    Assignee: Sony Electronics Inc.
    Inventor: Jon A. Gwin
  • Patent number: 5488002
    Abstract: Manufacturing a double polysilicon layer self-aligned type bipolar transistor. A polysilicon layer for emitter impurity diffusion is formed prior to the formation of a polysilicon layer for leading out a base. A first polysilicon layer containing impurities for base impurity diffusion is deposited over the entire surface of a semiconductor structure. After the first polysilicon layer is patterned into a predetermined shape, an intrinsic base layer is formed by thermally diffusing impurities from a base impurity diffusion source. Subsequently, a second polysilicon layer containing emitter impurities is formed over the base impurity diffusion source, and then patterning is performed such that the first and second polysilicon layers remain in a region narrower than the base impurity diffusion source. Thereafter, an emitter layer is formed by thermal diffusion.
    Type: Grant
    Filed: September 8, 1994
    Date of Patent: January 30, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koji Kimura, Shin-ichi Taka
  • Patent number: 5472527
    Abstract: A method for forming unsegregated metal oxide-silver composites includes preparing a precursor alloy comprising silver and precursor elements of a desired metal oxide and oxidizing the alloy under conditions of high oxygen activity selected to permit diffusion of oxygen into silver while significantly restricting the diffusion of the precursor elements into silver, such that oxidation of the precursor elements to the metal oxide occurs before diffusion of the metallic elements into silver. Further processing of the metal oxide composite affords an oxide superconducting composite with a highly unsegregated microstructure.
    Type: Grant
    Filed: June 24, 1993
    Date of Patent: December 5, 1995
    Assignee: American Superconductor Corporation
    Inventors: Alexander Otto, Lawrence J. Masur, Eric R. Podtburg, Kenneth H. Sandhage
  • Patent number: 5393687
    Abstract: A new method of forming source/drain buried contact junctions is described. The method of forming a buried contact to a source/drain junction or other active device region in a silicon substrate is described. A first polysilicon layer is deposited over the surface of a silicon substrate. A second layer of polysilicon is deposited over the first layer of polysilicon wherein the polysilicon grain boundaries of the first and second polysilicon layers will be mismatched. The second polysilicon layer is doped. The grain boundary mismatch will slow the diffusion of the dopant into the silicon substrate. The dopant is driven in to form the buried contact with a shallow junction.
    Type: Grant
    Filed: December 16, 1993
    Date of Patent: February 28, 1995
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventor: Mong-Song Liang
  • Patent number: 5324684
    Abstract: A technique for doping silicon material or other semiconductors uses gas phase dopant sources under reduced pressure in a radiantly heated, cold-wall reactor. The technique is applied to the automated integrated circuit manufacturing techniques being adopted in modern fabrication facilities. The method includes placing a substrate comprising semiconductor material on a thermally isolated support structure in a reduced pressure, cold-wall reaction chamber; radiantly heating the substrate within the reaction chamber to a controlled temperature; flowing a gas phase source of dopant at controlled pressure and concentration in contact with the substrate so that the dopant is absorbed by the substrate, and annealing the substrate. The substrate may be first coated with a layer of polycrystalline semiconductor, and then gas phase doping as described above may be applied to the polycrystalline layer.
    Type: Grant
    Filed: February 25, 1992
    Date of Patent: June 28, 1994
    Assignee: AG Processing Technologies, Inc.
    Inventors: Ahmad Kermani, Kristian E. Johnsgard, Carl Galewski
  • Patent number: 5308776
    Abstract: A method of manufacturing an SOI type substrate by forming a poly-Si layer on the surface of the one Si single crystal wafer (A), then forming a SiO.sub.2 film on the surface of the other Si single crystal wafer (B), bonding these wafers with each other, removing the end portion of the one Si single crystal wafer (A) by a polishing method leaving a part of this Si single crystal wafer as an element forming layer, providing a high concentration impurity region by selectively introducing impurity into the element forming layer and forming a high concentration impurity diffused region in the vicinity of interface with the poly-Si layer of the element forming layer by heat treatment; and a bipolar transistor formed on an SOI type substrate forming a high concentration impurity diffused region as a buried collector layer.
    Type: Grant
    Filed: February 18, 1992
    Date of Patent: May 3, 1994
    Assignee: Fujitsu Limited
    Inventor: Hiroshi Gotou
  • Patent number: 5275969
    Abstract: A method for diffusing a P type impurity into a semiconductor includes the steps of selectively implanting ions of a first P type impurity into a semiconductor substrate and thermally diffusing a second P type impurity into the semiconductor substrate containing at least a region where the first P type impurity ions are implanted. Therefore, the diffusion speed of the P type impurity is increased in the ion implantation region, whereby the P type impurity diffusion region which almost corresponds to the ion implantation region can be obtained and P type diffusion can be performed in high concentration with high precision.
    Type: Grant
    Filed: April 7, 1993
    Date of Patent: January 4, 1994
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Shogo Takahashi
  • Patent number: 5272108
    Abstract: A gallium nitride semiconductor light-emitting device comprising: a substrate of semiconductor or insulator; an N layer of n-type gallium nitride semiconductor (Al.times.Ga.sub.1-x N:0.ltoreq..times..ltoreq.1); an I layer of semiinsulating gallium nitride semiconductor (Al.sub.x Ga.sub.1-x N:0.ltoreq..times..ltoreq.1); a first electrode formed on the I layer; a low-resistance region extending from the first electrode through the I layer at least to the N layer and formed by diffusion of the material of the first electrode; and a second electrode formed on the I layer isolatedly from the first electrode.
    Type: Grant
    Filed: February 26, 1992
    Date of Patent: December 21, 1993
    Assignees: Kabushiki Kaisha Toyota Chuo Kenkyusho, Toyoda Gosei Co., Ltd.
    Inventor: Takahiro Kozawa
  • Patent number: 5259885
    Abstract: A method of preparing a laminated ceramic. The method includes preparing a precursor having at least one noble metal element component and at least two non-noble metal elements. The precursor is exposed to a first environment to form an oxidized zone having a first concentration of a primary ceramic phase containing the non-noble metal elements. The precursor is next exposed to a second environment to form a second oxidized zone having a second concentration of the primary ceramic phase, the second concentration being less than the first concentration. The precursor is repeatedly exposed to each environment to form a plurality of zones with the first concentration of the primary ceramic phase separated by zones with the second concentration of the ceramic.
    Type: Grant
    Filed: April 3, 1991
    Date of Patent: November 9, 1993
    Assignee: American Superconductor Corporation
    Inventor: Kenneth H. Sandhage
  • Patent number: 5252514
    Abstract: A process for the production of a low-loss optical waveguide in an epitaxial silicon film is employed to form a silicon structural element with integrated electronic components in a silicon substrate. Between the silicon substrate and the epitaxial silicon film is an insulating film. The epitaxial film consists of silicon-on-insulator (SOI) material, which is an uncommon material. In order to carry out this process relatively cheaply, a lightly doped epitaxial silicon film is applied to the silicon substrate. A substance germanium and having a refractive index with a real component higher than that of silicon is diffused into the epitaxial silicon film.
    Type: Grant
    Filed: March 2, 1992
    Date of Patent: October 12, 1993
    Assignee: Siemens Aktiengesellschaft
    Inventor: Bernd Schuppert
  • Patent number: 5151382
    Abstract: A semiconductor body (1 ) is provided having a first region (4) of one conductivity type adjacent one major surface (2). An insulating layer (5) is formed on the one major surface and masking means (6,7) are used to form over first and second areas (20 and 21) of the one major surface (2) windows (8,9,10) in the insulating layer (5) through which impurities are introduced to form a relatively highly doped region (11) of the opposite conductivity type adjacent the first area (20) and a relatively lowly doped region (12) of the opposite conductivity type adjacent the second area (21). The surface (5a) of the insulating layer (5) is exposed prior to introducing impurities of the one conductivity type for forming a region (13) within the relatively lowly doped region (12) of the opposite conductivity type and with a dose sufficient to form the region (13) but not sufficient to overdope the relatively highly doped region (11) so avoiding the need to mask the first area (20) during this step.
    Type: Grant
    Filed: September 17, 1991
    Date of Patent: September 29, 1992
    Assignee: U.S. Philips Corp.
    Inventors: Wilhelmus J. M. J. Josquin, Wilhelmus C. M. Peters, Albertus T. M. Van De Goor
  • Patent number: 5141895
    Abstract: A semiconductor device is formed by a process in which a diffusant penetration layer and a diffusant source layer containing a boron dopant are formed overlaying the surface of a semiconductor substrate. The diffusant source layer is annealed to cause the boron dopant to controllably diffuse through the diffusant penetration layer to the semiconductor substrate to form a doped region at the surface. The diffusant source layer and the diffusant penetration layer are removed and a gate insulator is formed on the substrate surface overlaying the doped region. An N doped gate electrode is then formed overlaying the gate insulator.
    Type: Grant
    Filed: January 11, 1991
    Date of Patent: August 25, 1992
    Assignee: Motorola, Inc.
    Inventors: James R. Pfiester, Howard C. Kirsch
  • Patent number: 5122478
    Abstract: A method for diffusing an impurity into a semiconductor includes producing a first semiconductor layer which does not include an element which alloy-reacts with the impurity on a surface of a compound semiconductor which includes a constitutional element that alloy-reacts with the impurity, covering the first semiconductor layer with a second layer including the impurity, and thereafter annealing to diffuse the impurity into the compound semiconductor.
    Type: Grant
    Filed: October 11, 1990
    Date of Patent: June 16, 1992
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Fumito Uesugi
  • Patent number: 5120677
    Abstract: A method for introducing an impurity into a polysilicon formed on an insulating film is described. A silicate glass layer (13) containing As is formed on a polysilicon layer (12) formed on an insulating film (2) and is thermally treated to introduce As into the polysilicon layer (12). The silicate glass layer (13) has a concentration of arsenic of not less than 25 wt. %, calculated as As.sub.2 O.sub.3 and the thermal treatment is effected in an atmosphere of a mixed gas of N.sub.2 and O.sub.2 with an oxygen partial pressure ratio of 0.05-0.7 at not lower than 1000.degree. C. for not shorter than 60 minutes.
    Type: Grant
    Filed: November 15, 1990
    Date of Patent: June 9, 1992
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Hidetoshi Wakamatsu
  • Patent number: 5116784
    Abstract: Si.sub.2 H.sub.6 and PH.sub.3 are introduced into a heated reaction tube in which a plurality of substrates are contained under vacuum pressure, thereby forming phosphor-doped silicon films on the substrates. By changing the flow of Si.sub.2 H.sub.6, a first layer consisting of a silicon film containing phosphor of low density, a second layer substantially consisting of phosphor, and a third layer consisting of substantially the same composition as that of the first layer are deposited in the order mentioned. Thereafter, the first through third layers are heated, thereby diffusing phosphor contained in the second layer. Thus, an integral film of uniform impurity density is formed from the first through third layers.
    Type: Grant
    Filed: October 9, 1991
    Date of Patent: May 26, 1992
    Assignee: Tokyo Electron Limited
    Inventor: Harunori Ushikawa
  • Patent number: 5086016
    Abstract: A contact is provided in a self-aligned manner to a doped region a semiconductor substrate by first forming a layer of a transition metal-boride compound over a selected region on the substrate. A layer of a transition metal-nitride compound is formed over the layer of transition metal-boride compound, and the structure is heated to drive dopant from the layer of transition metal-boride compound into the substrate. The transition metal-boride/transition metal nitride layers are patterned to leave a contact to the doped region.
    Type: Grant
    Filed: October 31, 1990
    Date of Patent: February 4, 1992
    Assignee: International Business Machines Corporation
    Inventors: Stephen B. Brodsky, Rajiv V. Joshi, John S. Lechaton, James G. Ryan, Dominic J. Schepis
  • Patent number: 5084412
    Abstract: According to this invention, there is provided to a semiconductor device comprising a semiconductor substrate on which an element is formed, an insulating interlayer formed on the semiconductor substrate, and a wiring layer having a structure in which a surface of a copper layer in a crystal state is covered with a nitride of a metal not forming an intermetallic compound with copper and the metal and/or the metal nitride is present at grain boundaries of the copper layer.
    Type: Grant
    Filed: October 1, 1990
    Date of Patent: January 28, 1992
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yasushi Nakasaki
  • Patent number: 4994410
    Abstract: A semiconductor device, device metallization, and method are described. The device metallization, which is especially designed for submicron contact openings, includes titanium silicide to provide a low resistance contact to a device region, titanium nitride and sputtered tungsten to provide a diffusion barrier, etched back chemical vapor deposited tungsten for planarization, and aluminum or an aluminum alloy for interconnection.
    Type: Grant
    Filed: February 16, 1990
    Date of Patent: February 19, 1991
    Assignee: Motorola, Inc.
    Inventors: Shih W. Sun, Jen-Jiang Lee
  • Patent number: 4945070
    Abstract: A CMOS device having shallow source and drain regions is formed in a body of single crystalline silicon having a major surface by forming in the body adjacent well regions of opposite conductivity type having an isolation region of an insulating material extending into the body from the major surface along the junction of the well regions. Thin layers of silicon oxide are formed on the major surface over each of the well regions, and a gate line of conductive polycrystalline silicon is formed over each of the silicon oxide layers. The side walls of the gate lines are covered with a layer of silicon oxide. A layer of polycrystalline silicon is selectively deposited on the surface of the body at each side of each gate line and on the gate lines. A layer of a refractory metal is deposited on the polycrystalline silicon layer. The polycrystalline silicon layer is heated to cause the metal to react with the silicon and form a metal silicide region at least partially through the polycrystalline silicon layer.
    Type: Grant
    Filed: January 24, 1989
    Date of Patent: July 31, 1990
    Assignee: Harris Corporation
    Inventor: Sheng T. Hsu
  • Patent number: 4897362
    Abstract: A method of forming a high-quality complementary transistor device using bonded wafer technology. The invention includes bonding a handle wafer to a first epitaxial layer and then providing dopants to form the respective N and P buried layers in said first epitaxial layer. A second epitaxial layer is then deposited over the buried layers to provide the device forming regions for the respective transistor devices.
    Type: Grant
    Filed: September 2, 1987
    Date of Patent: January 30, 1990
    Assignee: Harris Corporation
    Inventors: Jose A. Delgado, George Bajor
  • Patent number: 4871690
    Abstract: Different diffusion rates can be made operative relative to diffusion disordering in designated areas of a thin active layer or of quantum well feature compared to thermal disordering in other areas thereof where disordering is not desired by the selective placement of migratory defects in a semiconductor support means, such as a semiconductor substrate or semiconductor support layer for supporting subsequently epitaxially deposited semiconductor layers. Such migratory defects as used herein are intended to include impurities and/or other lattice defects initially introduced into the semiconductor support means prior to epitaxial deposition of semiconductor layers constituting the semiconductor structure, wherein at least one of such layers comprises a thin active layer (i.e.
    Type: Grant
    Filed: January 27, 1988
    Date of Patent: October 3, 1989
    Assignee: Xerox Corporation
    Inventors: Nick Holonyak, Jr., Robert D. Burnham
  • Patent number: 4780425
    Abstract: The present invention relates to a semiconductor device and a method of producing the same. According to this method, a lower diffusion layer of a double isolation diffusion area is attached to a surface of a substrate, an epitaxial layer being formed on the lower diffusion layer, the lower diffusion layer being largely outdiffused upwardly in the epitaxial layer and simultaneously an element diffusion area being deeply diffused from a surface of the epitaxial layer, and then an upper diffusion layer of the double isolation diffusion area being shallowly diffused from the surface of the epitaxial layer. Thus, the lateral expansion of the upper diffusion layer of the double isolation diffusion area can be suppressed and the integrated extent can be improved.
    Type: Grant
    Filed: November 12, 1987
    Date of Patent: October 25, 1988
    Assignee: Sanyo Electric Co., Ltd.
    Inventor: Teruo Tabata
  • Patent number: 4711514
    Abstract: A method of forming a tapered optical waveguide within a substrate (2). An appropriate substrate (2) is coated with a layer of barrier material (4) such as silicon dioxide which provides a relatively tight matrix relative to the open matrix of the substrate (2). The barrier material (4) is deposited on the substrate with a sloping variable thickness that is inversely related to the desired depth of the waveguide taper. The barrier material (4) can be deposited through a vacuum deposition technique and subsequently subjected to ion-milling to provide the desired taper. An appropriate source of metal ions (6), such as silver, capable of being transferred, such as by diffusion into the substrate (2) for increasing the refractive index and thereby defining a waveguide, is then transmitted to and through the barrier material (4).
    Type: Grant
    Filed: January 11, 1985
    Date of Patent: December 8, 1987
    Assignee: Hughes Aircraft Company
    Inventors: Gregory L. Tangonan, Huan-Wun Yen, David L. Persechini
  • Patent number: 4643777
    Abstract: There is disclosed a method of manufacturing a semiconductor device comprising the steps of forming a polysilicon film on a semiconductor substrate through an oxidation film, forming a mask of a predetermined pattern on the polysilicon film, forming a molybdenum film on the polysilicon film, and silicifying those regions of said molybdenum film not covered by the mask so that a structure of the uncovered molybdenum film regions and those regions of the polysilicon film located under the uncovered molybdenum regions have low resistance, while a region of the molybdenum film covered by the mask has high resistance.
    Type: Grant
    Filed: December 19, 1984
    Date of Patent: February 17, 1987
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takeo Maeda
  • Patent number: 4574469
    Abstract: A process is described for producing isolated semiconductor devices in a common substrate which have self-aligned and pre-located isolation walls, buried layers, and channel-stops. The isolation walls are formed from a stacked arrangement of a dielectric region and a non-single crystal semiconductor region, above a doped channel-stop region. A single mask layer determines the location and spacing of the non-single crystal portion of the isolation walls, the channel-stops, and the buried layers.
    Type: Grant
    Filed: September 14, 1984
    Date of Patent: March 11, 1986
    Assignee: Motorola, Inc.
    Inventors: Sal Mastroianni, Carroll Casteel, Terry S. Hulseweh