Diffusion, Nonselective Patents (Class 148/DIG36)
  • Patent number: 5569611
    Abstract: In a method of manufacturing a bipolar transistor, an oxide film pattern is formed on an epitaxial collector layer of a first conductive type which is formed on a buried layer of the first conductive type. A selectively-ion-implanted-collector (SIC) region is then formed in the collector layer, and after that, a base layer is grown on the SIC region with an inversely graded impurity distribution profile.
    Type: Grant
    Filed: October 12, 1994
    Date of Patent: October 29, 1996
    Assignee: NEC Corporation
    Inventor: Kiyotaka Imai
  • Patent number: 5182219
    Abstract: The surface area of a junction-isolated tub in a silicon epitaxial layer grown on a silicon substrate is increased by introducing dopant into surface portions of the tub to effectively push back the junction between the tub and the isolation region. The junction-isolation region surrounding the tub typically has a dopant concentration profile which decreases from the center of the junction-isolation region towards the junction with the tub. By increasing the surface concentration of dopant in the tube, the net dopant concentration of peripheral portions of the junction-isolation region is converted, thereby effectively increasing the size of the surface of the tub. The dopant concentration in the surface of the entire tub can be increased, or only the periphery of the tub can have increased dopant concentration, thereby maintaining the breakdown voltage of devices fabricated in the tub.
    Type: Grant
    Filed: August 1, 1991
    Date of Patent: January 26, 1993
    Assignee: Linear Technology Corporation
    Inventors: Carl Nelson, Jia-Tarng Wang
  • Patent number: 5043295
    Abstract: Process of making an IC chip with thin film resistors, and IC chips made by such process, wherein a chip substrate first is covered with layers of thin film and interconnect material (with an intermediate barrier layer if needed), such layers being etched away in predetermined regions in accordance with the metal interconnect pattern, the remaining layered material being aligned vertically, and thereafter, in a section of the remaining material, etching away the interconnect material (and barrier material if used) to expose the thin film material to form a thin film resistor which is self-aligned withe the adjoining sections of interconnect conductors. The material in the predetermined regions may be etched by a dry-etch (plasma) or by a wet-etch.
    Type: Grant
    Filed: June 20, 1989
    Date of Patent: August 27, 1991
    Inventors: Paul A. Ruggerio, Cynthia E. Anderson