Diffusion-deposition Patents (Class 148/DIG37)
  • Patent number: 5338697
    Abstract: An exposed active surface is prepared on a major surface of a semiconductor substrate. A source gas containing an impurity component is applied to the exposed active surface to adsorb thereon a film of the impurity component so as to form a barrier region along the major surface of the semiconductor substrate. A semiconductor device is formed on the major surface of the semiconductor substrate and is protected by the barrier region.
    Type: Grant
    Filed: December 3, 1990
    Date of Patent: August 16, 1994
    Assignee: Seiko Instruments Inc.
    Inventors: Kenji Aoki, Tadao Akamine, Naoto Saito
  • Patent number: 5183777
    Abstract: A method of forming a shallow junction comprises the step of: forming a film including a hydrogen compound with one element selected from the group of boron, phosphorus arsenic to a thickness of several atom layers to 1000 .ANG. on a silicon substrate and annealing the film, whereby an impurity region having a depth of 1000 .ANG. or less and an impurity concentration of 10.sup.18 to 10.sup.21 cm.sup.-3 is formed in the surface layer of the silicon layer.
    Type: Grant
    Filed: September 13, 1991
    Date of Patent: February 2, 1993
    Assignee: Fujitsu Limited
    Inventors: Masahiko Doki, Michiko Takei
  • Patent number: 5171708
    Abstract: A method of diffusing boron into semiconductor wafers is disclosed which essentially includes boron deposition and boron diffusion. The deposition is performed from 900.degree. to 1,000.degree. C. and the diffusion at a temperature of 890.degree. to 1000.degree. C. Oxidation induced stacking faults are greatly reduced.
    Type: Grant
    Filed: July 26, 1991
    Date of Patent: December 15, 1992
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Masatake Katayama, Shoichi Fujiya, Isao Moroga, Masaru Shinomiya
  • Patent number: 5162256
    Abstract: A multiplicity of thin layers are applied on top of each other having alternately comparatively high concentrations of charge carriers and no doping. The thickness and the concentration of charge carriers of the individual layers being are proportioned in such a manner that the desired low concentration of charge carriers is yielded by averaging the multiplicity of layers.
    Type: Grant
    Filed: January 31, 1991
    Date of Patent: November 10, 1992
    Assignee: Aixtron GmbH
    Inventor: Holger Jurgensen
  • Patent number: 5126281
    Abstract: Method for deposit of a p type dopant from a dopant layer into a predetermined region of a III-V semiconductor layer or multiple layers. The p type dopant is deposited in very high concentration in a semiconductor layer adjacent to the predetermined region. A second semiconductor layer, doped with a lower concentration of an n type dopant, is later deposited so that the high concentration p type dopant layer lies between the predetermined region and the n type dopant layer. The p type dopant is diffused into the predetermined region by thermally driven diffusion, which may be carried out at a lower temperature or for a shorter diffusion time interval than with conventional diffusion, and p type dopant diffusion may extend over greater distances.
    Type: Grant
    Filed: September 11, 1990
    Date of Patent: June 30, 1992
    Assignee: Hewlett-Packard Company
    Inventors: Kent A. W. Carey, James B. Williamson, Thomas S. Low, James S. C. Chang
  • Patent number: 5108948
    Abstract: A method of producing a semiconductor device such as a semiconductor laser having a controllably disordered superlattice. The superlattice is grown epitaxially and in the same epitaxial growth process a heavily selenium doped semiconductor layer is also grown in a known spatial relationship to the superlattice. The doped layer is patterned as by etching and then the device is annealed to diffuse selenium impurities from the doped layer. The time and temperature of annealing are controlled such that the impurities diffuse into and thereby disorder regions of the superlattice layer, leaving a non-disordered region which can serve as a resonator in a laser.
    Type: Grant
    Filed: November 17, 1988
    Date of Patent: April 28, 1992
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Takashi Murakami, Kanamf Otaki, Hisao Kumabe
  • Patent number: 4960730
    Abstract: A buried stripe semiconductor light emitting device and a method for producing the device in which the buried stripe functions as an internal resonator, and the device has window regions interposed between the resonator and facets on the external surface of the device. A first phase crystal growth is conducted in which a first cladding layer is grown on a doped substrate. Thereafter, a doped stripe of impurities is introduced into the first cladding layer in electrical contact with the doped substrate. The doped stripe extends longitudinally but terminates short of the facets so that later out-diffusion from the doped stripe will form the window regions. A second phase crystal growth is then conducted which buries the doped stripe internal to the semiconductor, i.e., not projecting through any external surface. The second phase crystal growth comprises an active layer, a second cladding layer and a contact layer successively grown on the first cladding layer.
    Type: Grant
    Filed: September 25, 1989
    Date of Patent: October 2, 1990
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Syoichi Kakimoto
  • Patent number: 4902633
    Abstract: A bipolar integrated circuit requiring less silicon area is provided by the use of a three layer epitaxy on top of a substrate. The first epitaxial layer is of the same conductivity type as the substrate and adds additional height to the substrate surrounding the buried layer. The buried layer serves as a collector and it is surrounded by an isolation area. The top two epitaxial layers are of a conductivity type opposite to that of the substrate with the upper most epitaxial layer having a higher dopant density than does the middle epitaxial layer. A master mask is used to provide self-alignment between the isolation area, a collector plug which makes contact to the buried layer, and a base region.
    Type: Grant
    Filed: May 9, 1988
    Date of Patent: February 20, 1990
    Assignee: Motorola, Inc.
    Inventor: Bertrand F. Cambou
  • Patent number: 4853339
    Abstract: In a process of preparing an infrared sensitive photodiode comprising the eps of(1) forming by vacuum deposition an epitaxial layer of a semiconductor alloy material selected from the group consisting of PbS, PbSe, PbTe, PbS.sub.x Se.sub.1-x, PbS.sub.x Te.sub.1-x, PbSe.sub.x Te.sub.1-x, Pb.sub.y Sn.sub.1-y S, Pb.sub.y Sn.sub.1-y Se, Pb.sub.y Sn.sub.1-y Te, Pb.sub.y Sn.sub.1-y S.sub.x, Pb.sub.y Sn.sub.1-y S.sub.x Te.sub.1-x, Pb.sub.y Sn.sub.1-y Se.sub.x Te.sub.1-x, Pb.sub.z Cd.sub.1-z S, Pb.sub.z Cd.sub.1-z Se, Pb.sub.z Cd.sub.1-z Te, Pb.sub.z Cd.sub.1-z S.sub.x Se.sub.1-x, Pb.sub.z Cd.sub.1-z S.sub.x Te.sub.1-x, and Pb.sub.z Cd.sub.1-z Se.sub.x Te.sub.
    Type: Grant
    Filed: July 27, 1988
    Date of Patent: August 1, 1989
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Tak-Kin Chu, Francisco Santiago
  • Patent number: 4824798
    Abstract: A thin film bilayer composite source comprises a deposited impurity source layer, e.g. Si or Sb, heavily doped with a diffusion enabling agent, e.g. As, and capped with a passivating layer, e.g. Si.sub.3 N.sub.4, SiO.sub.2, AlN or SiO.sub.x N.sub.y. In a preferred embodiment, a thin film bilayer composite source comprises a Si layer on the surface of said structure vapor deposited at a temperature in excess of 500.degree. C. in the presence of a source of As to hevily dope the layer in the range of 5%-20% atomic weight and a thin cap layer of Si.sub.3 N.sub.4 deposited on the Si layer at a temperature in excess of 500.degree. C. having a thickness only sufficient to prevent the outdiffusion of Ga and As, which thickness may be about 400 .ANG.-700 .ANG.. An important aspect of the employment of this bilayer composite source as a diffusion source for III-V structures is that the composite source is initially deposited at high temperatures, above 500.degree.0 C., i.e.
    Type: Grant
    Filed: November 5, 1987
    Date of Patent: April 25, 1989
    Assignee: Xerox Corporation
    Inventors: Robert D. Burnham, Robert L. Thornton
  • Patent number: 4818720
    Abstract: A semiconductor integrated circuit device is disclosed which comprises a bipolar transistor and a field effect transistor, in which a gate electrode of the field effect transistor and a collector electrode of the bipolar transistor are formed from a common electrode layer of a high impurity concentration, and in which the collector region of the bipolar transistor comprises a region of a high impurity concentration having a conductivity type the same as that of the collector region of the bipolar transistor.
    Type: Grant
    Filed: September 8, 1987
    Date of Patent: April 4, 1989
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroshi Iwasaki
  • Patent number: 4746377
    Abstract: In a surface region of a silicon semiconductor substrate (10), an arsenic diffusion layer (20) having a surface arsenic concentration of 5.times.10.sup.18 cm.sup.-3 to 5.times.10.sup.19 cm.sup.-3 is formed and then, the arsenic diffusion layer (20) is oxidized by a thermal oxidation method so that a thermally oxidized film (30) is formed on the arsenic diffusion layer (20). Thus, an insulating film (30) having an excellent insulating characteristic can be obtained, and therefore a MOS type semiconductor device with an excellent insulating characteristic can be obtained.
    Type: Grant
    Filed: January 28, 1986
    Date of Patent: May 24, 1988
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Kiyoteru Kobayashi, Hideaki Arima
  • Patent number: 4717588
    Abstract: A method for diffusing a metal dopant into a semiconductor switching device is provided by the use of a rapid thermal heating apparatus. This method provides a procedure for the selectively placing of a metal dopant in a region of the device or circuit. This aids in increasing the manufacturing yields of the switching device, and increases the number of active traps for minority carriers.
    Type: Grant
    Filed: December 23, 1985
    Date of Patent: January 5, 1988
    Assignee: Motorola Inc.
    Inventors: Syd R. Wilson, Wayne M. Paulson, Charles J. Varker
  • Patent number: 4644383
    Abstract: A vertical bipolar transistor having a subcollector region of two different thicknesses is provided to increase packing density. The thicker portion lies beneath the area between the emitter and the collector contact. A single additional masking step is needed to provide the dual thickness subcollector region.
    Type: Grant
    Filed: April 8, 1985
    Date of Patent: February 17, 1987
    Assignee: Harris Corporation
    Inventor: Osman E. Akcasu
  • Patent number: 4571275
    Abstract: The method suggests the replacement of all or part of the solid or blanket buried region, typically a subcollector region of a bipolar transistor, by a mesh or stripe shaped subcollector. During subsequent thermal processing involving growth of the epitaxial layer, the stripes will at least partially merge, resulting in a solid subcollector. The method of minimizing autodoping implies only a special design of the subcollector mask. Therefore, there is no longer any need for technological changes either in the process or in the equipment. The method also applies to other buried layers, such as, subemitters, resistors, bottom isolation regions, etc.
    Type: Grant
    Filed: December 19, 1983
    Date of Patent: February 18, 1986
    Assignee: International Business Machines Corporation
    Inventor: Tor W. Moksvold
  • Patent number: 4532700
    Abstract: A method is provided for manufacturing semiconductor structures having dielectrically isolated silicon regions on one side of a silicon body. This is accomplished by forming in the silicon body a set of buried regions and a set of surface regions having characteristics which make them anodically etch slower than the remaining portion of the silicon body. These two sets of regions define portions in the silicon body which are anodically etched to form porous silicon regions which are oxidized to form an isolation structure that isolates the silicon surface regions from each other and the remaining portion of the silicon body. Typically in a P-type silicon body the buried and surface regions are N-type regions formed through ion implantation.
    Type: Grant
    Filed: April 27, 1984
    Date of Patent: August 6, 1985
    Assignee: International Business Machines Corporation
    Inventors: Wayne I. Kinney, Jerome B. Lasky, Larry A. Nesbit
  • Patent number: 4528745
    Abstract: A method for the formation of buried gates in a semiconductor device using epitaxial growing method combined with diffusion method or diffusion by an additional heat treatment. The buried gate has smaller gate resistance by providing relatively high impurity concentration and also having good reverse characteristic by providing relatively low impurity concentration at the top of the buried gates.
    Type: Grant
    Filed: July 6, 1983
    Date of Patent: July 16, 1985
    Assignee: Toyo Denki Seizo Kabushiki Kaisha
    Inventor: Kimihiro Muraoka