Annealing, Incoherent Light Patents (Class 148/DIG4)
  • Patent number: 5773329
    Abstract: A method of low temperature and rapid silicon crystallization or rapid transformation of amorphous silicon to high quality polysilicon over a large area is disclosed using a pulsed rapid thermal annealing (PRTA) method and a metal seed layer. The PRTA method forms polysilicon thin film transistors (TFTs) with a high throughput, on low temperature and large area glass substrates. The PRTA method includes the steps of forming over a glass layer a tri-layer structure having a layer of amorphous silicon sandwiched between bottom and top dielectric layers; selectively etching the top dielectric layer to expose portions of the amorphous silicon layer; forming a metal seed layer over the exposed portions of the amorphous silicon layer; and pulsed rapid thermal annealing using successive pulses separated by rest periods to transform the amorphous silicon layer to a polysilicon layer. In an alternate PRTA method, instead of forming the tri-layer structure, a bi-layer structure is formded over the glass layer.
    Type: Grant
    Filed: July 24, 1996
    Date of Patent: June 30, 1998
    Assignee: International Business Machines Corporation
    Inventor: Yue Kuo
  • Patent number: 5750443
    Abstract: Disclosed is a method of manufacturing a semiconductor device wherein a corpuscular beam is radiated to a semiconductor substrate to create crystal defects therein. The semiconductor substrate is subjected to a heat treatment, e.g. for 1 second to 60 minutes, wherein rapid heating-up, e.g. raising temperature to 550.degree. to 850.degree. C. within 10 minutes, is done in a process prior to that of carrying out of the radiation with a corpuscular beam. By doing so, there is provided a semiconductor device which is free from degradation in electrical characteristics such as current amplification factor and has an increased switching speed, even where crystal defects are created through the radiation of corpuscular beam such as an electron beam to shorten the carrier lifetime. Thus, the inventive semiconductor device is satisfied by both requirements of switching speed and electrical characteristic.
    Type: Grant
    Filed: March 3, 1997
    Date of Patent: May 12, 1998
    Assignee: Rohm Co., Ltd.
    Inventor: Kazuhisa Sakamoto
  • Patent number: 5529937
    Abstract: After a pattern is transferred on silicon film crystallized by annealing, the silicon film is annealed by radiation of intense rays for a short time. Especially, in the crystallizing process by annealing, an element which promotes crystallization such as nickel is doped therein. The area not crystallized by annealing is also crystallized by radiation of intense rays and a condensed silicon film is formed. After a metal element which promotes crystallization is doped, annealing by light for a short time is performed by radiating intense rays onto the silicon film crystallized by annealing in an atmosphere containing halide. After the surface of the silicon film is oxidized by heating or by radiating intense rays in a halogenated atmosphere and an oxide film is formed on the silicon film, the oxide film is then etched. As a result, nickel in the silicon film is removed.
    Type: Grant
    Filed: July 20, 1994
    Date of Patent: June 25, 1996
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hongyong Zhang, Hideto Ohnuma, Yasuhiko Takemura
  • Patent number: 5387546
    Abstract: The present invention relates to a method for manufacturing a semiconductor device including a method for reforming an insulating film formed by a low temperature CVD method. It is an object of the present Invention to provide a method for manufacturing a semiconductor device capable of improving a film quality of an insulating film formed by a CVD method which is able to form a film at a low temperature and also capable of maintaining mass productivity, in which processing by irradiation with ultraviolet rays of the insulating film while heating the film after forming an insulating film (4) on a body to be formed by a chemical vapor deposition method is included.
    Type: Grant
    Filed: June 22, 1992
    Date of Patent: February 7, 1995
    Assignees: Canon Sales Co., Inc., Alcan-Tech Co., Ltd., Semiconductor Process Laboratory Co., Ltd.
    Inventors: Kazuo Maeda, Noboru Tokumasu, Yuko Nishimoto
  • Patent number: 5312771
    Abstract: An optical annealing method for a semiconductor layer provided on a substrate comprises irradiating a base member provided with a semiconductor layer and an absorbing layer for incoherent light across an insulating layer, with incoherent light followed by patterning the absorbing layer to form a gate electrode.
    Type: Grant
    Filed: April 6, 1993
    Date of Patent: May 17, 1994
    Assignee: Canon Kabushiki Kaisha
    Inventor: Takao Yonehara
  • Patent number: 5306662
    Abstract: A method for manufacturing a III-V Group compound or a II-VI Group compound semiconductor element by VPE, comprising the step of annealing a grown compound at 400.degree. C. or higher, or irradiating electron beam the grown compound at 600.degree. C. or higher.
    Type: Grant
    Filed: November 2, 1992
    Date of Patent: April 26, 1994
    Assignee: Nichia Chemical Industries, Ltd.
    Inventors: Shuji Nakamura, Naruhito Iwasa, Masayuki Senoh
  • Patent number: 5296405
    Abstract: An improved semiconductor processing is disclosed. In the manufacturing process, a semiconductor layer is formed and then undergoes photo annealing. A neutralizer is then introduced to the photoannealed semiconductor. The semiconductor thus formed demonstrates the SEL effect instead of the Staebler-Wronski effect.
    Type: Grant
    Filed: August 24, 1992
    Date of Patent: March 22, 1994
    Assignee: Semiconductor Energy Laboratory Co.., Ltd.
    Inventors: Shunpei Yamazaki, Kunio Suzuki, Susumu Nagayama, Takashi Inujima, Masayoshi Abe, Takeshi Fukada, Mikio Kinka, Ippei Kobayashi, Katsuhiko Shibata, Masato Susukida, Kaoru Koyanagi
  • Patent number: 5212101
    Abstract: The invention provides a method of producing silicon with about 100% substitutionality of very high concentrations of carbon up to about 10.sup.21 cm.sup.-3, which has good quality recrystallized layers containing low levels of residual damage, and which avoids precipitation of mobile carbon. This method, compatible with current state-of-the-art VLSI silicon technology, comprises the sequential steps of: implanting a silicon wafer with carbon ions, and two step annealing of the implanted silicon wafer.
    Type: Grant
    Filed: November 6, 1991
    Date of Patent: May 18, 1993
    Assignee: Secretary of State for Defence in her Britannic Majesty's Government of the United Kingdom
    Inventors: Leigh T. Canham, Keith G. Barraclough, Mark R. Dyball
  • Patent number: 5171710
    Abstract: An improved semiconductor processing is disclosed. In the manufacturing process, a semiconductor layer is formed and then undergoes photo annealing. A neutralizer is then introduced to the photoannealed semiconductor. The semiconductor thus formed demonstrates the SEL effect instead of the Staebler-Wronski effect.
    Type: Grant
    Filed: May 9, 1990
    Date of Patent: December 15, 1992
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kunio Suzuki, Susumu Nagayama, Takashi Inujima, Masayoshi Abe, Takeshi Fukada, Mikio Kinka, Ippei Kobayashi, Katsuhiko Shibata, Masato Susukida, Kaoru Koyanagi
  • Patent number: 5169796
    Abstract: A method of fabricating a metal-gate field effect transistor having source and drain regions which are self-aligned with the gate. The source and drain dopants are introduced into the substrate and driven. Then, a metal gate is formed, the metal gate having a length which is approximately the same as the length of the channel. After the gate is fabricated, dopant ions are implanted into any portions of the channel not covered by the gate. These dopant ions are activated by rapid thermal annealing at a temperature selected to avoid damage to the metal gate, to form bridge regions which extend one or both of the source/drain regions into the channel and which are self-aligned with the gate.
    Type: Grant
    Filed: September 19, 1991
    Date of Patent: December 8, 1992
    Assignee: Teledyne Industries, Inc.
    Inventors: Roger Murray, Nevand Godhwani
  • Patent number: 5024962
    Abstract: A method of fabricating metal gate field effect transistors utilizing a rapid thermal oxidation process to form a sealing oxide which prevents auto-doping during the formation of the gate oxide.
    Type: Grant
    Filed: April 20, 1990
    Date of Patent: June 18, 1991
    Assignee: Teledyne Industries, Inc.
    Inventors: Roger W. Murray, Nevand Godhwani
  • Patent number: 5024955
    Abstract: A variable-capacitance diode element is disclosed which comprises a semiconductor substrate of a first conductivity type having an epitaxial layer of the first conductivity type provided on a main surface portion thereof, said epitaxial layer having a higher resistivity than that of said semiconductor substrate; a first diffusion layer of the first conductivity type diffused in said epitaxial layer and having a lower resistivity than that of said epitaxial layer; a second diffusion layer of a second conductivity type surrounded by said first diffusion layer and having a lower resistivity than that of said first diffusion layer; and a third diffusion layer of the second conductivity type of a small diffusion length covering an exposed portion of a major surface of said first diffusion layer and an exposed portion of a major surface of said second diffusion layer. With such construction, the capacitance variation range of the diode element is widened, and the high-frequency serial resistance R.sub.
    Type: Grant
    Filed: June 13, 1990
    Date of Patent: June 18, 1991
    Assignee: Toko, Inc.
    Inventor: Takeshi Kasahara
  • Patent number: 4981815
    Abstract: A method for rapidly thermal processing a semiconductor wafer (1) by irradiation with electromagnetic radiation which provides that the majority portion of the energy required for heating the semiconductor wafer (1) is transmitted with at least single-sided irradiation of the semiconductor wafter (1) with electromagnetic radiation from a main irradiation arrangement (62) and the intensities (I.sub.M, I.sub.R) of the radiation directed onto the central region (6) and of the radiation directed onto the edge regions (5) are identical. The temperatures in the central region (6) and in the edge regions (5) of the semiconductor wafer (1) are maintained identical during the entire tempering process in order to increase the yield, and an additional electromagnetic radiation is directed onto the edge region (5) of the semiconductor wafer for compensating for the radiation of heat occurring faster at the edge region (5) of the semiconductor wafer (1).
    Type: Grant
    Filed: March 13, 1989
    Date of Patent: January 1, 1991
    Assignee: Siemens Aktiengesellschaft
    Inventor: Ronald Kakoschke
  • Patent number: 4971919
    Abstract: The present invention relates to a semiconductor photoelectric conversion device which has a laminate member composed of a plurality of PIN structures formed one on the other. The manufacturing method includes a laminate member forming step and an electrode forming step. In the laminate member forming step, the first and second PIN structures and the transparent conductive layers are formed. In the electorde forming step a metal layer is annealed to form a metal silicide layer and the remaining metal layer is removed.
    Type: Grant
    Filed: March 9, 1989
    Date of Patent: November 20, 1990
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 4963503
    Abstract: A liquid crystal display device comprises, a plurality of display electrodes which are selectively energized through on-off control of thin film transistors. In order to reduce the channel length of the thin film transistors to increase operation speed and obtain uniform characteristics each display electrode and an associated transistor source electrode is formed on one of a pair of transparent substrates of the liquid crystal display device, a semiconductor layer is formed between the display electrode and source electrode, a gate insulating film is formed on the semiconductor layer, and a gate electrode is formed on a portion of the gate insulating film between the display electrode and source electrode. Then, ions are implanted into the semiconductor layer with the gate electrode used as a mask, thus rendering portions of the semiconductor layer contiguous to the display electrode and source electrode into ohmic layers.
    Type: Grant
    Filed: March 29, 1989
    Date of Patent: October 16, 1990
    Assignee: Hosiden Electronics Co., Ltd.
    Inventors: Shigeo Aoki, Yasuhiro Ugai, Katsumi Miyake, Kotaro Okamoto
  • Patent number: 4950614
    Abstract: A method of making a tandem type semiconductor photoelectric conversion device, comprising steps of: forming laminate member on a substrate by laminating first and second PIN structure of non-single crystal semiconductor in that order (or in the reverse order); forming an electrode on the laminate member; and crystallization an I-type layer of the second PIN structure by light irradiation (a) through the electrode (in this case, the electrode is transparent), or (b) from the side opposite from the substrate before formation of the electrode (or (a) from the side opposite from the substrate before formation of the first PIN structure, or (b) through the substrate (in this case, the substrate is transparent)).
    Type: Grant
    Filed: January 30, 1989
    Date of Patent: August 21, 1990
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 4888305
    Abstract: An improved semiconductor processing is disclosed. In the manufacturing process, just formed semiconductor layer undergoes photo annealing and latent dangling bonds are let appear on the surface and gaps, then neutralizer is introduced to the ambience of the semiconductor. The semiconductor thus formed demonstrates SEL effect in place of Staebler-Wronski effect.
    Type: Grant
    Filed: March 9, 1989
    Date of Patent: December 19, 1989
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kunio Suzuki, Susumu Nagayama, Takashi Inujima, Masayoshi Abe, Takeshi Fukada, Mikio Kinka, Ippei Kobayashi, Katsuhiko Shibata, Masato Susukida, Kaoru Koyanagi
  • Patent number: 4888302
    Abstract: A defect free monocrystalline layer of silicon on an insulator is produced by forming a thin layer of silicon dioxide on a monocrystalline silicon substrate, forming a thin layer of polycrystalline or amorphous silicon on the silicon dioxide layer and focussing two beams from lamps on the thin silicon layer to form a line image providing a melt zone surrounded by two narrow heated zones having temperatures lower than the melt zone and having a temperature differential of from 2.degree.-10.degree. C./mm decreasing form the melt zone while heating the substrate to a temperature below that of the zones heated by the lamps and scanning the structure.
    Type: Grant
    Filed: March 29, 1989
    Date of Patent: December 19, 1989
    Assignee: North American Philips Corporation
    Inventor: Subramanian Ramesh
  • Patent number: 4879259
    Abstract: A method of annealing a wafer in a rapid thermal annealer is disclosed. The walls of the chamber are heated more rapidly than is the wafer. In a preferred embodiment, the interior of the graphite walls of the annealer is lined with a molybdenum sheet which is open toward the lamps that heat the chamber. Thus, the walls heat very rapidly to a temperature greater than the condensation point of arsenic, preventing arsenic condensation on the walls. Effective annealing can be achieved at wall temperatures in the range of 500.degree. to 600.degree. C. Prior to the heat ramp up, an arsenic atmosphere, preferably trimethylarsenic (TMAs) at an appropriate overpressure is introduced. This overpressure is maintained both during the heating and cooling cycle. By the use of this method, the exposure time for annealing can be reduced from prior times of as much as 20 minutes to as little as 10 seconds.
    Type: Grant
    Filed: February 1, 1989
    Date of Patent: November 7, 1989
    Assignee: The Board of Trustees of the Leland Stanford Junion University
    Inventors: Scott K. Reynolds, Dietrich W. Vook, James F. Gibbons
  • Patent number: 4851358
    Abstract: The concentration of internal gettering sites within a semiconductor wafer is controlled by two-step thermal processing. In a concentration reduction phase, the wafer is rapidly heated to an elevated temperature in the range from about 900.degree. to 1350.degree. C., resulting in the partial or total dissolution of precipitable impurities within the wafer. In a concentration enhancement step, the wafers are subjected to a relatively low temperature anneal process where the density of potential internal gettering sites is increased. By properly controlling the processing temperatures and treatment times, the two steps may be performed in either order to obtain wafers having internal gettering site concentrations within a desired range.
    Type: Grant
    Filed: February 11, 1988
    Date of Patent: July 25, 1989
    Assignee: DNS Electronic Materials, Inc.
    Inventor: Walter Huber
  • Patent number: 4845055
    Abstract: For preventing a semiconductor substrate from a heat attack, a method of rapid annealing using a lamp unit for a heat radiation comprises the step of preparing a semiconductor substrate having a multiple-layer structure and a vessel having an annealing chamber where the lamp unit is placed, the vessel is associated with an inert gas supplying system operative to supply a high-pressure inert gas to the annealing chamber, and the above step is followed by the steps of placing the semiconductor substrate in the annealing chamber, supplying the high-pressure inert gas to the annealing chamber so as to create a high-pressure inert ambient within a predetermined range and activating the lamp unit for the heat radiation so as to heat up the semiconductor substrate, so that the heat radiation is decreased in intensity by virtue of the high-pressure inert ambient.
    Type: Grant
    Filed: May 7, 1988
    Date of Patent: July 4, 1989
    Assignee: Yamaha Corporation
    Inventor: Takashi Ogata
  • Patent number: 4784975
    Abstract: The insulating and stabiity characteristics of silicon dioxide gate oxide insulator for field effect transistors are enhanced by subjecting the silicon dioxide to an annealing in an ambient that contains a gaseous oxygen-containing species in an amount sufficient to provide a partial pressure from the oxygen-containing material of about 10.sup.-6 torr to about 10 torr during annealing temperatures of about 500.degree. C. to about 1200.degree. C. Such is carried out for a time sufficient to enhance the insulating and stability characteristics of the silicon dioxide insulator.
    Type: Grant
    Filed: October 23, 1986
    Date of Patent: November 15, 1988
    Assignee: International Business Machines Corporation
    Inventors: Karl Hofmann, Gary W. Rubloff, Donald R. Young
  • Patent number: 4752592
    Abstract: An annealing method for a GaAs wafer which uses incoherent light, e.g., infrared light generated from tungsten lamp, halogen lamp, etc. and a GaAs guard ring which surrounds the GaAs wafer. The thickness of the guard ring is 1.5 times more than that of the GaAs wafer, the internal diameter of the guard ring is less than diameter of GaAs wafer plus 3 mm and the width of the guard ring is less than 10 mm.
    Type: Grant
    Filed: November 28, 1986
    Date of Patent: June 21, 1988
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Akiyoshi Tamura, Takeshi Onuma
  • Patent number: 4751193
    Abstract: Method is provided for manufacturing large crystalline and monocrystalline semiconductor-on-insulator devices.
    Type: Grant
    Filed: October 9, 1986
    Date of Patent: June 14, 1988
    Assignee: Q-Dot, Inc.
    Inventor: James J. Myrick
  • Patent number: 4743569
    Abstract: A two step rapid thermal anneal (RTA) has been studied for activating Be implanted GaAs, where a short duration high temperature step is used to electrically activate the Be followed by a longer low temperature anneal for lattice re-growth. PN diodes show a substantial reduction in reverse diode leakage current after the lower temperature second step anneal, when compared to a single step RTA or to furnace annealing (FA). For low energy Be implants, no difference in electrical activation between the single step and the two step anneal is observed. Raman studies demonstrate that residual substrate impurities and high Be concentrations inhibit restoration of single crystal lattice characteristics after RTA. Lattice quality is also shown not to limit diode characteristics in the RTA material.
    Type: Grant
    Filed: April 20, 1987
    Date of Patent: May 10, 1988
    Assignee: Texas Instruments Incorporated
    Inventors: Donald L. Plumton, Liem T. Tran, Walter M. Duncan
  • Patent number: 4729962
    Abstract: The process of the invention includes applying precursors 6 with N- and P-type dopants therein to a silicon web 2, with the web 2 then being baked in an oven 10 to drive off excessive solvents, and the web 2 is then heated using a pulsed high intensity light in a mechanism 12 at 1100.degree.-1150.degree. C. for about 10 seconds to simultaneously form semiconductor junctions in both faces of the web.
    Type: Grant
    Filed: March 24, 1986
    Date of Patent: March 8, 1988
    Assignee: The United States of America as represented by the United States Department of Energy
    Inventor: Robert B. Campbell
  • Patent number: 4585492
    Abstract: Silicon dioxide insulating films for integrated circuits are provided with enhanced electronic properties, including enhanced dielectric breakdown of MOS insulating layers and reduced trapping of holes by exposing a metal oxide semiconductor wafer including an exposed silicon dioxide layer, in an ambient of flowing oxygen gas, to heating radiation from a halogen lamp for a duration on the order of 100 seconds to achieve annealing temperature on the order of 1000.degree. C.For reduced hole trapping, the ambient gas is oxygen and the annealing temperature is on the order of 1000.degree. C. for a duration on the order of 100 seconds, depending on the oxide thickness.Nitrogen, occurring at the silicon-silicon dioxide interface as a result of previous processing including a long anneal in nitrogen, increases the improvement of the silicon dioxide by the subsequent rapid thermal annealing in oxygen.
    Type: Grant
    Filed: July 30, 1984
    Date of Patent: April 29, 1986
    Assignee: International Business Machines Corporation
    Inventors: Zeev A. Weinberg, Donald R. Young
  • Patent number: 4576652
    Abstract: Ion implanted gallium arsenide substrates are annealed by providing an arsenic-containing gaseous ambient on all sides of the substrate, and heating the gallium arsenide substrate with broad area incoherent light.
    Type: Grant
    Filed: July 12, 1984
    Date of Patent: March 18, 1986
    Assignee: International Business Machines Corporation
    Inventors: Harold J. Hovel, Thomas F. Kuech
  • Patent number: 4566913
    Abstract: Silicon dioxide insulating films for integrated circuits are provided with enhanced electronic properties, including decreased water content and reduced trapping of electrons, by exposing a metal oxide semiconductor wafer including an exposed silicon dioxide layer, in an ambient of flowing inert gas, to heating radiation from a halogen lamp for a duration on the order of ten seconds to achieve annealing temperature in the range 600C.-800C.
    Type: Grant
    Filed: July 30, 1984
    Date of Patent: January 28, 1986
    Assignee: International Business Machines Corporation
    Inventors: Marc H. Brodsky, Zeev A. Weinberg
  • Patent number: 4561907
    Abstract: A method for forming highly doped, low sheet resistance, anisotropically etched polysilicon using heat pulse annealing and plasma etching. The combination of low sheet resistance and anisotropic etch behavior is provided by heat pulse annealing for a time which corresponds to a characteristic transition region of the sheet resistance-annealing time curve.
    Type: Grant
    Filed: July 12, 1984
    Date of Patent: December 31, 1985
    Inventor: Bruha Raicu