Abstract: The preferred embodiment of the present invention overcomes the limitations of the prior art and provides a device and method to increase the latch-up immunity of CMOS devices by reducing the mobility of carriers between the devices. The preferred embodiment uses an implant formed beneath trench isolation between n-channel and p-channel devices. This implant preferably comprises relatively large/heavy elements implanted into the wafer beneath the trench isolation. The implant elements reduce the mobility of the charge carriers. This increases the latch-up holding voltage and thus reduces the likelihood of latch-up. The implants can be formed without the need for additional photolithography masks.

Abstract: The number of surface defects in semiconductor materials having a volatile species, particulary group-III nitride-based semiconductor devices, are reduced by first implanting species atoms into the semiconductor sample to fill some of the surface layer species vacancies created by growth and device fabrication processes, and then rapid thermal annealing the sample to repair broken bonds and crystalline defects and to move implanted species atoms from interstitial to substitutional sites. An optional third step deposits a dummy layer on the sample surface prior to implantation, making possible an implantation profile that places a higher density of species atoms in the surface layer than is attainable without the dummy layer and to inhibit species atoms from leaving the sample during high-temperature processing steps that follow.

Abstract: A neutron radiation detector is described. A semiconductor material is populated with helium three (.sup.3 He) atoms to increase its overall neutron capture efficiency. Upon capture of a neutron by a .sup.3 He atom, a tritium ion and a proton are generated with energies of 0.191 and 0.573 MeV, respectively. These energies are deposited in the semiconductor material creating electron-hole pairs. The electron-hole pairs are withdrawn from the material by the application of an electric field and are collected as charges at the terminals. The associated circuitry processes the charges into pulses with these being counted and their sizes measured. The results are recorded and displayed. The number of pulses are a measure of the number of neutrons absorbed in the detector and of the neutron flux of interest. In many instances the detector can also be used to detect and display non-neutron type radiation or simultaneously neutron and non-neutron forms of radiative activity.

Abstract: SOI (silicon-on-insulator) technology has been touted as a promising approach for fabricating advanced integrated circuits because of its advantage over bulk silicon circuits such as faster speed and improved radiation tolerance. One drawback to SOI is that parasitic bipolar induced latch-up/breakdown voltage levels severely limits the maximum supply voltage at which SOI circuits and devices can operate. When the parasitic device turns on, the SOI transistor cannot be switched off by changing the gate bias. What is described is a method whereby the operating voltage in which this effect occurs is significantly increased thus allowing circuit operation at reasonable power supply voltages. The method is to implant an electrically neutral in silicon impurity atom such as krypton, xenon or germanium into the device to form ion scattering centers. The size of the impurity atom must be much larger than the size of the silicon atom. The size difference generating a scattering center.

Abstract: The phase transformation temperature of a metal silicide layer formed overlying a silicon layer on a semiconductor wafer is lowered. First, a refractory metal is disposed proximate to the surface of the silicon layer, a precursory metal is deposited in a layer overlying the refractory metal, and the wafer is heated to a temperature sufficient to form the metal silicide from the precursory metal. The precursory metal may be a refractory metal, and is preferably titanium, tungsten, or cobalt. The concentration of the refractory metal at the surface of the silicon layer is preferably less than about 10.sup.17 atoms/cm.sup.3. The refractory metal may be Mo, Co, W, Ta, Nb, Ru, or Cr, and more preferably is Mo or Co. The heating step used to form the silicide is performed at a temperature less than about 700.degree. C., and more preferably between about 600.degree.-700.degree. C.

Abstract: This is a method of forming a vertical transistor device comprising: forming an n-type first drain/source layer 42; patterning a portion of the first drain/source layer 42 to form a channel 44 and a trench; forming a p-type gate structure 46 in the trench; and forming a n-type second drain/source layer 48 over the gate structure 46 and the channel 44; contacting the gate structure 54; forming p-ohmic contact to the gate structure 56; forming n-ohmic source contact 54; and forming n-ohmic drain contact 58. Other devices and methods are also disclosed.

Abstract: GaAs films compensated with TEOV to reduce free electron concentration are grown having superior morphology by heating the TEOV above the temperature used in the prior art, filtering the other constituents but not the TEOV, and reducing the arsenic ambient during the preliminary heating phase.

Abstract: This is a method of forming a vertical transistor device. The method comprises: forming a n-type source layer 12; forming a p+ carbon doped gate layer 14; forming a gate structure from the gate layer; and forming a n-type drain layer 16 over the gate structure to provide a buried carbon doped gate structure. The buried carbon doped gate structure provides a very small device with favorable on-resistance, junction capacitance, gate resistance, and gate driving voltage. Other devices and methods are also disclosed.

Abstract: A method is disclosed for the incorporation of relatively high vapor pressure elements into good quality GaAs at extremely low T.sub.s using the migration enhanced epitaxy techinque. Zinc was doped in GaAs material grown at a low T.sub.s of 120.degree. C. Zinc may thus be used as a p-type dopant replacing more toxic Be. Similarly, other high vapor pressure elements can be incorporated much more efficiently into the material grown at low T.sub.s.

Abstract: The disclosure relates to a method of forming in situ phosphorous doped polysilicon wherein a surface upon which phosphorous doped polysilicon is to be deposited is placed in a vacuum furnace and, after low pressure HCl cleaning of the surface and furnace, a predetermined ratio of silane and a gaseous phosphorous containing compound taken from the class consisting of phosphorous trichloride, tertiary butyl phosphine, isobutyl phosphine, trimethyl phosphate and tetramethyl phosphate are simultaneously passed through the furnace at predetermined pressure and temperature to provide a uniformly phosphorous doped layer of polysilicon on the surface.

Abstract: A blue light emitting diode which has a multiple layer structure and is grown on a semiconductor crystalline substrate, wherein zinc of a group II element of the periodic table, lithium, sodium, or potassium of group VI elements are used. These elements and their compounds are used as impurities to be introduced into the construction when it is at the condition of vapor growing. A blue light emitting diode has a pair of Ohmic electrodes, an n-type semiconductor layer and a p-type semiconductor layer. These layers are grown from a vapor phase on the substrate and sandwiched between the electrodes.

Abstract: A process is described for growing at least one layer doped with a transition element of cobalt on a substrate by introducing a source of indium, such as tri ethyl indium, (C.sub.2 H.sub.5).sub.3 In or, a source of a group V element, a source of the transition element, such as cobalt nitrosyl tricarbonyl CO(NO)(CO).sub.3, and a source of phosphorus, to the substrate heated in an inert or reducing atmosphere at a pressure substantially between 1/100 atmosphere and one atmosphere to grow at least one semi-insulating semiconductor layer on the substrate.

Abstract: A method of growing zinc chalcogenide in an atmosphere which contains the vapor of di-.pi.-cyclopentadienyl manganese or di-.pi.-alkyl cyclopentadienyl manganese that serves as a source of manganese. By growing zinc chalcogenide in the above atmosphere, there is obtained a manganese-doped zinc chalcogenide having a very high crystal quality, which is very suitable for the active layer in light emitting devices.

Abstract: An improved method of fabricating a defect-free semiconductor layer and a semiconductor on insulator structure is provided by forming an isoelectronically doped semiconductor layer between a substrate and an semiconductor layer. The isoelectronic dopant atoms are different in atomic size than the atoms of the semiconductor material, thus misfit dislocations are created at the interface of the isoelectronically doped semiconductor layer due to lattice mismatch. Impurities and defects are not only gettered to the misfit dislocation sites, but are also prevented from propagating to the epitaxial layer. These misfit dislocations are thermally stable and are confined in a plane parallel to the interfaces of the isoelectronically doped semiconductor layer, thus very effective gettering agents. If the isoelectroncially doped semiconductor layer us also a heavily doped buried layer, no misfit dislocations are desired because the buried layer is an active device layer.

Abstract: A low dislocation density semiconductor device includes a first semiconductor layer of a III-V or II-VI semiconductor compound and alloying atoms on a non-metal substrate. The semiconductor compound usually has a large dislocation density. A predetermined position of the alloying atoms in the compound lattice structure can substantially reduce the compound dislocation density. Energy is applied to the alloying atoms so they are at the predetermined positions. The number of alloying atoms causes the semiconductor compound solubility limit to be exceeded. The layer is formed on a substrate of the III-V or II-VI semiconductor, such as gallium arsenide or another semiconductor, such as silicon or on an insulator such as sapphire. In the latter cases, the layer is formed on an intermediate layer having a lattice constant between that of the substrate and semiconductor compound.

Abstract: Zinc is diffused into indium phosphide in the presence of cadmium to prevent degradation of the indium phosphide surface.

Abstract: The disclosure relates to a method of forming in situ phosphorous doped polysilicon wherein a surface upon which phosphorous doped polysilicon is to be deposited is placed in a vacuum furnace and, after low pressure HCl cleaning of the surface and furnace, a predetermined ratio of silane and a gaseous phosphorous containing compound taken from the class consisting of phosphorous trichloride, tertiary butyl phosphine, isobutyl phosphine, trimethyl phosphate and tetramethyl phosphate are simultaneously passed through the furnace at predetermined pressure and temperature to provide a uniformly phosphorous doped layer of polysilicon on the surface.

Abstract: A method of producing n-type III-V compound semiconductor comprises growing a plurality of monolayers of III-V compound semiconductor molecules on a III-V compound substrate; growing a single layer of group VI element on the III-V monolayers so as to occupy the lattice points for group V element by means of Atomic Layer Epitaxy process; decreasing the number of group VI element by exposing the single layer to the gas of group V element; and growing a plurality of monolayers of III-V compound semiconductor molecules on the group VI element-doped layer by means of the Atomic Layer Epitaxy process.

Abstract: An n-type III-V compound semiconductor comprises a plurality of monolayers of III-V compound semiconductor molecules having a layer-by-layer structure of group III element and group V element laminated alternately, and a group VI element-doped monolayer. The group VI element-doped monolayer is inserted into the III-V compound semiconductor molecules by occupying lattice points which were occupied by the group V element. The layers of the semiconductor are grown by Atomic Layer Epitaxy process.

Abstract: In a method for producing a spatially periodic semiconductor layer structure in the form of a superlattice composed of an alternating arrangement of strained semicondutor layers of at least two different semiconductor compositions forming at least one heterojunction, at least one of the semiconductor layers is provided with a doped layer which extends essentially parallel to the heterojunction and whose layer thickness is no greater than the thickness of the semiconductor layer in which it is produced.

Abstract: Semi-insulating epitaxial layers of Group III-V based semiconductor compounds are produced by a MOCVD process through the use of organic titanium-based compounds. Resistivities greater than 1.times.10.sup.7 ohm/cm have been achieved.

Abstract: A semiconductor quantized layered structure comprising first and second different semiconductor materials comprising compound semiconductors from both the Group III and Group V elements and forming a plurality of alternate layers, each interfaced to its adjacent layer in a semiconductor homojunction or heterojunction. The bottom of the conduction bands of the first and second materials are at different energy levels and the tops of the valence bands of the first and second materials are at different energy levels. The bottoms of the conduction bands of the first and second materials form a plurality of serially arranged potential wells and barriers due to differences in the band structures of the different materials forming alternate layers and the interfacing of the layers forming heterojunctions so that the thinness of the layers will spatially localize electrons to obtain quantized electron states in one dimension transverse to the longitudinal extent of said layers.

Abstract: An epitaxially grown high resistivity crystalline layer of gallium arsenide is produced in a reactor vessel with a predetermined amount of carbon dioxide introduced during growth of the high resistivity gallium arsenide (GaAs) crystalline layer to provide carbon as a dopant. Thus, a plurality of carbon atoms is provided in the crystal, such carbon atoms having electrons at energy levels between a valance energy band and a conduction energy band of the GaAs crystal. With these energy levels, the carbon atoms are substantially ionized at room temperature by accepting a plurality of electrons from the valance band of the GaAs. The presence of these carbon ions in the crystal compensates for a stoichiometric defect which occurs during epitaxial growth of the GaAs crystalline layer. This results in a high resistivity layer which provides a buffer layer between a GaAs substrate and an active GaAs layer.

Abstract: A method of improving field-effect transistors, and the product thereof, wherein the resistivity of the upper layer of the source-gate channel region of a GaAs field-effect transistor (FET) may be selectively raised is disclosed. Impurity ions are implanted in the source-gate channel region followed by a much shallower implantation of boron in the same region. The boron ion concentration should exceed the N+ impurity ion concentration by a factor of 2 or more.