Dual Dielectric Patents (Class 148/DIG43)
  • Patent number: 6150220
    Abstract: A dual thickness gate insulation layer, for use with, e.g., a dual gate MOSFET (Metal Oxide Semiconductor Field Effect Transistor), is formed using a more simplified method and improves the reliability. An impurity layer is formed in the semiconductor substrate, and the impurity layer includes a first portion and a second portion. An insulation layer is grown in the semiconductor substrate, and the insulation layer includes a first layer and a second layer which are different from each other in thickness. The present invention simplifies the insulation layer fabricating steps and improves product reliability.
    Type: Grant
    Filed: November 19, 1998
    Date of Patent: November 21, 2000
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventors: Yun-Jun Huh, Nam-Hoon Cho
  • Patent number: 6124153
    Abstract: A method for manufacturing a polysilicon thin film transistor (TFT) according to the present invention reduces the electric field near the drain junction by varying partially the thickness of a gate insulating layer through a post oxide process. A polysilicon layer is patterned to become an active layer and a chemical vapor deposition oxide film deposited. By thermal oxidation a thermal oxide film is formed under the chemical vapor deposition oxide film. A gate electrode made of polysilicon is formed on the gate insulating layer. Thermal oxidation is performed to make the end portions of the thermal oxide film thicker than the portion under the gate electrode of the thermal oxide film. With this process, the electric field near the drain junction region is reduced and thus the leakage currents of the TFT decrease. In addition, the method in this invention is very simple compared with the conventional methods of obtaining a LDD structure and on-current is not reduced.
    Type: Grant
    Filed: July 15, 1996
    Date of Patent: September 26, 2000
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joo-hyung Lee, Yong-suk Jin
  • Patent number: 5650344
    Abstract: A method of making a semiconductor device in which a polysilicon gate is separated from a semiconductor substrate by a re-oxidized nitrided oxide film and in which the concentration of re-oxidized nitride in the film underlying the gate is non-uniform. The concentration of nitrogen in the substrate and the re-oxidized nitrided oxide along their interface and underlying the gate is non-uniform. The non-uniform concentrations are provided by incomplete shielding of the oxide by the gate during the nitriding and re-oxidizing processes.
    Type: Grant
    Filed: July 17, 1995
    Date of Patent: July 22, 1997
    Assignee: Harris Corporation
    Inventors: Akira Ito, John T. Gasner
  • Patent number: 5610082
    Abstract: A method for fabricating a thin film transistor, enabling an easy fabrication and an improvement in device characteristic by use of a self-alignment.
    Type: Grant
    Filed: December 28, 1993
    Date of Patent: March 11, 1997
    Assignee: LG Electronics Inc.
    Inventor: Eui Y. Oh
  • Patent number: 5593921
    Abstract: A method is provided for forming a contact opening or via of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A first metal region is formed over an underlying region. A first insulating layer is formed over the integrated circuit. A second insulating layer is then formed over the first insulating layer. A portion of the second insulating layer is etched to expose a portion of the first insulating layer wherein the exposed first insulating layer and the remaining second insulating layer form a substantially planar surface. A metal oxide layer is formed over the exposed first insulating layer and the remaining second insulating layer. A photoresist layer is formed and patterned over the metal oxide layer. The metal oxide layer is then selectively etched to form a via exposing a portion of the first insulating layer. The first insulating layer in the via is then selectively etched to expose a portion of the first metal region.
    Type: Grant
    Filed: May 9, 1995
    Date of Patent: January 14, 1997
    Assignee: SGS-Thomson Microelectronics, Inc.
    Inventors: Fusen E. Chen, Fu-Tai Liou, Girish A. Dixit
  • Patent number: 5488015
    Abstract: This invention provides a semiconductor device and process for making the same with dramatically reduced capacitance between adjacent conductors and an interlayer dielectric construction which emphasizes mechanical strength, etch compatibility, and good heat transfer. This process can include applying a solution between conductors 24, and then gelling, surface modifying, and drying the solution to form an extremely porous dielectric layer 28. A non-porous dielectric layer 30 may be formed over porous layer 28, which may complete an interlayer dielectric and provide mechanical strength, heat transfer, and a solid layer for via etch. A novel process for creating the porous dielectric layer is disclosed, which can be completed at vacuum or ambient pressures, yet results in porosity, pore size, and shrinkage of the dielectric during drying comparable to that previously attainable only by drying gels at supercritical pressure.
    Type: Grant
    Filed: May 20, 1994
    Date of Patent: January 30, 1996
    Assignee: Texas Instruments Incorporated
    Inventors: Robert H. Havemann, Shin-Puu Jeng, Bruce E. Gnade, Chih-Chen Cho
  • Patent number: 5474956
    Abstract: A method of patterning a metallized substrate using a thin partially cured etch block layer. In accordance with the method, a substrate is provided and a layer of metal, such as aluminum, is deposited on the substrate. A thin layer of organic dielectric material, such as polyimide, is deposited over the layer of metal. The thin layer of organic dielectric material is deposited to a thickness on the order one micron, for example, which is thin enough to have etch resistance when acting as an etch block layer for subsequent wet etch patterning of the layer of metal, and thick enough to have no pinhole defects. The deposited thin organic dielectric layer is then partially cured. The underlying layer of metal is then patterned and wet etched using the partially cured thin organic dielectric material as the blocking layer. An additional thick layer of organic dielectric material is then deposited or coated over the patterned layer of metal and partially cured organic dielectric layer.
    Type: Grant
    Filed: March 14, 1995
    Date of Patent: December 12, 1995
    Assignee: Hughes Aircraft Company
    Inventors: Philip A. Trask, Vincent A. Pillai
  • Patent number: 5464783
    Abstract: A method for making gate dielectrics for MOS devices includes first forming a silicon oxynitride layer, and then forming a silicon dioxide layer that underlies the oxynitride layer. The oxynitride layer functions as a membrane for controlled diffusion of oxygen to the oxidation region of the silicon substrate.
    Type: Grant
    Filed: February 2, 1995
    Date of Patent: November 7, 1995
    Assignee: AT&T Corp.
    Inventors: Young O. Kim, Lalita Manchanda, Gary R. Weber
  • Patent number: 5397725
    Abstract: A method of fabricating an electrically-programmable read-only-memory (EPROM) or a flash memory array structure that controls oxide thinning to prevent shorts in the array and trenching of the bit lines is provided. The method includes the following steps. First, in accordance with conventional processing techniques, layers of gate oxide, polyl, ONO, poly cap, and nitride are sequentially deposited on the substrate. Next, in accordance with the present invention, a layer of thin poly is deposited on the layer of nitride. The thin poly/nitride/poly cap/ONO/polyl layers are then etched to define thin poly/nitride/poly cap/ONO/polyl parallel strips. Edge oxide is then formed on the thin poly/nitride/poly cap/ONO/polyl strips. Following this, a layer of spacer oxide is formed over the layer of edge oxide. An anisotropic etch back of the layers of spacer oxide and edge oxide is then performed until the thin poly layer and the substrate are exposed.
    Type: Grant
    Filed: October 28, 1993
    Date of Patent: March 14, 1995
    Assignee: National Semiconductor Corporation
    Inventors: Graham R. Wolstenholme, Albert Bergemont
  • Patent number: 5371047
    Abstract: An integrated circuit having organic dielectric between interconnection layers eliminates damage caused by vapors outgassing from the organic dielectric by the use of a two-component organic layer having a breathable etch resistant organic layer above the main organic dielectric layer, both of the organic layers remaining in the final circuit. The etch resistant layer is resistant to the etchant used to pattern the layer of interconnect above the organic dielectric.
    Type: Grant
    Filed: October 30, 1992
    Date of Patent: December 6, 1994
    Assignee: International Business Machines Corporation
    Inventors: Stephen E. Greco, Kris V. Srikrishnan
  • Patent number: 5294295
    Abstract: For passivation of an integrated circuit device, a film of silicon dioxide is deposited over the integrated circuit device. A film of silicon nitride is deposited over the film of silicon dioxide. The film of silicon nitride and the film of silicon dioxide are etched using a single passivation mask to expose the bond pads of the integrated circuit device. Spacer regions of silicon nitride are placed over edges of the film of silicon dioxide exposed by the etching. The spacer regions may be placed by depositing a second film of silicon nitride over the film of silicon nitride. This second film of silicon nitride covers the metal bond pads and the exposed edges of the film of silicon dioxide. An anisotropic etchback of the second film of silicon nitride is performed to expose the metal bond pads while leaving spacer regions which cover the edges of the film of silicon dioxide.
    Type: Grant
    Filed: October 31, 1991
    Date of Patent: March 15, 1994
    Assignee: VLSI Technology, Inc.
    Inventor: Calvin T. Gabriel
  • Patent number: 5286677
    Abstract: A method is described for etching contact openings through first and second interlevel dielectric layers covering the peripheral circuits of a DRAM integrated circuit to be electrically contacted in a semiconductor wafer is described. There is provided within and over the semiconductor wafer DRAM integrated circuit including peripheral circuits to be electrically contacted. A first conductive layer is formed over the DRAM integrated circuit and the layer is patterned. A first interlevel dielectric layer is formed over the first conductive layer which has been patterned. The first interlevel layer is composed of in the order from the first conductive layer of a silicon oxide layer and a borophosphosilicate layer. A second conductive layer is formed over the first interlevel dielectric layer and the second conductive layer is patterning said second conductive layer. A second interlevel dielectric layer is formed over the exposed second conductive layer and first interlevel dielectric.
    Type: Grant
    Filed: May 7, 1993
    Date of Patent: February 15, 1994
    Assignee: Industrial Technology Research Institute
    Inventor: Kuo-Chang Wu
  • Patent number: 5219792
    Abstract: Disclosed is a method for manufacturing a semiconductor device.
    Type: Grant
    Filed: July 18, 1991
    Date of Patent: June 15, 1993
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jang-rae Kim, Han-su Kim
  • Patent number: 5210045
    Abstract: A dual dielectric structure is employed in the fabrication of thin film field effect transistors in a matrix addressed liquid display to provide improved transistor device characteristics and also to provide both electrical and chemical isolation for material employed in the gate metallization layer. In particular, the use of a layer of silicon oxide over the gate metallization layer is not only consistent with providing the desired electrical and chemical isolation, but also with providing redundant gate metallization material to be employed beneath source or data lines for electrical circuit redundancy. Gate line redundancy is also possible. The electrical and chemical isolation provided by the dual dielectric layer reduces the possibilities of short circuits occurring in the display. The absence of short circuits together with the improved redundancy characteristics significantly increase manufacturing yield.
    Type: Grant
    Filed: May 18, 1992
    Date of Patent: May 11, 1993
    Assignee: General Electric Company
    Inventors: George E. Possin, Harold G. Parks, Jack D. Kingsley
  • Patent number: 5208189
    Abstract: Defects in a thin dielectric layer of a semiconductor device are plugged by a discontinuous layer to maintain integrity of the dielectric without degrading the reliability of the device. In one form of the invention, a semiconductor device (10) includes an oxide layer (14) formed on a substrate material (12). Growth of a nitride layer (18), using CVD techniques, is initiated in any defects (16) in the oxide layer, but growth is terminated prior to entering a continuous growth stage. By plugging the defects with nitride without forming a continuous nitride layer, defect density in thin oxides is reduced without experiencing disadvantages associated with thick oxide-nitride stacks. The invention is also applicable to plugging defects in dielectric layers other than oxide. Furthermore, growth of a discontinuous layer may be achieved with a material other than a nitride using CVD techniques.
    Type: Grant
    Filed: September 30, 1991
    Date of Patent: May 4, 1993
    Assignee: Motorola, Inc.
    Inventors: Bich-Yen Nguyen, Philip J. Tobin
  • Patent number: 5182221
    Abstract: A method of filling a recess so that it is flat with a material by a bias ECR-CVD process is capable of depositing the recess with the material without resulting in the increase in the aspect ratio of the recess with the progress of the deposition process and without forming any voids in the material filling up the recess. A method in accordance with the present invention is characterized in that the bias ECR-CVD process is controlled so as to meet a condition expressed by: R=2y/x, where R is the deposition rate ratio, namely, the ratio of a vertical deposition rate at which the material is deposited on the vertical side surface of the recess to a deposition rate at which the material deposited on the horizontal bottom surface of the recess, x is the width of the recess and y is the depth of the recess.
    Type: Grant
    Filed: June 12, 1991
    Date of Patent: January 26, 1993
    Assignee: Sony Corporation
    Inventor: Junichi Sato
  • Patent number: 5171705
    Abstract: Method and structure is disclosed for a high-density DMOS transistor with an improved body contact. The improvement comprises a self-aligned structure in combination with a body contact region which overdopes the source region in order to minimize the number of critical photoresist steps. The use of two dielectric spacers obviates the need for a separate contact mask.
    Type: Grant
    Filed: November 22, 1991
    Date of Patent: December 15, 1992
    Assignee: Supertex, Inc.
    Inventor: Benedict C. K. Choy
  • Patent number: 5094984
    Abstract: A method for encapsulation of an integrated circuit array that suppresses or eliminates absorption and subsequent out-gassing of water vapor and suppresses or eliminates out-gassing of toxic constituents of the encapsulation layer such as trimethyl borate. A first layer of borophosphosilicate glass is deposited on the integrated circuit array, followed immediately by deposit of a thin cap layer of undoped oxide of silicon. The method also allows use of boron and phosphorous concentrations in the borophosphosilicate glass as high as 9 weight percent with no loss of stability of that layer, before or after thermal treatment. Reflow processing temperatures as low as T.sub.r =700.degree.-900.degree. C. may be used here. Alternatively, silicon nitride can replace the silicon oxide in the cap layer, using either a high temperature process or a lower temperature plasma-enhanced process.
    Type: Grant
    Filed: June 25, 1991
    Date of Patent: March 10, 1992
    Assignee: Hewlett-Packard Company
    Inventors: Charles C. Liu, Krzysztof Nauka
  • Patent number: 5073510
    Abstract: According to the present invention, the incomplete silicon exposure is prevented by the sufficient overetching after the formation of an etching-stop layer on an oxide layer for protecting a conductive layer from the damage of the protective oxide layer when the self-aligned contact window is formed. Therefore, the thickness of the protective oxide layer can be minimized, and the bend of the chip can be improved whereby the following process will be accomplished easily.
    Type: Grant
    Filed: October 23, 1990
    Date of Patent: December 17, 1991
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Oh-Hyun Kwon, Taek-Yong Jang, Jung-Hyun Shin, Won-Taek Choi
  • Patent number: 5070037
    Abstract: This invention comprehends a multilevel electrically conductive interconnect for an integrated circuit wherein an inventive feature of the interconnect is the intermediate dual dielectric layer between the non-contacting portions of the surrounding metal conductors. The dual dielectric layer consists of a first dielectric layer and a second dielectric layer preferably formed from a polyimide material. The dual dielectric layer provides a significant improvement in defect density and a substantially planarized surface for the deposition of the top conductor, thereby improving the reliability and integrity of the electrical interconnection and integrated circuit.
    Type: Grant
    Filed: August 31, 1989
    Date of Patent: December 3, 1991
    Assignee: Delco Electronics Corporation
    Inventors: Ronald K. Leisure, Oya F. Larsen, Ronald K. Reger
  • Patent number: 5061644
    Abstract: A method of forming a self-aligned contact to a transistor component located on a semiconductor substrate comprising forming a transistor component opening in a masking layer overlying a semiconductor substrate and using epitaxial lateral overgrowth to form a self-aligned contact, the epitaxial overgrowth beginning in the masking layer opening at an upper surface of the semiconductor substrate and extending normal to and laterally over the masking layer surface.
    Type: Grant
    Filed: September 20, 1990
    Date of Patent: October 29, 1991
    Assignee: Honeywell Inc.
    Inventors: Jerry Yue, Michael S. T. Liu
  • Patent number: 5023192
    Abstract: A first device region (20) of one conductivity type is provided adjacent one major surface (11) of a semiconductor body (10). A layer (30) doped with impurities of the opposite conductivity type is provided on the one major surface (11) for forming an extrinsic subsidiary region (41) of a second device region (40) of the opposite conductivity type. An opening (31) is formed through the doped layer (30). Impurities for forming a coupling region (43) of the opposite conductivity type are introduced through the opening (31) prior to defining an insulating first portion (50) on the side wall (32) of the doped layer (30) to form a first window (80). Impurities for forming an intrinsic subsidiary region (42) of the second device region (40) are introduced through the first window (80).
    Type: Grant
    Filed: September 13, 1990
    Date of Patent: June 11, 1991
    Assignee: U.S. Philips Corporation
    Inventors: Wilhelmus J. Josquin, Jan Van Dijk
  • Patent number: 5006485
    Abstract: A method of manufacturing integrated circuit is set forth in which a plurality of conducting patterns are formed on a substrate and dielectric material is deposited on the surface of the substrate and thereafter etched. The invention involves forming the dielectric material from two separate dielectric layers having respectively formed thicknesses such that upon etching the top dielectric layer is completely removed, while the underlying dielectric layer is removed according to the underlying type of conductive pattern.
    Type: Grant
    Filed: December 4, 1989
    Date of Patent: April 9, 1991
    Assignee: U.S. Philips Corporation
    Inventor: Claudine Villalon
  • Patent number: 5003062
    Abstract: A method is described for planarization of dielectric layers between conductor layers in multilayer metallurgy of submicron integrated circuit devices. The method begins with the integrated circuit intermediate product having devices, such as FETs or bipolar formed therein, but before interconnection metallurgy has been formed on the principal surface of the product. The principal surface has a patterned conductive layer at its surface. The spin-on-glass sandwich now is begun to be formed by depositing a silicon dioxide coating over the patterned conductor layer. A first layer of spin-on-glass is deposited upon the silicon dioxide coating. The layer is baked at a temperature of less than about 350 degrees C. Vacuum degassing of the coating at less than about 100 mtorr and 350 degrees C. effectively overcomes the outgassing problem by removing unwanted gases in the glass layer at this point in the process.
    Type: Grant
    Filed: April 19, 1990
    Date of Patent: March 26, 1991
    Assignee: Taiwan Semiconductor Manufacturing Co.
    Inventor: Daniel L. Yen
  • Patent number: 5001076
    Abstract: A III-V semiconductor surface (10') of a III-V substrate (10) is provided with a thick dielectric layer (40), preferably comprising a composite nitride/oxide layer (40a/40b). A layer of comparatively thin silicon nitride layer (40a) is formed on the substrate and a comparatively thicker silicon dioxide layer (40b) is formed thereover. The composite dielectric layer acts as a good ion absorber during ion implantation (54), thereby masking the substrate from ions in undersirable locations. Further, the composite dielectric layer provides appropriate contrast for alignment marks, thereby reducing the number of masking steps and the amount of gate area in FETs otherwise required to compensate for potential misalignment. The composite dielectric layer affords surface protection, which not only keeps the semiconductor clean during processing, but also provides a cap during annealing.
    Type: Grant
    Filed: April 19, 1989
    Date of Patent: March 19, 1991
    Assignee: Vitesse Semiconductor Corporation
    Inventor: James M. Mikkelson
  • Patent number: 4996165
    Abstract: A method for planarizing surfaces in multi-layered semiconductor structures using elevated features in the form of semiconductor materials, such as for forming heterojunctions, or interconnection metal. A process of forming the features includes leaving residual photoresist on the features. After feature formation and definition of transistor or other structure locations, dielectric material is deposited across the structure. Remaining photoresist is subsequently removed along with dielectric deposited thereon leaving dielectric between the features. A layer of polyimide is spun on the structure and into depressions between the dielectric and features. Typically material deposition, etching, dielectric backfilling and spin-coating steps are repeated until a predetermined number of contact or conductivity regions or interconnection metal layers are formed in the desired multi-layered structure.
    Type: Grant
    Filed: April 21, 1989
    Date of Patent: February 26, 1991
    Assignee: Rockwell International Corporation
    Inventors: Mau-Chung F. Chang, Peter M. Asbeck
  • Patent number: 4966865
    Abstract: A method for planarizing a semiconductor slice prior to its metallization is disclosed. The semiconductor slice is processed so as to form the diffusions and underlying interconnection layers using well known techniques. After the deposition and patterning of the last interconnection layer prior to metallization, a layer of platinum or another metal is deposited onto the slice. The slice is sintered to form a silicide film on those portions of the interconnection layers and diffusions which were directly exposed to the sputtered platinum. A layer of phosphorous-doped dielectric is then deposited, followed by a layer of undoped oxide. Photoresist or another conformal material is spun on to the slice, resulting in a planar top surface. The slice is exposed to a plasma etch which etches both the photoresist and the undoped oxide, resulting in a top surface of the undoped oxide which is substantially planar.
    Type: Grant
    Filed: September 16, 1988
    Date of Patent: October 30, 1990
    Assignee: Texas Instruments Incorporated
    Inventors: Michael T. Welch, Ronald E. McMann, Manuel L. Torreno, Jr., Evaristo Garcia, Jr., Jeffrey E. Brighton
  • Patent number: 4960723
    Abstract: An improved method for making a self-aligned vertical field effect transistor is provided wherein a nitride sidewall spacer is formed around a polysilicon gate, and an oxide sidewall spacer, which may be heavily doped with an n-type dopant, is formed covering the silicon nitride sidewall spacer. The silicon nitride sidewall spacer allows the oxide sidewall spacer of a conventional self-aligned vertical field effect transistor process to be removed partially or completely before making ohmic contact to the source thus increasing the contact area between the source and the source electrode and eliminating reliability problems related to n-type doped oxide in contact with aluminum electrodes.
    Type: Grant
    Filed: March 30, 1989
    Date of Patent: October 2, 1990
    Assignee: Motorola, Inc.
    Inventor: Robert B. Davies
  • Patent number: 4950624
    Abstract: An improved CVD apparatus for depositing a uniform film is shown. The apparatus comprises a reaction chamber, a substrate holder and a plurality of light source for photo CVD or a pair of electrode for plasma CVD. The substrate holder is a cylindrical cart which is encircled by the light sources, and which is rotated around its axis by a driving device. With this configuration, the substrates mounted on the cart and the surroundings can be energized by light or plasma evenly throughout the surfaces to be coated.
    Type: Grant
    Filed: May 16, 1988
    Date of Patent: August 21, 1990
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takashi Inuzima, Shigenori Hayashi, Toru Takayama, Seiichi Odaka, Naoki Hirose
  • Patent number: 4870032
    Abstract: Certain semiconductor device structures are described in which single crystal layers of cubic Group II fluorides cover at least part of the surface of III-V semiconductor compound. The Fluoride crystal has a cubic structure and may be lattice matched or lattice mismatched to the compound semiconductor substrate depending on fluoride composition. These fluoride single crystal layers are put down by a molecular beam epitaxy procedure using certain critical substrate temperature ranges and a particular cleaning procedure.
    Type: Grant
    Filed: March 24, 1987
    Date of Patent: September 26, 1989
    Assignee: American Telephone and Telegraph Company, AT&T Bell Laboratories
    Inventors: Wilbur D. Johnston, Jr., Charles W. Tu
  • Patent number: 4845048
    Abstract: A method of fabricating a semiconductor device which includes:(1) a step of forming an opening in a silicon substrate using a first silicon oxide film and a first silicon nitride film formed on the silicon substrate as masks,(2) a step of forming a second silicon oxide film and a second silicon nitride film on the side wall of the opening by the reduced pressure CVD method and anisotropic etching method,(3) a step of performing isotropic dry etching using the first and second silicon oxide films as masks, and(4) a step of performing heat treatment in an oxidizing atmosphere using the first and second silicon nitride films as masks.Thereby, uniform isotropic etching may be accomplished by use of the dry etching method.
    Type: Grant
    Filed: November 7, 1988
    Date of Patent: July 4, 1989
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Tokuhiko Tamaki, Masafumi Kubota
  • Patent number: 4808552
    Abstract: A process is disclosed for making a conductive interconnecting path formed between two conductive areas of an integrated circuit, the conductive areas separated by at least an insulating layer of silicon nitride over a layer of oxide. The interconnecting path is formed by depositing a thick insulator coating, over the conductive and non-conductive areas then forming a vertical-walled trench, with said silicon nitride acting as an etch stop, in the thick insulator between conducting areas, then filling the trench with conductive material using chemical vapor deposition, and finally removing conductive material except for that conductive material deposited in the trench.
    Type: Grant
    Filed: June 2, 1987
    Date of Patent: February 28, 1989
    Assignee: Texas Instruments Incorporated
    Inventor: Dirk N. Anderson
  • Patent number: 4795722
    Abstract: A method for planarizing a semiconductor slice prior to its metallization is disclosed. The semiconductor slice is processed so as to form the diffusions and underlying interconnection layers using well known techniques. After the deposition and patterning of the last interconnection layer prior to metallization, a layer of the platinum or another metal is deposited onto the slice. The slice is sintered to form a silicide film on those portions of the interconnection layers and diffusions which were directly exposed to the sputtered platinum. A layer of phosphorous-doped dielectric is then deposited, followed by a layer of undoped oxide. Photoresist or another conformal material is spun on to the slice, resulting in a planar top surface. The slice is exposed to a plasma etch which etches both the photoresist and the undoped oxide, resulting in a top surface of the undoped oxide which is substantially planar.
    Type: Grant
    Filed: February 5, 1987
    Date of Patent: January 3, 1989
    Assignee: Texas Instruments Incorporated
    Inventors: Michael T. Welch, Ronald E. McMann, Manuel L. Torreno, Jr., Evaristo Garcia, Jr., Jeffrey E. Brighton
  • Patent number: 4692997
    Abstract: An MOMOM semiconductor device (72) has a plurality of mesa stacked horizontal layers including at least one metal layer (75) having an exposed edge at a generally vertical side (86) of the mesa. An oxide layer (76) is formed on the exposed edge of the metal layer. A second metal layer (77) extends along the side of the mesa over the first oxide layer. A second oxide layer (78) is formed on the second metal layer, and a third metal layer (79) is formed on the second oxide layer. An MOMOM tunnel emission transistor is provided by emitter metal (75) - oxide (76) - base metal (77) - oxide (78) - collector metal (79).
    Type: Grant
    Filed: May 15, 1986
    Date of Patent: September 15, 1987
    Assignee: Eaton Corporation
    Inventor: Joseph A. Calviello
  • Patent number: 4692998
    Abstract: A process for the fabrication of semiconductor components and in particular a process in which the components are fabricated with a controlled spacing of etched channels. The process is in particular utilized in fabricating a monolithic array of elements such as a pin diode array. The process of the present invention combines the use of an anisotropic silicon etching process for the desired device geometries with a means of defining all device surface topology by substantially a single photomask thus eliminating critical mask alignment. A second embodiment of the invention is also described employing fewer layers of deposition with a double photomask step.
    Type: Grant
    Filed: January 12, 1985
    Date of Patent: September 15, 1987
    Assignee: M/A-COM, Inc.
    Inventors: Albert L. Armstrong, Joel L. Goodrich
  • Patent number: 4665608
    Abstract: A method of manufacturing a semiconductor device comprises a step of preparing a semiconductor substrate (12) having a surface layer of silicon, a step of forming a conductive thin film (14) of a silicide composed of a metal having a high melting point and silicon on the semiconductor substrate (12), a step of forming an oxidation-resistant mask (18) on a first portion (14a) of the conductive thin film (14) and a step of converting a second, exposed, portion (19) of the conductive thin film (14) into an insulating film (19a) of a composite oxide composed of silicon oxide and an oxide of the subject metal by oxidizing the exposed portion (19) while maintaining the first portion (14a) of the conductive thin film (14) covered by the mask (18).
    Type: Grant
    Filed: December 14, 1984
    Date of Patent: May 19, 1987
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tatsuo Okamoto, Hiroshi Harada
  • Patent number: 4649630
    Abstract: A process is disclosed for controllably providing dielectrically isolated semiconductor regions having a uniform and well defined thickness. Grooves are formed in a first surface of a semiconductor substrate and then a dielectric layer is formed covering that surface and the grooves extending into the surface. A layer of backing material such as polycrystalline silicon is formed overlying the dielectric layer. A semiconductor substrate is then thinned to form a new surface with portions of the dielectric layer and backing material exposed at that surface. A semiconductor layer is epitaxially grown overlying the new surface with the semiconductor layer having a monocrystalline structure where it is grown on exposed regions of the original substrate and having a polycrystalline structure otherwise. An oxidation masking layer is formed overlying those portions of the semiconductor layer which have a monocrystalline structure.
    Type: Grant
    Filed: April 1, 1985
    Date of Patent: March 17, 1987
    Assignee: Motorola, Inc.
    Inventors: Bernard W. Boland, Paul W. Sanders
  • Patent number: 4581622
    Abstract: A silicon nitride film containing from 20 to 70% oxygen, for use as a surface passivation film, has enhanced ultraviolet ray transmissivity while exhibiting the desirable moisture proofness quality of a silicon nitride film.
    Type: Grant
    Filed: February 13, 1984
    Date of Patent: April 8, 1986
    Assignee: Fujitsu Limited
    Inventors: Kanetake Takasaki, Mikio Takagi, Kenji Koyama
  • Patent number: 4571819
    Abstract: A method for forming trench isolation oxide using doped silicon dioxide which is reflowed at elevated temperatures to collapse any voids therein and produce surface planarity. An underlying layered composite selected from oxide, polysilicon and silicon nitride permits the formation and reflow of the doped isolation oxide and remains in place in the trench to contribute to the trench isolation structure.
    Type: Grant
    Filed: November 1, 1984
    Date of Patent: February 25, 1986
    Assignee: NCR Corporation
    Inventors: Steven H. Rogers, Randall S. Mundt, Denise A. Kaya
  • Patent number: 4558508
    Abstract: A process for making a CMOS dual-well semiconductor structure with field isolation doping, wherein only a single lithographic masking step is required for providing self-alignment both of the wells to each other and also of the field isolation doping regions to the wells. The lithographic masking step forms a well mask and defines an oxidation barrier which acts as: an implant mask (absorber) during the ion-implantation of a field dopant of one type; an oxidation barrier over one well during the oxidation of the opposite-type well to form over the one well a sacrificial oxide layer which forms the alignment marks for subsequent formation of the field-doping regions; and a dopant-transmitter during the ion-implantation of an opposite-type field dopant which is simultaneously absorbed by the sacrificial oxide. As a result, there are formed field-doped oxide layers self-aligned to the wells so that, with a subsequent masking step, oxide field isolations are defined over the doped oxide layers.
    Type: Grant
    Filed: October 15, 1984
    Date of Patent: December 17, 1985
    Assignee: International Business Machines Corporation
    Inventors: Wayne I. Kinney, Charles W. Koburger, III, Jerome B. Lasky, Larry A. Nesbit, Ronald R. Troutman, Francis R. White
  • Patent number: 4536947
    Abstract: A CMOS process is described which is particularly suited for forming dynamic memory cells. The cells are formed in an n-well and a single plate member formed from a first layer of polysilicon is used for the entire array. Unique etching of the first polysilicon layer prevents stringers from occurring when the second layer of polysilicon is deposited. A tri-layer dielectric is used for the capacitors in the array. Novel "rear-end" processing is disclosed using a phosphorus doped glass.
    Type: Grant
    Filed: July 2, 1984
    Date of Patent: August 27, 1985
    Assignee: Intel Corporation
    Inventors: Mark T. Bohr, Ken K. Yu, Leo D. Yau, Shyam G. Garg