Edge Diffusion Under Mask Patents (Class 148/DIG44)
  • Patent number: 5882981
    Abstract: After formation of a sandwich over a substrate of a layer of silicon dioxide (3) followed by a layer of silicon (1) having a pad oxide (7) thereon and a patterned silicon nitride layer (9) over the pad oxide, the unmasked portion of the pad oxide and silicon are removed to provide mesas of silicon with silicon nitride thereover and possibly removal of some of the buried oxide layer. A flowable insulator (15), preferably silsesquioxane (H.sub.x SiO.sub.1.5, where x.ltoreq.1, depending upon the level of polymerization) in a contaminant-free, high purity solvent which is later removed during an annealing step, is placed over the exposed surface such that it fills the voids between the mesas of silicon with silicon nitride thereon and extends over the nitride. The flowable insulator, due to its flowability, provides a generally planar surface. The flowable insulator is etched back and a cap oxide (17) is optionally deposited over the etched back insulator layer.
    Type: Grant
    Filed: July 29, 1997
    Date of Patent: March 16, 1999
    Assignee: Texas Instruments Incorporated
    Inventors: Rajan Rajgopal, Kelly J. Taylor, Thomas R. Seha, Keith A. Joyner
  • Patent number: 5672528
    Abstract: A semiconductor device characterized by a field limiting ring formed by a number of field limiting cells that define wells which are laterally diffused to form a continuous equipotential ring between interior and exterior regions of a semiconductor device. A number of active cells are formed in the interior region, and are therefore delineated from the exterior region of the device. Each of these active cells is a transistor, and preferably a field-effect transistor, whose structure is essentially identical to the field limiting cells, except that their wells are not merged but instead are isolated from each other. The field limiting ring increases the breakdown voltage and the ruggedness of device, and therefore enables the device to sustain high voltages when the device is in the off-state. The process does not require masking, implanting and diffusion steps for the sole purpose of forming the field limiting ring, but is instead fully integrated with the semiconductor process for forming the active cells.
    Type: Grant
    Filed: April 22, 1996
    Date of Patent: September 30, 1997
    Assignee: Delco Electronics Corporation
    Inventors: Donald Ray Disney, Wayne Anthony Sozansky, James Max Himelick
  • Patent number: 5650344
    Abstract: A method of making a semiconductor device in which a polysilicon gate is separated from a semiconductor substrate by a re-oxidized nitrided oxide film and in which the concentration of re-oxidized nitride in the film underlying the gate is non-uniform. The concentration of nitrogen in the substrate and the re-oxidized nitrided oxide along their interface and underlying the gate is non-uniform. The non-uniform concentrations are provided by incomplete shielding of the oxide by the gate during the nitriding and re-oxidizing processes.
    Type: Grant
    Filed: July 17, 1995
    Date of Patent: July 22, 1997
    Assignee: Harris Corporation
    Inventors: Akira Ito, John T. Gasner
  • Patent number: 5053345
    Abstract: SOI islands having doped edges are formed by providing over the surface of a layer of single crystalline silicon on an insulating substrate a masking layer formed of two layers, the lowermost layer adjacent the silicon layer being silicon oxide and the uppermost layer being silicon nitride. The masking layer is defined using standard photolithographic techniques and etching to form the masking layer over only the areas of the silicon layer which are to form the islands. The uncovered portion of the silicon layer is then removed by etching to form the islands. The lowermost layer of the masking layer is then etched laterally away from the edges of the island to expose a portion of the surface of the silicon layer adjacent the edges of the islands. After removing the uppermost layer of the masking layer, the exposed edge portions of the surface of the silicon layer are doped by ion implantation to form the islands with doped edges.
    Type: Grant
    Filed: February 20, 1989
    Date of Patent: October 1, 1991
    Assignee: Harris Corporation
    Inventors: George L. Schnable, Albert W. Fisher
  • Patent number: 5039623
    Abstract: A semiconductor body (10) has at one major surface (15) a step (14) defining a device area (13) of the semiconductor body above a buried region (12) provided within the semiconductor body (10). A protective insulating layer (24) is provided on a side wall (14a) of the step (14) and an insulating region (22) on an area (15a) of the one major surface adjoining the side wall (14a) of the step. Silicon is deposited over the one surface (15) with the anti-oxidation layer (24) on the side wall (14a) of the step (14) to define over the area (15a) of the one surface (15) an intermediate silicon region (23c) which is isolated from the side wall (14a) of the step and which leaves a window area (14'a) of the side wall (14a) exposed. The protective insulating layer (24a) is then removed from the window area (14'a) of the side wall (14a).
    Type: Grant
    Filed: April 3, 1990
    Date of Patent: August 13, 1991
    Assignee: U.S. Philips Corporation
    Inventors: Henricus G. R. Maas, Roland A. Van Es, Johannes W. A. Van Der Velden
  • Patent number: 5028564
    Abstract: Methods of fabricating heavily doped edges of mesa structures in silicon-on-sapphire and silicon-on-insulator semiconductor devices. The methods are self-aligning and require a minimum of masking steps to achieve. The disclosed methods reduce edge leakage and resolve N-channel threshold voltage instability problems. Mesa structures are formed that comprise N-channel and P-channel regions having a thermal oxide layer deposited thereover. A doping layer of borosilicate glass, or alternatively, an undoped oxide layer that is subsequently implanted, is deposited over the mesa structures. In the first method, the doping layer is etched by means of an anisotropic plasma etching procedure to form oxide spacers at the edges of the mesa structures. The doping layer is removed from the N-mesa structures using an N-channel mask and wet oxide etching procedure. The structure is then heated to a relatively high temperature to drive the dopant into the edges of the N-channel mesa structures.
    Type: Grant
    Filed: April 27, 1989
    Date of Patent: July 2, 1991
    Inventors: Chen-Chi P. Chang, Kuan Y. Liao, Joseph E. Farb
  • Patent number: 4755479
    Abstract: With an increase of integration density in an integrated circuit, the channel length of MIS FET becomes shorter and shorter, which causes a hot carrier effect. To solve the problem, the doping profile of source/drain regions and doping amount must be precisely controlled such that a strong electric field is not generated in a transition region from channel to drain. To obtain this objective, the present invention discloses a method, in which reflowed sidewalls of doped silicate glass having a gentle slope are formed on both sides of a gate electrode, and the gate electrode and the sidewalls thus formed are used as a mask for ion implantation. The depth of ion implantation and the doping amount change gradually from the channel region to the drain region avoiding a generation of the strong electric field and thus alleviates the short channel trouble.
    Type: Grant
    Filed: February 4, 1987
    Date of Patent: July 5, 1988
    Assignee: Fujitsu Limited
    Inventor: Takao Miura