Abstract: An improved planarization process includes the steps of forming recessed regions (38) and elevated regions (34) in a semiconductor substrate (30). The substrate is oxidized to form an oxide liner (39) overlying the recessed regions, and a fill material (40) is deposited to overlie the substrate (30) filling the recessed regions (38). An etching process is used to remove portions of the fill material (40) and to expose portions of a first planarization layer (44) overlying the elevated regions (34) of the substrate (30). The fill material is etched and a second planarization layer (46) is deposited to overlie dielectric portions (42), and portions (44) of first planarization layer (32) exposed by the etching process. A chemical-mechanical-polishing process is then carried out to form a planar surface (47), and remaining portions of the planarization layers and fill material are removed.

Abstract: Tri-isopropylantimony is used as a source of antimony in chemical vapor deposition production of semiconductor materials. The process can be used to introduce antimony as a dopant into III/V and II/VI semiconductor materials.

Abstract: A semiconductor device includes an InP substrate, an intrinsic InGaAs channel layer formed on the InP substrate and lattice matched to the InP substrate, a doped GaAsSb carrier supply layer formed on the intrinsic InGaAs channel layer and lattice matched to the InP substrate, a gate electrode formed on the doped GaAsSb carrier supply layer, and a source electrode and a drain electrode which are respectively formed on the doped GaAsSb carrier supply layer and located on both sides of the gate electrode.

Abstract: III-V films are grown on large automatically perfect terraces of III-V substrates which have a different lattice constant, with temperature and Group II and V arrival rates chosen to give a Group III element stable surface. The growth is pulsed to inhibit Group III metal accumulation to low temperature, and to permit the film to relax to equilibrium. The method of the invention 1) minimizes starting step density on sample surface; 2) deposits InAs and GaAs using an interrupted growth mode (0.25 to 2 mono-layers at a time); 3) maintains the instantaneous surface stoichiometry during growth (As-stable for GaAs, In-stable for InAs); and 4) uses time-resolved RHEED to achieve aspects (1)-14 (3).

Abstract: A method for fabricating a semiconductor device comprises the steps of forming the first semiconductor layer on a semiconductor substrate, forming a surface protection layer of antimony (Sb) or the material having Sb as its main component, executing the other steps necessary for the fabrication of the semiconductor device, removing the surface protection layer, and forming, on the first semiconductor layer thus exposed, the second semiconductor layer.

Abstract: A process for preparing high sensitivity indium antimonide film magnetoresistance element. A silicon single crystal wafer is treated with oxidative diffusion to form a layer of silicon oxide on the surface of the silicon single crystal, a layer of indium antimonide is grown on the substrate by vapor deposition, and the indium antimonide layer is then subjected to a specific annealing treatment in which the indium antimonide layer is partially oxidized and then re-crystallized. The resultant magnetoresistance element possessing improved sensitivity, stability and suitable for large scale production is obtained.

Abstract: This invention relates to ultra-thin semiconductor films which can be in the submicron range formed from semiconductor materials such as silicon, germanium and gallium arsenide. The films are formed by creating a thin slightly damaged surface on the polished reverse side of a film (e.g., a wafer) of the semiconductor by low dose ion implantation and then etching the semiconductor material on the front side of the film to remove the semiconductor material down to the ion implanted damaged layer. While the implanted ions can be chosen from functionally desirable ions which upon annealing remain in the film to alter the original electrical characteristics, the implanted ions can also be chosen so that upon annealing, the resultant ultra-thin semiconductor film has the same electrical characteristics as the original semiconductor material.The ion implantation changes the etching characteristics of the ion implanted layer.

Abstract: This invention relates to ultra-thin semiconductor films which can be in the submicron range formed from semiconductor materials such as silicon, germanium and gallium aresenide. The films are formed by creating a thin slightly damaged surface on the polished reverse side of a film (e.g., a wafer) of the semiconductor by low dose ion implantation and then etching the semiconductor material on the front side of the film to remove the semiconductor material down to the ion implanted damaged layer. While the implanted ions can be chosen from functionally desirable ions which upon annealing remain in the film to alter the original electrical characteristics, the implanted ions can also be chosen so that upon annealing, the resultant ultra-thin semiconductor film has the same electrical characteristics as the original semiconductor material.The ion implantation changes the etching characteristics of the ion implanted layer.

Abstract: An improved system and method for annealing indium antimonide ion implanted junctions employing an open-tube benign annealing environment. A furnace having a hollow chamber therein is maintained continuously at a predetermined annealing temperature and wafers of indium antimonide to be annealed are inserted into the chamber through a resealable airlock at one end of the chamber. A source of molten indium saturated with antimony is provided within the chamber to maintain desired partial pressures of indium and antimony within the chamber. Hydrogen gas is continuously flushed through the chamber to purge contaminants and maintain the chamber at a desired slight overpressure over atmospheric. At the conclusion of annealing, the indium antimonide wafer is removed from the chamber into the airlock which is flushed with hydrogen gas. The wafer is allowed to cool to room temperature and removed from the airlock for subsequent processing steps.

Abstract: An intermetallic compound semiconductor thin film comprises a single crystalline deposition thin film made of a III-V group intermetallic compound having a stoichiometry composition ratio of 1:1. When forming the III-V group semiconductor thin film by an evaporation method, a substrate temperature is initially maintained at a high level while the evaporation source temperature is gradually raised, and when the intermetallic composition of the III-V group begins to deposit on the substrate, the substrate temperature is lowered while the evaporation source temperature is maintained at the same level as existed at the time when the intermetallic compound is deposited, and the deposition time is controlled.