Etching Patents (Class 148/DIG51)
  • Patent number: 5981326
    Abstract: This invention is a processing method for electrically isolating CMOS transistors. The method involves implanting a channel stop dopant into field regions between transistor active regions, self aligning relatively thick silicon dioxide over these field regions and providing thin oxide in the active regions that are self aligned to the field regions. The method does not require any shallow trench isolation (STI), and does not require Local Oxidation of Silicon (LOCOS), thereby resulting in little damage to the silicon.
    Type: Grant
    Filed: March 23, 1998
    Date of Patent: November 9, 1999
    Inventor: Frank M. Wanlass
  • Patent number: 5926705
    Abstract: In a method for manufacturing an LDD-structured MOS transistor and a bipolar transistor, a gate insulating layer is formed on a MOS transistor region and a bipolar transistor region. Then, a gate electrode is formed on the MOS transistor region. Then, an insulating layer is formed on the entire surface, and as etched back by a reactive ion etching process to form a sidewall spacer. The MOS transistor region and the bipolar transistor region are etched by a wet etching process using the gate electrode and its sidewall spacer as a mask.
    Type: Grant
    Filed: October 21, 1996
    Date of Patent: July 20, 1999
    Assignee: NEC Corporation
    Inventor: Takuo Nishida
  • Patent number: 5895259
    Abstract: A polysilicon diffusion doping method which employs a deposited dopant-rich oxide layer with a highly uniform distribution of dopant atoms and thickness. Polysilicon layers 1,500 angstroms thick have been doped, achieving average resistance values of 60 ohms and non-uniformity values of 5 percent. Resistance values were measured using the four-point probe method with probe spacings of 0.10 cm. After a polysilicon layer has been formed upon a surface of a silicon wafer, a dopant-rich oxide layer is deposited upon the polysilicon layer at reduced pressure. The dopant-rich oxide layer is deposited, and serves as a source of dopant atoms during the subsequent diffusion process. The dopant-rich oxide layer is a phosphosilicate glass (PSG) including phosphorus pentoxide (P.sub.2 O.sub.5) and phosphorus trioxide (P.sub.2 O.sub.3) and deposited using a PECVD technique.
    Type: Grant
    Filed: May 15, 1996
    Date of Patent: April 20, 1999
    Assignee: Advanced Micro Devices, Inc.
    Inventors: W. Mark Carter, Allen L. Evans, John G. Zvonar
  • Patent number: 5801071
    Abstract: A semiconductor laser diode apparatus has a substrate of a first conduction type, a first clad layer of the first conduction type which is formed on the substrate, a current block layer which is formed on the first clad layer, a V groove stripe which is formed in a vertical direction so that a tip of the V groove can arrive at the first clad layer in depth, an active layer which is formed on the first clad layer and the current block layer along the V groove stripe without a low resistance layer, a second clad layer of a second conduction type which is formed on the active layer, a contact layer of the second conduction type which is formed on the second clad layer, a first electrode which is formed on a surface of the substrate which is reverse side of a surface on which the first clad layer is formed and a second electrode which is formed oil a surface of the contact layer. Therefore a low threshold current level can be achieved.
    Type: Grant
    Filed: July 9, 1996
    Date of Patent: September 1, 1998
    Assignee: Ricoh Company, Ltd.
    Inventor: Takashi Takahashi
  • Patent number: 5801103
    Abstract: The present invention is directed to a novel etching process for a semiconductor material which inhibits corrosion of metal comprised of pretreating the material, preferably with a surfactant, and then exposing the material to a mixture comprising a buffered oxide etch.
    Type: Grant
    Filed: December 4, 1995
    Date of Patent: September 1, 1998
    Assignee: Micron Technology, Inc.
    Inventors: Robert T. Rasmussen, Surjit S. Chadha, David A. Cathey
  • Patent number: 5789301
    Abstract: This is a method of fabricating a heterojunction bipolar transistor on a wafer. The method can comprise: forming a doped subcollector layer 31 on a semiconducting substrate 30; forming a doped collector layer 32 on top of the collector layer, the collector layer doped same conductivity type as the subcollector layer; forming a doped base epilayer 34 on top of the collector layer, the base epilayer doped conductivity type opposite of the collector layer; forming a doped emitter epilayer 36, the emitter epilayer doped conductivity type opposite of the base layer to form the bipolar transistor; forming a doped emitter cap layer 37 on top of the emitter epilayer, the emitter cap layer doped same conductivity as the emitter epilayer; forming an emitter contact 38 on top of the emitter cap layer; forming a base contact on top of the base layer; forming a collector contact on top of the collector layer; and selective etching the collector layer to produce an undercut 45 beneath the base layer.
    Type: Grant
    Filed: October 25, 1996
    Date of Patent: August 4, 1998
    Assignee: TriQuint Semiconductor, Inc.
    Inventor: Darrell Glenn Hill
  • Patent number: 5700701
    Abstract: This is a method of fabricating a bipolar transistor on a wafer. The method can comprise: forming a doped emitter contact layer 31 on a substrate 30; forming a doped emitter layer 32 on top of the emitter contact layer, the emitter layer doped same conductivity type as the emitter contact layer; forming a doped base epilayer 34 on top of the emitter layer, the base epilayer doped conductivity type opposite of the emitter layer; forming a doped collector epilayer 36, the collector epilayer doped conductivity type opposite of the base layer to form the bipolar transistor; forming an collector contact 38 on top of the collector layer; forming a base contact 40 on top of the base layer; forming a emitter contact 44 on top of the emitter contact layer; and selective etching the emitter layer to produce an undercut 45 beneath the base layer.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: December 23, 1997
    Assignee: Texas Instruments Incorporated
    Inventors: Darrell Hill, Shou-Kong Fan, Ali Khatibzadeh
  • Patent number: 5698063
    Abstract: A method for differentially etching an N-sided polygon aperture through a first major surface of a <100> silicon wafer along the <111> planes begins with depositing a mask and defining therein a first intermediate polygon aperture having at least 4N+2 sides, where N is a positive integer. At least one side is generally parallel to the <110> plane, and the intersection of a second side and a third side of the first intermediate polygon is located generally along a major crystal axis perpendicular to the <110> plane. The included angle between the second and third sides expands during anisotropic etching to form one of the N sides of the polygon located along the major axis perpendicular to the <110> plane.
    Type: Grant
    Filed: December 21, 1995
    Date of Patent: December 16, 1997
    Assignee: Ford Motor Company
    Inventor: John Carlson Ames
  • Patent number: 5580800
    Abstract: A thin film transistor according to this invention has a gate electrode comprising a lower layer of aluminum of a high purity of over 99.5% and an upper layer of aluminum containing over 0.5% silicon. Alternatively, it has a gate electrode made by adding a IIIa group element to a IIIb group element. Residues produced by the etching of the silicon-containing aluminum gate electrode are etched with a mixture solution of hydrofluoric acid, nitric acid and acetic acid. After contact holes have been formed in an interlayer insulating film, laser annealing is carried out, and metal electrodes are formed in the contact holes thereafter.
    Type: Grant
    Filed: March 15, 1994
    Date of Patent: December 3, 1996
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hongyong Zhang, Yasuhiko Takemura, Hideki Uochi, Itaru Koyama, Minoru Miyazaki, Akane Murakami, Toshimitsu Konuma, Akira Sugawara, Yukiko Uehara
  • Patent number: 5573960
    Abstract: A method of manufacturing a semiconductor layer includes preparing a first semiconductor substrate; forming an etching stop layer on the surface of the first substrate; forming an active layer on the etching stop layer; forming a crystal defect reducing layer on the active layer; preparing a second semiconductor substrate having a heat conductivity higher than the heat conductivity of the first substrate; bonding the crystal defect reducing layer to the second substrate; selectively etching the first substrate to expose the etching stop layer; selectively etching the etching stop layer to expose the active layer, whereby the active layer is disposed on the second substrate with the crystal defect reducing layer therebetween. The heat dissipation property is significantly improved by the second substrate having a high heat conductivity and by reducing the thicknesses of the active layer and the crystal defect reducing layer.
    Type: Grant
    Filed: July 10, 1995
    Date of Patent: November 12, 1996
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Shigekazu Izumi, Norio Hayafuji
  • Patent number: 5565384
    Abstract: A semiconductor device and process for making the same which reduces capacitance between adjacent conductors on a connection layer, reduces overetching due to via misalignment or uneven device topography, and maintains a rigid structure with good heat transfer characterisitics. In one embodiment, horizontal gaps between the patterned conductors 18 and 44 are substantially filled with an organic-containing dielectric material (Allied Signal 500 Series, for example) 22 and 54. Inorganic dielectric layers 24 and 56 are formed over organic-containing dielectric layers 22 and 54, respectively, from a material such as silicon dioxide. Vias are etched through the inorganic dielectric layers using an etch process such as fluorocarbons in a high density plasma which does not appreciably etch the organic-containing dielectric material.
    Type: Grant
    Filed: April 28, 1994
    Date of Patent: October 15, 1996
    Inventor: Robert H. Havemann
  • Patent number: 5563094
    Abstract: In situ removal of selected or patterned portions of semiconductor layers is accomplished by induced evaporation enhancement to form reversed bias current confinement structures in semiconductor devices, such as heterostructure lasers and array lasers.
    Type: Grant
    Filed: September 6, 1990
    Date of Patent: October 8, 1996
    Assignee: Xerox Corporation
    Inventors: Thomas L. Paoli, John E. Epler
  • Patent number: 5508229
    Abstract: In accordance with the present invention, a method for forming solder bumps begins with a wafer that has been patterned with bond pad areas. A plurality of distinct metal layers are then deposited over the wafer. Subsequently, solder is deposited by way of plating through a mask over the metal layers in the bond pad areas. After the removal of the mask, the metal layers outside of the soldered areas are etched using a dilute phosphoric acid solution, which includes phosphoric acid, acetic acid, hydrogen peroxide, and deionized water. By the use of this solution, the metal layers are removed without attacking the soldered areas. Thus, a pattern of solder bumps are formed. The metal layers include distinct layers of aluminum, nickel-vanadium, and copper. Alternatively, the aluminum layer is eliminated.
    Type: Grant
    Filed: May 24, 1994
    Date of Patent: April 16, 1996
    Assignee: National Semiconductor Corporation
    Inventor: Mark H. Baker
  • Patent number: 5484507
    Abstract: A method for differentially etching an N-sided polygon aperture through a first major surface of a <100> silicon wafer along the <111> planes begins with depositing a mask and defining therein a first intermediate polygon aperture having at least 4N+2 sides, where N is a positive integer. At least one side is generally parallel to the <110> plane, and the intersection of a second side and a third side of the first intermediate polygon is located generally along a major crystal axis perpendicular to the <110> plane. The included angle between the second and third sides expands during anisotropic etching to form one of the N sides of the polygon located along the major axis perpendicular to the <110> plane.
    Type: Grant
    Filed: December 1, 1993
    Date of Patent: January 16, 1996
    Assignee: Ford Motor Company
    Inventor: John C. Ames
  • Patent number: 5476813
    Abstract: In a method of manufacturing a bonded semiconductor substrate, a SiGe mixed crystal layer, a silicon layer containing N-type impurities, a SiGe mixed crystal layer containing N-type impurities of high concentration, and a silicon layer containing N-type impurities of high concentration are formed in this order on a top surface of a silicon substrate by an epitaxial growth process to form a first semiconductor substrate. A silicon oxide film is formed on a surface of a silicon substrate to form a second semiconductor substrate. The first and second semiconductor substrates are bonded to each other by heat treatment, with their top surfaces contacting each other. The first semiconductor substrate is etched from the back surface thereof until the SiGe mixed crystal layer is exposed, and the SiGe mixed crystal layer is etched until the silicon layer containing N-type impurities is exposed. This method prevents the thickness of the element forming layer from varying.
    Type: Grant
    Filed: November 14, 1994
    Date of Patent: December 19, 1995
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroshi Naruse
  • Patent number: 5444020
    Abstract: A method for forming contact holes having different depths in an insulating layer which covers a semiconductor substrate. A first step selectively etches the upper parts of the insulating layer which correspond to contact holes having a greater depth than the shallowest contact hole, using a first mask pattern. A second etch step selectively etches the remainder of the insulating layer for all of the contact holes at the same time using a second mask pattern. Thus, contact hole misalignment is kept to a minimum.
    Type: Grant
    Filed: October 13, 1993
    Date of Patent: August 22, 1995
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung-ku Lee, Kyung-seok Oh
  • Patent number: 5434091
    Abstract: This is a method of fabricating a bipolar transistor on a wafer. The method can comprise: forming a doped emitter contact layer 31 on a substrate 30; forming a doped emitter layer 32 on top of the emitter contact layer, the emitter layer doped same conductivity type as the emitter contact layer; forming a doped base epilayer 34 on top of the emitter layer, the base epilayer doped conductivity type opposite of the emitter layer; forming a doped collector epilayer 36, the collector epilayer doped conductivity type opposite of the base layer to form the bipolar transistor; forming an collector contact 38 on top of the collector layer; forming a base contact 40 on top of the base layer; forming a emitter contact 44 on top of the emitter contact layer; and selective etching the emitter layer to produce an undercut 45 beneath the base layer.
    Type: Grant
    Filed: October 7, 1994
    Date of Patent: July 18, 1995
    Assignee: Texas Instruments Incorporated
    Inventors: Darrell Hill, Shou-Kong Fan, Ali Khatibzadeh
  • Patent number: 5352327
    Abstract: Wafer surface degradation in a photoexcitation dry cleaning process, due to volatilization of surface halides that allows the exposed silicon surface to be further etched, is obviated by controlling the conditions of the process, specifically silicon wafer surface temperature, such that silicon reaction products that are formed on the surface of the wafer in the presence of the photoexcited disassociated halogen radicals do not volatilize. The silicon wafer is placed upon a low temperature chuck. When the halogen gas within the reaction chamber is irradiated with ultraviolet light, it produces disassociated halogen atoms that react with the surface of said silicon. Irradiation of the halogen gas and the surface of the silicon wafer is controlled by an optical shutter, in order to limit the amount of ultraviolet radiation that strikes and is absorbed by the wafer.
    Type: Grant
    Filed: July 10, 1992
    Date of Patent: October 4, 1994
    Assignee: Harris Corporation
    Inventor: Robert Witowski
  • Patent number: 5346851
    Abstract: A quantum effect device implementation of the Shannon Decomposition Function in the form of a Shannon Cell is provided in which a first quantum dot logic unit (50) is coupled between the X input and the output of the Shannon Cell. A second quantum dot logic unit (52) is coupled between the Y input and the output of the Shannon Cell. The control input to the Shannon Cell is coupled to both the first and second quantum dot logic units (50 and 52) such that current flows through the appropriate quantum dot logic unit (50 or 52) depending upon the logic state of the control input.
    Type: Grant
    Filed: November 20, 1992
    Date of Patent: September 13, 1994
    Assignee: Texas Instruments Incorporated
    Inventors: John N. Randall, Gary A. Frazier, Rajni J. Aggarwal
  • Patent number: 5316979
    Abstract: A reactive ion etching process is used for the fabrication of submicron, single crystal silicon, movable mechanical structures and capacitive actuators. The reactive ion etching process gives excellent control of lateral dimensions while maintaining a large vertical depth in the formation of high aspect-ratio freely suspended single crystal silicon structures. The silicon etch process is independent of crystal orientation and produces controllable vertical profiles.
    Type: Grant
    Filed: March 29, 1993
    Date of Patent: May 31, 1994
    Assignee: Cornell Research Foundation, Inc.
    Inventors: Noel C. MacDonald, Zuoying L. Zhang
  • Patent number: 5314837
    Abstract: The process of making a registration mark on an integrated-circuit substrate wherein photoimaging first is used to define an optically-recognizable mark on a predetermined position of the substrate, and the substrate then is covered with silicon dioxide. Photoresist then is applied over the substrate and selectively removed except over the mark. Etchant then is applied to remove all silicon dioxide except over the photoresist-covered mark. An epitaxial layer thereafter is grown over the substrate. The silicon dioxide over the mark prevents epitaxial growth in that region, so that the mark remains clear and optically visible for the rest of the IC processing.
    Type: Grant
    Filed: June 8, 1992
    Date of Patent: May 24, 1994
    Assignee: Analog Devices, Incorporated
    Inventors: Herbert J. Barber, Pamela A. Mayernik
  • Patent number: 5294568
    Abstract: A method of selective etching of native oxide on a substrate is disclosed in which hydrogen halide vapor and water vapor are exposed to the substrate surface under appropriate conditions and long enough to remove native oxide but not long enough to remove any significant amount of other oxides. Treating conditions are maintained to prevent water vapor from condensing on the substrate until sufficient native oxide is etched so that substantially all the native oxide will be etched before appreciable other oxides are etched.
    Type: Grant
    Filed: April 10, 1992
    Date of Patent: March 15, 1994
    Assignee: Genus, Inc.
    Inventors: Michael A. McNeilly, Bruce E. Deal, Dah-Bin Kao, John de Larios
  • Patent number: 5266516
    Abstract: A new method to produce a contact or via opening and filled metallurgy for integrated circuits. An insulating layer structure is formed over semiconductor device structures. A resist mask with substantially vertical sided openings is formed in the mask over the insulating layer and above the device elements to be electrically contacted. These device elements can be, for example source/drain regions in the semiconductor substrate, a metallurgy layer interconnecting other device element and the like. The exposed insulating layer is isotropically etched to a depth of between about 500 to 850 Angstroms to form a break in the vertical sided opening under construction. The exposed insulating layer is anisotropically etched to complete the construction of the substantially vertical sided openings through the insulating layer to a device element to be electrically contacted.
    Type: Grant
    Filed: January 2, 1992
    Date of Patent: November 30, 1993
    Assignee: Chartered Semiconductor Manufacturing Pte Ltd
    Inventor: Bernard W. K. Ho
  • Patent number: 5232868
    Abstract: A method for forming a thin semiconductor film comprises the steps of supplying on a surface of a heated substrate a first material gas composed of germanium halide or germanium hydro-fluoride obtained by partially substituting fluorine of the germanium fluoride together with a second material gas composed of silicon hydride or silicon fluoro-hydride obtained by partially substituting hydrogen of the silicon hydride with fluorine and causing a chemical reaction between the first and second material gases, thereby growing a thin film containing germanium over the surface of the substrate. By controlling the substrate temperature or flow rate ratio of the first material gas to the second material gas, an optical gap of the thin film grown can be controlled.
    Type: Grant
    Filed: August 5, 1991
    Date of Patent: August 3, 1993
    Assignee: Agency of Industrial Science and Technology
    Inventors: Yutaka Hayashi, Mitsuyuki Yamanaka
  • Patent number: 5223457
    Abstract: A plasma process apparatus capable of operation significantly above 13.56 MHz can produce reduced self-bias voltage of the powered electrode to enable softer processes that do not damage thin layers that are increasingly becoming common in high speed and high density integrated circuits. A nonconventional match network is used to enable elimination of reflections at these higher frequencies. Automatic control of match network components enables the rf frequency to be adjusted to ignite the plasma and then to operate at a variable frequency selected to minimize process time without significant damage to the integrated circuit.
    Type: Grant
    Filed: October 11, 1991
    Date of Patent: June 29, 1993
    Assignee: Applied Materials, Inc.
    Inventors: Donald M. Mintz, Hiroji Hanawa, Sasson Someskh, Dan Maydan
  • Patent number: 5198390
    Abstract: A reactive ion etching process is used for the fabrication of submicron, single crystal silicon, movable mechanical structures and capacitive actuators. The reactive ion etching process gives excellent control of lateral dimensions while maintaining a large vertical depth in the formation of high aspect-ratio freely suspended single crystal silicon structures. The silicon etch process is independent of crystal orientation and produces controllable vertical profiles.
    Type: Grant
    Filed: January 16, 1992
    Date of Patent: March 30, 1993
    Assignee: Cornell Research Foundation, Inc.
    Inventors: Noel C. MacDonald, Zuoying L. Zhang
  • Patent number: 5182234
    Abstract: A dopant-opaque layer of polysilicon is deposited on gate oxide on the upper substrate surface to serve as a pattern definer during fabrication of the device. It provides control over successive P and N doping steps used to create the necessary operative junctions within a silicon substrate and the conductive structures formed atop the substrate. A trench is formed in the upper silicon surface and a source conductive layer is deposited to electrically contact the source region as a gate conductive layer is deposited atop the gate oxide layer. The trench sidewall is profile tailored using a novel O.sub.2 -SF.sub.6 plasma etch technique. An oxide sidewall spacer is formed on the sides of the pattern definer and gate oxide structures, before depositing the conductive material. A planarizing layer is applied and used as a mask for selectively removing any conductive material deposited atop the oxide spacer.
    Type: Grant
    Filed: July 26, 1991
    Date of Patent: January 26, 1993
    Assignee: Advanced Power Technology, Inc.
    Inventor: Theodore O. Meyer
  • Patent number: 5157000
    Abstract: A process is disclosed through which vias (50) can be formed by the reaction of an etchant species (52) with a mercury cadmium telluride (HgCdTe) or zinc sulfide (ZnS) layer (42). The activating gases (20) are preferably a hydrogen gas or a methane gas which is excited in a diode plasma reactor (100) which has an RF power source (13) applied to one of two parallel electrodes. The etching occurs in selected areas in a photoresist pattern (44) residing over the ZnS or HgCdTe layer (42). Wet etching the layer (42) with a wet etchant (54) following the dry etching, improves the via (50) by making the walls (48) smoother, and allowing for expansion of the vias (50) to a dimension necessary for proper operation of a HgCdTe-based infrared detector.
    Type: Grant
    Filed: February 8, 1991
    Date of Patent: October 20, 1992
    Assignee: Texas Instruments Incorporated
    Inventors: Jerome L. Elkind, Patricia B. Smith, Larry D. Hutchins, Joseph D. Luttmer, Rudy L. York, Julie S. England
  • Patent number: 5137847
    Abstract: A method of producing a GaAs single crystal substrate comprises the steps of conducting a first-stage annealing by vacuum-sealing a GaAs single crystal wafer and arsenic in a heat-resistant vessel and heating the wafer to a temperature of 1050.degree. to 1150.degree. C. while exposing it to arsenic vapor pressure, cooling the wafer to room temperature at a cooling rate of 1.degree.-25.degree. C./min., removing the wafer from the vessel, etching the wafer and placing it in another vessel, conducting a second-stage annealing by heating the wafer to a temperature of 910.degree. to 1050.degree. C. in a non-oxidizing atmosphere, cooling the wafer to room temperature at a cooling rate of 1.degree.-25.degree. C./min., removing it from the vessel, etching the wafer, conducting a third-stage annealing by vacuum-sealing the wafer and arsenic in the heat-resistant vessel and heating the wafer to a temperature of 520.degree.-730.degree. C. while exposing it to arsenic vapor, and cooling the wafer at least down to 400.
    Type: Grant
    Filed: December 12, 1991
    Date of Patent: August 11, 1992
    Assignee: Nippon Mining Co., Ltd.
    Inventors: Haruhito Shimakura, Manabu Kanou
  • Patent number: 5134090
    Abstract: A method of producing patterned epitaxial silicon films and devices fabricated thereby is described. The method forms a first layer of a refractory material on a substrate and pattern delineates the first layer. Silicon is then deposited at a temperature within the range between 400 degrees C. and 700 degrees C. and the polycrystalline material that forms is removed.
    Type: Grant
    Filed: June 12, 1989
    Date of Patent: July 28, 1992
    Assignee: AT&T Bell Laboratories
    Inventors: John C. Bean, George A. Rozgonyi
  • Patent number: 5122481
    Abstract: There is disclosed a method of manufacturing a semiconductor device comprising the steps of: forming a semiconductor element on one of major surfaces of a GaAs substrate; a grinding the substrate to make the GaAs substrate to a predetermined thickness by grinding the other surface of the GaAs substrate with a grinding stone having an average grain size of 6 micro-meters or larger; and an chemical etching the other surface of the substrate by 0.6 micro-meters or more just after the grinding step, without any further grinding treatment done on the other surface, just after the grinding step.
    Type: Grant
    Filed: September 4, 1991
    Date of Patent: June 16, 1992
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Masanori Nishiguchi
  • Patent number: 5110765
    Abstract: A solution of H.sub.2 O.sub.2 and EDTA selectively etches GaAs-containing Group III-V compounds in the presence of other Group III-V compounds. Illustratively, Al.sub.y Ga.sub.1-y As (y.ltoreq.0) is selectively etched in the presence of Al.sub.x Ga.sub.1-x As(x>y), and InGaAs is selectively etched in the presence of either InAlAs or InP.
    Type: Grant
    Filed: November 30, 1990
    Date of Patent: May 5, 1992
    Assignee: AT&T Bell Laboratories
    Inventors: Jaya Bilakanti, Edward J. Laskowski
  • Patent number: 5096854
    Abstract: The present invention relates to a method for polishing a silicon wafer. The method comprises the steps of: (a) supplying a polishing fluid to a polishing surface, the polishing fluid including an alkaline fluid and polishing particles of high-purity silica dispersed in the alkaline fluid, the polishing surface being planar; (b) bringing a silicon wafer in contact with the polishing surface; and (c) moving at least one of the silicon wafer and the polishing surface relative to the other, thereby polishing the silicon wafer. The method is characterized by the following: the polishing surface is made of a ceramic material harder than the silicon wafer and more resistant to mechanochemical polishing than silicon, and the maximum roughness of the ceramic is less than 0.02 .mu.m.
    Type: Grant
    Filed: June 19, 1989
    Date of Patent: March 17, 1992
    Assignees: Japan Silicon Co., Ltd., Sony Corporation
    Inventors: Yuichi Saito, Shinsuke Sakai, Hisao Hayashi, Takeshi Matsushita
  • Patent number: 5093278
    Abstract: According to this invention, a first cladding layer of a first conductivity type, an active layer, a second cladding layer of a second conductivity type, and a cap layer much more susceptible to side etching than the second cladding layer susceptible to side etching than the second cladding layer are sequentially grown on a (100) crystal plane of a semiconductor substrate of the first conductivity type, and a stripe-like mask extending in a <011> direction is formed on the grown substrate with respect to each layer of the stacked substrate. This etching is performed in a crystal orientation for forming a reverse triangular mesa. However, since the cap layer is made of a material susceptible to side etching, a rounded mesa is formed. Thereafter, when a burying layer is formed on the etched portion by a vapor phase epitaxy method, the burying layer can be made to have a flat surface depending on crystal orientations.
    Type: Grant
    Filed: September 21, 1990
    Date of Patent: March 3, 1992
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Hidenori Kamei
  • Patent number: 5084419
    Abstract: A method of manufacturing a semiconductor device in which a portion of a monocrystalline silicon layer protruded from a surface of an insulating member is polished up to the surface by a chemical-mechanical polishing is disclosed. A polycrystalline silicon layer and a leveling material are formed in sequence on the protruded portion of the monocrystalline silicon layer and on an exposed part of the surface of the insulating member, and a reactive ion etching and the chemical-mechanical polishing are carried out.
    Type: Grant
    Filed: March 23, 1989
    Date of Patent: January 28, 1992
    Assignee: NEC Corporation
    Inventor: Masato Sakao
  • Patent number: 5075256
    Abstract: A method and apparatus are disclosed for removing one or more materials deposited on the backside and end edges of a semiconductor wafer which comprises urging the front side of the wafer against a faceplate in a vacuum chamber; flowing one or more gases through a space maintained between the front side of the wafer and the faceplate; and forming a plasma in a gap maintained between the backside of the wafer and susceptor to remove materials deposited on the backside and end edge of the wafer; the gas flowing through the space between the front side of the wafer and the faceplate acting to prevent the plasma from removing materials on the front side of the wafer.
    Type: Grant
    Filed: August 25, 1989
    Date of Patent: December 24, 1991
    Assignee: Applied Materials, Inc.
    Inventors: David N. Wang, Lawrence C. Lei, Mei Chang, Cissy Leung
  • Patent number: 5045503
    Abstract: A microwave monolithic integrated circuit comprising a GaAs substrate having upper and lower opposed surfaces, an active region and at least one passive region produced on the upper surface of the substrate, and a heat sink produced on the lower surface of the substrate, wherein the substrate thickness beneath the active region is smaller than the substrate thickness beneath at least one passive region, thereby disposing the heat sink near the active region to improve heat dissipation therefrom. The active region and the passive regions are separated by intermediate areas and the substrate thickness beneath the intermediate areas is smaller than the substrate thickness beneath the active region such that the heat sink at least partially surrounds the substrate beneath the active region.
    Type: Grant
    Filed: June 26, 1990
    Date of Patent: September 3, 1991
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Michihiro Kobiki, Masahiro Yoshida, Takahide Ishikawa
  • Patent number: 5043299
    Abstract: An improved process for the selective deposition of tungsten on a masked semiconductor wafer is disclosed which comprises cleaning the surfaces of the wafer in an air-tight cleaning chamber, then transferring the cleaned wafer to a vacuum deposition chamber such as a CVD chamber for selective deposition of tungsten thereon without exposing the cleaned wafer to conditions which would recontaminate the cleaned wafer prior to said deposition, and then selectively depositing tungsten on the unmasked surfaces of the cleaned wafer.
    Type: Grant
    Filed: December 1, 1989
    Date of Patent: August 27, 1991
    Assignee: Applied Materials, Inc.
    Inventors: Mei Chang, David N. Wang
  • Patent number: 5030590
    Abstract: The invention comprises an improvement in the process wherein a polysilicon layer, which is formed over a step on an integrated circuit structure and masked with a photoresist, is anisotropically etched to remove the exposed portions of the polysilicon layer leaving residues of polysilicon adjacent to the step and residues of a polymerized silicon/oxide-containing material adjacent the sidewalls of the masked portions of the polysilicon layer. The improvement comprises treating the integrated circuit substrate with a dilute hydroxide solution to remove both the polysilicon residues and the residues of polymerized silicon/oxide-containing material.
    Type: Grant
    Filed: June 9, 1989
    Date of Patent: July 9, 1991
    Assignee: Applied Materials, Inc.
    Inventors: Zahra H. Amini, Ian S. Latchford
  • Patent number: 5023197
    Abstract: A method for manufacturing a MOS transistor formed in a silicon block on insulator with convex rounded up edges, initially consisting in etching the block in a thin layer of silicon on insulator (SOI). In this method etching of the block comprises the following steps: forming at the position where it is desired to obtain the block a mask layer portion (3) having a thickness slightly higher than that of the SOI; depositing a second silicon layer (11) having a predetermined thickness; and anisotropically etching silicon until said insulator is apparent outside the mask layer portion.
    Type: Grant
    Filed: August 15, 1990
    Date of Patent: June 11, 1991
    Assignee: French State represented by the Minister of Post, Telecommunications and Space
    Inventors: Michel Haond, Jean Galvier
  • Patent number: 5023203
    Abstract: A method for reducing the line widths produced by patterning a semiconduc substrate with a multilayer resist mask employs a `spacer`-forming oxide layer which is non-selectively formed over the mask structure after an aperture for exposing a lower resist layer has been formed in an upper portion of the multilayer mask, but prior to etching a lower resist layer. The oxide layer is subjected to a dry systemic etch to vertically remove material of the oxide layer down to the surface of the lower resist layer. Because of the substantial step coverage of the oxide layer, a `spacer` or `stringer` portion remains along the sidewalls of the original aperture in the upper portion of the mask, whereby the dimensions of the exposure window are reduced. Retaining this sidewall spacer as an integral part of mask structure permits narrower line widths to be replicated in the underlying substrate.
    Type: Grant
    Filed: June 23, 1989
    Date of Patent: June 11, 1991
    Assignee: Korea Electronics & Telecommunications Research Institute et al.
    Inventor: Sangsoo Choi
  • Patent number: 5017511
    Abstract: A process is disclosed through which vias (50) can be formed by the reaction of an etchant species (52) with a mercury cadmium telluride (HgCdTe) or zinc sulfide (ZnS) layer (42). The activating gases (20) are preferably a hydrogen gas or a methane gas which is excited in a diode plasma reactor (100) which has an RF power source (13) applied to one of two parallel electrodes. The etching occurs in selected areas in a photoresist pattern (44) residing over the ZnS or HgCdTe layer (42). Wet etching the layer (42) with a wet etchant (54) following the dry etching, improves the via (50) by making the walls (48) smoother, and allowing for expansion of the vias (50) to a dimension necessary for proper operation of a HgCdTe-based infrared detector.
    Type: Grant
    Filed: July 10, 1989
    Date of Patent: May 21, 1991
    Assignee: Texas Instruments Incorporated
    Inventors: Jerome L. Elkind, Patricia B. Smith, Larry D. Hutchins, Joseph D. Luttmer, Rudy L. York, Julie S. England
  • Patent number: 5001080
    Abstract: A semiconductor device including a substrate having a low substrate surface formed in the substrate with a first gentle slope from the substrate surface; a single crystalline layer formed on the low substrate surface nearly level with the substrate surface and having a gentle slope facing the first gentle slope; an optical semiconductor element is constructed using the single crystalline layer. An electronic semiconductor element is constructed using the substrate surface. A wiring layer connects electrodes of the optical semiconductor element and the electronic semiconductor element through the first and the second gentle slopes.
    Type: Grant
    Filed: October 26, 1987
    Date of Patent: March 19, 1991
    Assignee: Fujitsu Limited of 1015
    Inventors: Osamu Wada, Tatsuyuki Sanada, Shuichi Miura, Hideki Machida, Shigenobu Yamakoshi, Teruo Sakurai
  • Patent number: 4988644
    Abstract: An apparatus and a method for the etching of semiconductor materials is disclosed. The apparatus includes a process chamber which includes a plasma generator remote from and in fluid communication with the process chamber. The remote plasma generator includes an inlet tube, a discharge tube in fluid communication with the inlet tube, an excitation cavity surrounding the discharge tube, an outlet tube in fluid communication with the discharge tube and a process chamber, and an injection tube in the outlet tube.
    Type: Grant
    Filed: May 23, 1989
    Date of Patent: January 29, 1991
    Assignee: Texas Instruments Incorporated
    Inventors: Rhett B. Jucha, Cecil J. Davis, Steve S. Huang, Lee M. Loewenstein, Jeff D. Achenbach
  • Patent number: 4983540
    Abstract: An ion beam (113) focused into a diameter of at most 0.1 .mu.m bombards substantially perpendicularly to the superlattice layers of a one-dimensional superlattice structure and is scanned rectilinearly in a direction of the superlattice layers so as to form at least two parallel grooves (108, 109, 110, 111) or at least two parallel impurity-implanted parts (2109) as potential barrier layers, whereby a device of two-dimensional superlattice structure can be manufactured. At least two parallel grooves (114, 115, 116, 117) or impurity-implanted parts are further formed orthogonally to the potential barrier layers of the two-dimensional superlattice structure, whereby a device of three-dimensional superlattice structure can be manufactured. In addition, deposition parts (2403, 2404, 2405) may well be provided by further depositing an insulator into the grooves (108, 109, 110, 111, 114, 115, 116, 117) which are formed by the scanning of the ion beam.
    Type: Grant
    Filed: November 18, 1988
    Date of Patent: January 8, 1991
    Assignee: Hitachi, Ltd.
    Inventors: Hiroshi Yamaguchi, Keiya Saito, Fumikazu Itoh, Koji Ishida, Shinji Sakano, Masao Tamura, Shoji Shukuri, Tohru Ishitani, Tsuneo Ichiguchi
  • Patent number: 4980317
    Abstract: Disclosed is a method of producing an integrated semiconductor structure, comprising components with dimensions in the submicron range, wherein a three-layer resist system is used to produce a polymer or resist mask. The polymer or resist mask thus produced is used to etch a layer of polysilicon on the semiconductor substrate. The method is characterized in that the pattern, produced conventionally in the top layer of the three-layer resist and including an angle < about 90.degree., is transferred by RIE, using CF.sub.4, to the center layer of plasma nitride and by RIE, using oxygen, to the bottom resist or polymer layer. In a prior art method, this was followed by lateral etching in oxygen to reduce the dimensions of the mask by a desired amount.
    Type: Grant
    Filed: March 21, 1989
    Date of Patent: December 25, 1990
    Assignee: International Business Machines Corporation
    Inventors: Otto Koblinger, Reinhold Muhl, Hans-Joachim Trumpp
  • Patent number: 4962057
    Abstract: In situ evaporation of selected surface regions or layers of compound semiconductors is accomplished without breaking the growth system environment employing photo induced evaporation enhancement in chemical vapor deposition epitaxy. Intense radiation from an energy source desorbs or causes evaporation of consecutive monolayers of atoms or combined atoms from the surface crystal by thermal evaporation. The desorbed atoms from the growth surface are removed atomic layer by atomic layer in a fairly uniform and systematic manner and may be characterized as "monolayer peeling" resulting in a morphology that is sculpturally smooth and molecularly continuous. In this sense, the method of this invention is analogous to erasing or the etching of crystal material and is the antithesis to laser deposition patterning wherein erasure after growth or reduced rate of growth during growth provide "negative growth patterning".
    Type: Grant
    Filed: October 13, 1988
    Date of Patent: October 9, 1990
    Assignee: Xerox Corporation
    Inventors: John E. Epler, David W. Treat, Thomas L. Paoli
  • Patent number: 4962064
    Abstract: A method is disclosed for making a highly planarized integrated circuit structure having deposited oxide portions planarized to the level of adjacent portions of the integrated circuit structure which comprises: deposition, over an integrated circuit structure having first portions at a height higher than the remainder of the integrated circuit structure, a conformal oxide layer; depositing a layer of a planarizing material such as polysilicon over the conformal oxide layer; polishing the structure a first time to expose the highest portions of the underlying conformal oxide layer; etching the structure a first time with an etchant system capable of removing the conformal oxide preferentially to the planarizing material; further polishing the structure a second time to remove planarizing material left from the first etching step; and then optionally etching the remainder of the structure to remove any remaining planarizing material and the remaining conformal oxide over the raised portions of the underlying i
    Type: Grant
    Filed: May 12, 1988
    Date of Patent: October 9, 1990
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Jacob D. Haskell, Craig S. Sander, Steven C. Avanzino, Subhash Gupta
  • Patent number: 4956312
    Abstract: A method of manufacturing a semiconductor device is described in which electrical contact is provided to an area (10) of an electrically conductive level (1) exposed through an opening (2) in a covering layer (3). A further layer is provided over the covering layer (3) as a first layer (4) of one material provided to a first thickness on the covering layer (3) and a second layer (5) of a different material provided to a second thickness on the first layer.
    Type: Grant
    Filed: May 19, 1989
    Date of Patent: September 11, 1990
    Assignee: U.S. Philips Corporation
    Inventor: Josephus M. F. G. Van Laarhoven
  • Patent number: 4954459
    Abstract: A method is disclosed for making a highly planarized integrated circuit structure having deposited oxide portions planarized to the level of adjacent portions of the integrated circuit structure which comprises: depositing, over an integrated circuit structure having first portions at a height higher than the remainder of the integrated circuit structure, a conformal oxide layer having a thickness which exceeds the height of said first portions above the remainder of the integrated circuit structure; forming a patterned mask layer over said deposited oxide layer with one or more openings therein in registry with the higher height first portions of the integrated circuit structure; etching exposed portions of said conformal oxide layer through the mask openings down to a level approximately equal to the level of the unexposed portion of the conformal oxide layer; removing the mask layer; and polishing the oxide layer to remove raised portions of the conformal oxide layer remaining after the etching step to for
    Type: Grant
    Filed: July 3, 1989
    Date of Patent: September 4, 1990
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Steven C. Avanzino, Jacob D. Haskell