Gallium Arsenide Patents (Class 148/DIG56)
  • Patent number: 5882950
    Abstract: A fabrication method for a horizontal direction semiconductor PN junction array which can be achieved when an epitaxial layer is grown by a metalorganic chemical vapor deposition (MOCVD method) by introducing (or doping) a small amount of CCl.sub.4 or CBr.sub.4 gas, includes forming a recess on an N type GaAs substrate by using a non-planar growth, performing a growth method of a P type epitaxial layer on the N type GaAs substrate by a metalorganic chemical vapor deposition method, and forming a horizontal direction PN junction array of P-GaAs/N-GaAs or P-AlGaAs/N-GaAs by introducing a gas comprising CCl.sub.4 or CBr.sub.4 .
    Type: Grant
    Filed: December 27, 1996
    Date of Patent: March 16, 1999
    Assignee: Korea Institute Of Science And Technology
    Inventors: Suk-Ki Min, Seong-Il Kim, Eun Kyu Kim
  • Patent number: 5801071
    Abstract: A semiconductor laser diode apparatus has a substrate of a first conduction type, a first clad layer of the first conduction type which is formed on the substrate, a current block layer which is formed on the first clad layer, a V groove stripe which is formed in a vertical direction so that a tip of the V groove can arrive at the first clad layer in depth, an active layer which is formed on the first clad layer and the current block layer along the V groove stripe without a low resistance layer, a second clad layer of a second conduction type which is formed on the active layer, a contact layer of the second conduction type which is formed on the second clad layer, a first electrode which is formed on a surface of the substrate which is reverse side of a surface on which the first clad layer is formed and a second electrode which is formed oil a surface of the contact layer. Therefore a low threshold current level can be achieved.
    Type: Grant
    Filed: July 9, 1996
    Date of Patent: September 1, 1998
    Assignee: Ricoh Company, Ltd.
    Inventor: Takashi Takahashi
  • Patent number: 5294557
    Abstract: A method for ion-implanting a dopant species in semiconductors includes the steps of implanting a dopant species in a semiconductor material at a predetermined rate, the predetermined rate being based on a rate corresponding to a maximum in a characteristic graph of percent activation as a function of dopant species implantation rate; and annealing the dopant implanted semiconductor.
    Type: Grant
    Filed: August 26, 1991
    Date of Patent: March 15, 1994
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Frederick G. Moore, Harry B. Dietrich
  • Patent number: 5229319
    Abstract: Disclosed is a method of selective chemical vapor deposition for selectively forming thin films of a semiconductor, dielectric or metal on a semiconductor by providing a mask of SiO.sub.2 having a plurality of openings in various forms on the substrate, wherein a trimethyl gallium (TMG) gas as a Group III material, 10% hydrogen-based arsine (AsH.sub.3) gas as a Group V material, and 500 ppm hydrogen-based disilane (Si.sub.2 H.sub.6) gas as an n-type impurity material are alternately supplied onto the substrate, and each supply amount of the material gases is controlled at a value to obtain a film growth rate for forming the corresponding monoatomic layer or monomolecular layer to each material at each opening. Also disclosed is an apparatus for performing the above-disclosed method of chemical vapor deposition, wherein four reaction chambers are included, and the material gases are supplied to the respective reaction chambers in accordance with the following gas supply sequences: Chamber 1: TMG+H.sub.2 /H.
    Type: Grant
    Filed: November 28, 1990
    Date of Patent: July 20, 1993
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshito Kawakyu, Hironori Ishikawa, Masahiro Sasaki, Masao Mashita
  • Patent number: 5228927
    Abstract: A heat-treating method for an indium-doped dislocation-free gallium arsenide monocrystal having a low carbon concentration and grown in the Liquid Encapsulated Czochralski method, comprising a two-step heat treatment:(i) heating the monocrystal at a temperature between 1050.degree. C. and 1200.degree. C. for a predetermined time length, and cooling the monocrystal quickly; and(ii) heating the monocrystal at a temperature between 750.degree. C. and 950.degree. C. for a predetermined time length, and cooling the monocrystal quickly.
    Type: Grant
    Filed: March 29, 1991
    Date of Patent: July 20, 1993
    Assignee: Shin-Etsu Handotai Company Limited
    Inventors: Yutaka Kitagawara, Susumu Kuwahara, Takao Takenaka
  • Patent number: 5185273
    Abstract: A method is provided for correlating ion implantation from a silicon wafer (13) to a gallium arsenide wafer. A first dose of a predetermined amount of silicon ions is implanted into a silicon wafer (13). The first dose of the implanted silicon ions in the silicon wafer (13) is evaluated by a measuring system (10) that monitors a modulated reflected signal from the silicon wafer (13) and quantifies the signal as to the number of implanted silicon ions in the silicon wafer. If the measured quantity of implanted silicon ions is a desired amount of implanted silicon ions the same number of silicon ions is then implanted into the gallium arsenide wafer.
    Type: Grant
    Filed: September 30, 1991
    Date of Patent: February 9, 1993
    Assignee: Motorola, Inc.
    Inventor: Craig L. Jasper
  • Patent number: 5173443
    Abstract: Methods are disclosed for making semiconductor windows which are transparent to light in the infrared range which have good electrical conductivity and are formed of a substrate material (11) having a semiconductor coating (14) having a dopant included therein. The coating is diffused, grown or deposited on one surface of the substrate and is controlled to obtain both low electrical resistivity and high infrared transmissivity. The coating can be formed of the same material as the substrate or can be a different material. Windows having particular thermal properties are formed utilizing zinc selenide and zinc sulfide as the substrate.
    Type: Grant
    Filed: June 27, 1990
    Date of Patent: December 22, 1992
    Assignee: Northrop Corporation
    Inventors: V. Warren Biricik, James M. Rowe, Paul Kraatz, John W. Tully, Wesley J. Thompson, Rudolph W. Modster
  • Patent number: 5137847
    Abstract: A method of producing a GaAs single crystal substrate comprises the steps of conducting a first-stage annealing by vacuum-sealing a GaAs single crystal wafer and arsenic in a heat-resistant vessel and heating the wafer to a temperature of 1050.degree. to 1150.degree. C. while exposing it to arsenic vapor pressure, cooling the wafer to room temperature at a cooling rate of 1.degree.-25.degree. C./min., removing the wafer from the vessel, etching the wafer and placing it in another vessel, conducting a second-stage annealing by heating the wafer to a temperature of 910.degree. to 1050.degree. C. in a non-oxidizing atmosphere, cooling the wafer to room temperature at a cooling rate of 1.degree.-25.degree. C./min., removing it from the vessel, etching the wafer, conducting a third-stage annealing by vacuum-sealing the wafer and arsenic in the heat-resistant vessel and heating the wafer to a temperature of 520.degree.-730.degree. C. while exposing it to arsenic vapor, and cooling the wafer at least down to 400.
    Type: Grant
    Filed: December 12, 1991
    Date of Patent: August 11, 1992
    Assignee: Nippon Mining Co., Ltd.
    Inventors: Haruhito Shimakura, Manabu Kanou
  • Patent number: 5124278
    Abstract: The present invention addresses the use of metalorganic amines as metallic donor source compounds in reactive deposition applications. More specifically, the present invention addresses the use of the amino-substituted metallic donor source compounds M(NR.sub.2).sub.3-x H.sub.x, where R is organic, alkyl or fluoroalkyl, and x is less than or equal to 2, and M=As, Sb or P, in processes requiring deposition of the corresponding element. These uses include a number of different processes; the metalorganic vapor phase epitaxy of compound semiconductor material such as GaAs, InP, AlGaAs, etc.; doping of SiO.sub.2 or borosilicate based glasses to enhance the reflow properties of the glass; in-situ n-type doping of silicon epitaxial material; sourcing of arsenic or phosphorus for ion implantation; chemical beam epitaxy (or MOMBE); and diffusion doping into electronic materials such as silicon dioxide, silicon and polycrystalline silcon.
    Type: Grant
    Filed: September 21, 1990
    Date of Patent: June 23, 1992
    Assignee: Air Products and Chemicals, Inc.
    Inventors: David A. Bohling, Gregory T. Muhr, Sherri L. Bassner
  • Patent number: 5118642
    Abstract: A reactant gas is fed to a dispersing chamber which is disposed under a reaction chamber, and both disposed within a vacuum chamber. The reactant gas is dispersed and then fed through a plurality of communicating holes to the reaction chamber. A second reactant gas is fed to a lower dispersing chamber. After dispersion, this second gas is fed through pipes through the first dispersing chamber and into the reaction chamber around the first reaction gas. Said first reactant gas is blown off downward from the end opening of the feeding pipe and dispersed in parallel along the collar portion and dispersed homogeneously in the first reactant gas dispersing chamber, and in the state, is introduced to the reaction chamber via communicating holes.
    Type: Grant
    Filed: January 24, 1991
    Date of Patent: June 2, 1992
    Assignee: Daidousanso Co., Ltd.
    Inventors: Akira Yoshino, Kenji Okumura, Yoshinori Ohmori, Toshiharu Ohnishi
  • Patent number: 5110751
    Abstract: A first semiconductor layer, a second semiconductor layer for source and drain regions, and a bottom SiN layer are successively formed. After the bottom SiN layer is selectively etched to make an opening, a SiON layer and a top SiN layer are formed thereon. A resist pattern having an opening that is closer to the source region than to the drain region is formed on the top SiN layer. The top SiN layer and SiON layer are etched with the resist pattern used as a mask, to expose the second semiconductor layer. The SiON layer is side-etched with hydrofluoric acid until exposing the gate-side portion of the source-side bottom SiN layer. Then, the second semiconductor layer is etched to expose the first semiconductor layer and to form the source and drain regions, where the gate-side edge of the source region is determined by that of the source-side bottom SiN layer and the gate-side edge of the drain region is determined by that of the drain-side SiON layer.
    Type: Grant
    Filed: February 20, 1991
    Date of Patent: May 5, 1992
    Assignee: Rohm Co., Ltd.
    Inventor: Yoshikazu Nakagawa
  • Patent number: 5091338
    Abstract: This invention comprises a Pd layer formed on an n-type GaAs semiconductor crystals, and a Ge layer being formed on the Pd layer, characterized in that the thickness of the Pd layer is between 300 .ANG. and 1500 .ANG. and the thickness of the Ge layer is between 500 .ANG. and 1500 .ANG..In addition, this invention provides an ohmic electrode forming process for compound semiconductor crystals for forming an ohmic electrode on an n-type GaAs semiconductor crystal, comprising a first layer forming step for forming a palladium (pd) layer on a compound semiconductor crystal; a second layer forming step for forming a germanium layer (Ge) on the Pd layer; and an annealing step for annealing the Pd layer and the Ge layer by a rapid thermal annealing treatment.The Pd layer is formed between 300 .ANG. and 1500 .ANG. in the first layer forming step; the Ge layer is between 500 .ANG. and 1500 .ANG.
    Type: Grant
    Filed: April 23, 1990
    Date of Patent: February 25, 1992
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Junichi Tsuchimoto, Tooru Yamada, Takaya Miyano
  • Patent number: 5021365
    Abstract: Control of the Fermi level pinning problem and the production of flat band surface performance in compound semiconductors is achieved by providing a cationic oxide free of anionic species on the surface of the semiconductor for flat band performance and with a localized inclusion of some anionic species for barrier performance so that oxide and metal work function responsiveness is available in structure and performance in MOSFET, MESFET and different work function metal FET structures. A cationic gallium oxide is produced on GaAs by oxide growth during illumination and while being rinsed with oxygenated water. The oxidation is used to produce both anionic and cationic species while the rinsing process selectively removes all the anionic species.
    Type: Grant
    Filed: March 13, 1989
    Date of Patent: June 4, 1991
    Assignee: International Business Machines Corporation
    Inventors: Peter D. Kirchner, Alan C. Warren, Jerry M. Woodall, Steven L. Wright
  • Patent number: 4994408
    Abstract: A method for growing high quality epitaxial films using low pressure MOCVD that includes providing a substrate that is misoriented from a singular plane, placing the substrate into an MOCVD reactor at a total pressure of less than 0.2 atmospheres and then growing an epitaxial film on the substrate. When providing a misoriented gallium arsenide substrate, the MOCVD reactor is set at a temperature in the range of 650 to 750 degrees centigrade to grow an aluminum gallium arsenide film. This temperature is substantially lower than that at which aluminum gallium arsenide epitaxial films are commonly grown and the resulting film has a smooth surface morphology and enhanced photoluminesence properties.
    Type: Grant
    Filed: February 6, 1989
    Date of Patent: February 19, 1991
    Assignee: Motorola Inc.
    Inventor: Eric S. Johnson
  • Patent number: 4952527
    Abstract: A new III-IV buffer material is described which is produced by low temperature growth of III-V compounds by MBE that has unique and desirable properties, particularly for closely spaced, submicron gate length active III-V semiconductor devices, such as HEMT's, MESFET's and MISFET's. In the case of the III-V material, GaAs, the buffer is grown under arsenic stable growth conditions, at a growth rate of 1 micron/hour, and at a substrate temperature preferably in the range of 150 to about 300.degree. C. The new material is crystalline, highly resistive, optically inactive, and can be overgrown with high quality III-V active layers.
    Type: Grant
    Filed: February 19, 1988
    Date of Patent: August 28, 1990
    Assignee: Massachusetts Institute of Technology
    Inventors: Arthur R. Calawa, Frank W. Smith, Michael J. Manfra, Chang-Lee Chen
  • Patent number: 4952446
    Abstract: This invention relates to ultra-thin semiconductor films which can be in the submicron range formed from semiconductor materials such as silicon, germanium and gallium arsenide. The films are formed by creating a thin slightly damaged surface on the polished reverse side of a film (e.g., a wafer) of the semiconductor by low dose ion implantation and then etching the semiconductor material on the front side of the film to remove the semiconductor material down to the ion implanted damaged layer. While the implanted ions can be chosen from functionally desirable ions which upon annealing remain in the film to alter the original electrical characteristics, the implanted ions can also be chosen so that upon annealing, the resultant ultra-thin semiconductor film has the same electrical characteristics as the original semiconductor material.The ion implantation changes the etching characteristics of the ion implanted layer.
    Type: Grant
    Filed: December 14, 1988
    Date of Patent: August 28, 1990
    Assignee: Cornell Research Foundation, Inc.
    Inventors: Kevin C. Lee, Charles A. Lee, John Silcox
  • Patent number: 4946735
    Abstract: This invention relates to ultra-thin semiconductor films which can be in the submicron range formed from semiconductor materials such as silicon, germanium and gallium aresenide. The films are formed by creating a thin slightly damaged surface on the polished reverse side of a film (e.g., a wafer) of the semiconductor by low dose ion implantation and then etching the semiconductor material on the front side of the film to remove the semiconductor material down to the ion implanted damaged layer. While the implanted ions can be chosen from functionally desirable ions which upon annealing remain in the film to alter the original electrical characteristics, the implanted ions can also be chosen so that upon annealing, the resultant ultra-thin semiconductor film has the same electrical characteristics as the original semiconductor material.The ion implantation changes the etching characteristics of the ion implanted layer.
    Type: Grant
    Filed: December 14, 1988
    Date of Patent: August 7, 1990
    Assignee: Cornell Research Foundation, Inc.
    Inventors: Kevin C. Lee, Charles A. Lee, John Silcox
  • Patent number: 4943540
    Abstract: A method for selectively etching higher aluminum concentration AlGaAs in the presence of lower aluminum concentration AlGaAs or GaAs, preferably at room temperature. The AlGaAs is first cleaned with a solution of NH.sub.4 OH and rinsed. The AlGaAs is then etched in a solution of HF. If photoresist is used on the AlGaAs, the photoresist may first be baked to increase the adhesion of the photoresist to the AlGaAs and to "toughen" the photoresist to reduce undercutting thereof. Agitation is applied to the AlGaAs or the etchant to assist in the uniform etching of the AlGaAs.
    Type: Grant
    Filed: December 28, 1988
    Date of Patent: July 24, 1990
    Assignee: AT&T Bell Laboratories
    Inventors: Fan Ren, Nitin J. Shah
  • Patent number: 4939102
    Abstract: 36 We have discovered the III-V semiconductor layers with previously unattainably high effective hole concentrations can be produced by molecular growth processes (e.g. MBE) if an amphoteric dopant such as Be is used and if, during the growth of the highly doped III-V layer, the substrate is maintained at a temperature T.sub.g that is substantially lower than customarily used. For instance, a InGaAs layer with effective hole concentration 1.0.times.10.sup.20 cm.sup.-3 was grown at T.sub.g =450.degree. C., and a GaAs layer with effective hole concentration of 1.0.times.10.sup.20 cm.sup.-3 was grown at T.sub.g of 475.degree. C. The heavily doped III-V layers can be of device grade and can usefully be part of electronic devices such as high speed bipolar transistors.
    Type: Grant
    Filed: January 17, 1989
    Date of Patent: July 3, 1990
    Assignee: American Telephone and Telegraph Company
    Inventors: Robert A. Hamm, Roger J. Malik, Morton B. Panish, John F. Walker
  • Patent number: 4937204
    Abstract: A semiconductor apparatus is disclosed, in which the entire or part of an electron active region is formed by a superlattice structure semiconductor layer in which a plurality of different semiconductor layers, less than 8 monolayers, and containing a fraction or a binary compound semiconductor layers are alternately and epitaxially grown and a main current direction is selected to be in the direction perpendicular to the laminae of said superlattice layers.
    Type: Grant
    Filed: January 4, 1989
    Date of Patent: June 26, 1990
    Assignee: Sony Corporation
    Inventors: Akira Ishibashi, Yoshifumi Mori, Masao Itabashi
  • Patent number: 4935382
    Abstract: A semiconductor epitaxial device structure is described in which there are alternate single crystal layers of semiconductor, insulator and semiconductor. A typical example is InP/CaF.sub.2 /InP. A process for producing such a structure is also described.
    Type: Grant
    Filed: October 31, 1988
    Date of Patent: June 19, 1990
    Assignee: American Telephone and Telegraph Company
    Inventors: Wilbur D. Johnston, Jr., Charles W. Tu
  • Patent number: 4908074
    Abstract: Disclosed is a process for the production of a semiconductor element by introducing a gas of an organic metal compound of an element of the group III and a gas containing an element of the group V into a reaction chamber in which a substrate of a single crystal of alumina is arranged and epitaxially growing a III.V compound semiconductor by the thermal decomposition vapor deposition of the compound of the elements of the groups III.V, said process comprises, in combination, the steps of (A) heating the substrate at a temperature of 400.degree. to 550.degree. C., introducing the gas of the organic metal compound of the element of the group III and the gas containing the element of the group V into the reaction chamber and forming a film of a compound of the elements of the groups III.V on the surface of the substrate by the vapor deposition, (B) heating the substrate obtained at the step (A) at a temperature higher than 550.degree. C. but lower than 750.degree. C.
    Type: Grant
    Filed: December 6, 1988
    Date of Patent: March 13, 1990
    Assignee: Kyocera Corporation
    Inventors: Takashi Hosoi, Kokichi Ishibitsu
  • Patent number: 4877757
    Abstract: A processing apparatus and method for depositing a passivating layer on a mercury-cadmium-telluride wafer utilizing a single process chamber to provide oxygen gas to the chamber with the excitation energy being provided by a remotely generated plasma in order to remove any organic residue and then supplying either a sulfide or selenide gas in combination with illuminating the wafer with an in situ generated ultraviolet energy to produce a passivating layer.
    Type: Grant
    Filed: December 7, 1988
    Date of Patent: October 31, 1989
    Assignee: Texas Instruments Incorporated
    Inventors: Rudy L. York, Joseph D. Luttmer, Patricia B. Smith, Cecil J. Davis
  • Patent number: 4865655
    Abstract: An epitaxial wafer for producing arrays of GaAsP-LEDs comprises, in the GaAs.sub.1-x P.sub.x layer with varying X, a layer region(s) with a discontinuous variance of x along the thickness of the GaAs.sub.1-x P.sub.x layer. This layer region(s) contribute to a uniformity in the brightness of the light emission of LEDs formed in the epitaxial wafer.
    Type: Grant
    Filed: November 18, 1987
    Date of Patent: September 12, 1989
    Assignees: Mitsubishi Monsanto Chemical Co., Ltd., Mitsubishi Chemical Industries, Ltd.
    Inventors: Hisanori Fujita, Masaaki Kanayama, Takeshi Okano
  • Patent number: 4855250
    Abstract: A method of manufacturing a semiconductor light emitting device by forming a compound semiconductor structure with homo- or heterojunction therein having a first p-type compound semiconductor crystal layer at the top of the structure, growing a second p-type compound semiconductor crystal layer on the structure in a reactor, wherein, before the beginning of the crystal growth step, a p-type dopant is caused to flow into the reactor in which the structure is placed. In some embodiments, the flow of the p-type dopant continues after the completion of the crystal growth.
    Type: Grant
    Filed: December 28, 1987
    Date of Patent: August 8, 1989
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Motoyuki Yamamoto, Yasuhiko Tsuburai
  • Patent number: 4851368
    Abstract: A triangular ring laser utilizing total internal reflection at two angled facets and a preselected amount of reflection at a third angled facet is disclosed. Partial transmission occurs through the third facet to reduce the threshold current required for achieving stimulated emission. The facets are at three corners of the triangular laser, and are formed by chemically assisted ion beam etching in which SiO.sub.2 is used as a mask, whereby smooth vertical walls are produced to form facets having reflective characteristics equivalent to those formed by cleaving.
    Type: Grant
    Filed: December 4, 1987
    Date of Patent: July 25, 1989
    Assignee: Cornell Research Foundation, Inc.
    Inventors: Abbas Behfar-Rad, S. Simon Wong
  • Patent number: 4843033
    Abstract: A method of diffusion of dopants (e.g. zinc) into III-V substrates (e.g. GaAs) using metal silicide and dopants (e.g. W.sub.x Si.sub.y :Zn) is disclosed. A cap layer (e.g. SiO.sub.2 or Si.sub.3 N.sub.4) is also used. The zinc tungsten silicide is formed by cosputtering zinc and tungsten silicide (W.sub.5 Si.sub.3). Applications include adjustment of threshold voltages in JFETs by rapid thermal pulsing of zinc into device channel regions and use of the zinc tungsten silicide as a base contact plus extrinsic base dopant source together with a nitride sidewall self-alignment.
    Type: Grant
    Filed: April 20, 1987
    Date of Patent: June 27, 1989
    Assignee: Texas Instruments Incorporated
    Inventors: Donald L. Plumton, Shiban K. Tiku
  • Patent number: 4839307
    Abstract: A semiconductor laser having an internal current restriction includes a (100) face-oriented p-type GaAs substrate treated to have a groove or difference in level having an (n11) A face (n=1-5) as an inclined surface. An AlGaAs: Si layer, an AlGaAs:Be cladding layer, an AlGaAs active layer, and an AlGaAs:Sn cladding layer are grown on the substrate in the order mentioned. Since the Si acts as an n-type material on the (100) face and as a p-type material on the (n11) face, the AlGaAs:Si layer becomes a p-type layer solely in the groove, and it is in this portion that a current path is formed. The laser can be fabricated by molecular-beam epitaxy applied in a single step.
    Type: Grant
    Filed: May 11, 1987
    Date of Patent: June 13, 1989
    Assignee: Omron Tateisi Electronics Co.
    Inventors: Koichi Imanaka, Hiroshi Imamoto
  • Patent number: 4830984
    Abstract: A method, and products formed by such method, of providing a substantially planar surface to a layer of semiconducting material (24) formed on a first surface of a substrate (20), the substrate having a second surface opposite the first surface. The method comprising forming a layer (22) of a first material on the second surface of the substrate; forming a layer of the semiconducting material (24) on the first surface of the substrate; whereby said layer of said first material exerts a tensioning force on said second surface of the substrate (20) which countereffects a tensioning force exerted on said first surface of said substrate by said layer of semiconductor material (24) so that said first surface of said substrate has a substantially planar form. In some embodiments tensioning forces arise due to differential thermal expansion of said first material and said substrate and said semiconductor material and said substrate.
    Type: Grant
    Filed: July 18, 1988
    Date of Patent: May 16, 1989
    Assignee: Texas Instruments Incorporated
    Inventor: Andrew J. Purdes
  • Patent number: 4829023
    Abstract: A method for producing a semiconductor laser including successively growing at least two semiconductor layers simultaneously on a substrate, the finally grown layer not containing aluminum and the layer grown immediately before the finally grown layer containing aluminum, etching a stripe groove through the finally grown layer to expose part of the semiconductor layer containing aluminum, growing a second semiconductor layer not including aluminum on the finally grown layer and the exposed surface of the semiconductor layer containing aluminum, and growing a semiconductor layer including aluminum on the second semiconductor layer not containing aluminum.
    Type: Grant
    Filed: November 30, 1987
    Date of Patent: May 9, 1989
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yutaka Nagai, Yutaka Mihashi, Tetsuya Yagi, Yoichiro Ota
  • Patent number: 4818712
    Abstract: An aluminum liftoff masking process is effected on a prepared gallium arsenide wafer having a base thereon. Successive layers of silicon dioxide and aluminum are deposited on the wafer. The aluminum and silicon dioxide layers are successively etched, including undercutting of the aluminum layer. Base majority carriers are implanted through the windows to the base and refractory metal ohmic contacts are built up in the windows. After forming the base contacts, the base contact areas may be passivated. The aluminum layer and any overlaying layers thereon are removed by etching off the aluminum.
    Type: Grant
    Filed: October 13, 1987
    Date of Patent: April 4, 1989
    Assignee: Northrop Corporation
    Inventor: John W. Tully
  • Patent number: 4782034
    Abstract: Semi-insulating epitaxial layers of Group III-V based semiconductor compounds are produced by an MOCVD process through the use of bis arene titanium sources, such as cyclopentadienyl cycloheptatrienyl titanium and bis (benzene) titanium.
    Type: Grant
    Filed: June 4, 1987
    Date of Patent: November 1, 1988
    Assignee: American Telephone and Telegraph Company, AT&T Bell Laboratories
    Inventors: Andrew G. Dentai, Charles H. Joyner, Jr., Timothy W. Weidman, John L. Zilko
  • Patent number: 4772564
    Abstract: A thin-film solar cell on a substrate is fabricated by selectively introducing nucleation sites into the insulator layer which is formed on the substrate material, and activating the nucleation sites during growth of the semiconductor layers. The solar cell is made up of semiconductor layers formed on a substrate. The substrate includes an insulator containing electrically conducting nucleation sites which is interposed between the electrical contact of the substrate and the adjacent semiconductor. The insulator can also be optically transparent. Grain boundaries and voids terminate on the insulator.
    Type: Grant
    Filed: May 13, 1987
    Date of Patent: September 20, 1988
    Assignee: Astrosystems, Inc.
    Inventors: Allen M. Barnett, Robert B. Hall
  • Patent number: 4716445
    Abstract: The heterojunction bipolar transistor has a structure of wide band-gap transistor and comprises a collector region having an N-type GaAs layer, a base region having a P-type germanium layer formed on the N-type GaAs layer, and an emitter region having an N-type semiconductor layer of mixed crystal of silicon and germanium formed on the P-type germanium layer. The mixed crystal of the N-type semiconductor layer may have a uniform distribution of silicon or a graded distribution of silicon in which a content of silicon is zero at the surface facing the P-type germanium layer and is continuously increased with distance from the surface facing the P-type germanium layer.
    Type: Grant
    Filed: January 20, 1987
    Date of Patent: December 29, 1987
    Assignee: NEC Corporation
    Inventor: Jun'ichi Sone
  • Patent number: 4700467
    Abstract: Grounding of source contacts (S) of flat devices and integrated circuits (of the FET type) is carried out according to the following process steps: a GaAs wafer is applied on a support and is covered on its free or rear face with photoresist; the latter is then etched along the border lines of the single FETs; the GaAs layer between contiguous FETs is removed also to make accessible the contacts S; a layer of noble metal is then deposited on the FET rear faces, so that it bridges the contacts S; the single metallized devices are disconnected from the initial support and finally are soldered to a package base.
    Type: Grant
    Filed: June 7, 1985
    Date of Patent: October 20, 1987
    Assignee: Telettra-Telefonia Eletrronica e Radio, S.p.A.
    Inventor: Giampiero Donzelli
  • Patent number: 4657603
    Abstract: A method for the manufacture of gallium arsenide thin film solar cells on inexpensive substrate material whereby an intermediate layer of highly doped, amorphous germanium is employed in order to promote the growth of the gallium arsenide layers. A high-energy radiation is directed to specific, prescribed points on the highly doped, amorphous germanium layer thereby generating centers having a defined crystal orientation, so that the epitaxial layer spreads laterally from these centers in a surface-covering fashion during the epitaxial vapor phase deposition. The solar cells produced by designational grain growth can be manufactured with high purity in a simple way and have an efficiency (greater than 20%) comparable to known mono-crystalline solar cells.
    Type: Grant
    Filed: September 20, 1985
    Date of Patent: April 14, 1987
    Assignee: Siemens Aktiengesellschaft
    Inventors: Wolfgang Kruehler, Josef Grabmaier
  • Patent number: 4533410
    Abstract: A layer of a compound semiconductor having good quality is formed by disposing a substrate in an epitaxial growth layer, feeding a second reactant gas through a guide member extending from the downstream side to the upstream side of the flow of a first reactant gas, mixing the first reactant gas and second reactant gas, and supplying the resultant gaseous mixture of the first and second reactant gases onto the substrate.
    Type: Grant
    Filed: October 17, 1983
    Date of Patent: August 6, 1985
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Mototsugu Ogura, Yuzaburoh Ban, Nobuyasu Hase
  • Patent number: H29
    Abstract: A TUNNETT (tunneling transit time) electronic device comprising a very thin injector uniformly doped at a high concentration, a thin drift region of lower doping of the same semiconductivity type, and a collector of high doping of the same semiconductivity type. A Schottky barrier is formed by placing a metal electrode on the injector and an ohmic contact may be made on the collector. In a preferred embodiment the injector is made of Ge grown on the drift region by vacuum epitaxy. The drift region is preferably GaAs grown by epitaxy on a GaAs collector.
    Type: Grant
    Filed: January 4, 1983
    Date of Patent: March 4, 1986
    Assignee: The Government of the United States
    Inventors: Aristos Christou, John E. Davey
  • Patent number: H368
    Abstract: A method of improving field-effect transistors, and the product thereof, wherein the resistivity of the upper layer of the source-gate channel region of a GaAs field-effect transistor (FET) may be selectively raised is disclosed. Impurity ions are implanted in the source-gate channel region followed by a much shallower implantation of boron in the same region. The boron ion concentration should exceed the N+ impurity ion concentration by a factor of 2 or more.
    Type: Grant
    Filed: September 16, 1980
    Date of Patent: November 3, 1987
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventor: Max N. Yoder