Germanium On Silicon Or Ge-si On Iii-v Patents (Class 148/DIG59)
  • Patent number: 5997638
    Abstract: The present invention is a layered structures of substantially-crystalline semiconductor materials and processes for making such structures. More particularly, the invention epitaxial grows a substantially-crystalline layer of a second elemental semiconductor material on a substantially-crystalline first semiconductor material different from the second material in which there is a significant mismatch in at least one dimension between the crystal-lattice structures of the two materials.
    Type: Grant
    Filed: May 9, 1995
    Date of Patent: December 7, 1999
    Assignee: International Business Machines Corporation
    Inventors: Matthew Warren Copel, Michael Horn von Hoegen, Francoise Isabelle Kolmer Le Goues, Rudolf Maria Tromp
  • Patent number: 5906708
    Abstract: Silicon-germanium-based compositions comprising silicon, germanium, and carbon (i.e., Si--Ge--C), methods for growing Si--Ge--C epitaxial layer(s) on a substrate, etchants especially suitable for Si--Ge--C etch-stops, and novel methods of use for Si--Ge--C compositions are provided. In particular, the invention relates to Si--Ge--C compositions, especially for use as etch-stops and related processes and etchants useful for microelectronic and nanotechnology fabrication.
    Type: Grant
    Filed: December 6, 1995
    Date of Patent: May 25, 1999
    Assignee: Lawrence Semiconductor Research Laboratory, Inc.
    Inventors: McDonald Robinson, Richard C. Westhoff, Charles E. Hunt, Li Ling
  • Patent number: 5846867
    Abstract: A method of producing a bipolar transistor includes the step of forming an emitter contact layer containing a high concentration of impurity by means of plasma doping or solid-state diffusion without causing diffusion of impurity in a base layer. This makes it possible to realize a thin base layer having a high impurity concentration.The invention also provides a method of producing a semiconductor device including a bipolar transistor and another device element such as a resistor element including a polysilicon layer containing an activated impurity in such a manner that both the bipolar transistor and the device element are disposed on the same single substrate, the method including the steps of: forming a polysilicon layer containing an activated impurity on the surface of a substrate; and then forming a base layer of the bipolar transistor. This method prevents the base layer from being affected by heat treatment on the polysilicon layer.
    Type: Grant
    Filed: December 17, 1996
    Date of Patent: December 8, 1998
    Assignee: Sony Corporation
    Inventors: Takayuki Gomi, Hiroaki Ammo
  • Patent number: 5616515
    Abstract: A resonant tunneling diode (400) made of a germanium quantum well (406) with silicon oxide tunneling barriers (404, 408). The silicon oxide tunneling barriers (404, 408) plus germanium quantum well (406) may be fabricated by oxygen segregation from germanium oxides to silicon oxides.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: April 1, 1997
    Assignee: Texas Instruments Incorporated
    Inventor: Yasutoshi Okuno
  • Patent number: 5521108
    Abstract: A conductive member is described with a surface of controlled roughness thereon which is useful in the construction of an integrated circuit structure. In a preferred embodiment, the conductive member is formed using a mixture of germanium and silicon which is then oxidized, resulting in the formation of a roughened surface on the germanium/silicon conductive member due to the difference in the respective rates of oxidation of the germanium and silicon. After oxidation of the conductive member, the oxide layer may be removed, leaving the roughened surface on the germanium/silicon conductive member. When an integrated circuit structure such as an EPROM is to be formed using this conductive member with a roughened surface, a further layer of oxide is then deposited over the roughened surface followed by deposition of a second layer of conductive material such as polysilicon or a germanium/silicon mixture, from which the control gate will be formed.
    Type: Grant
    Filed: September 15, 1993
    Date of Patent: May 28, 1996
    Assignee: LSI Logic Corporation
    Inventors: Michael D. Rostoker, Ashok Kapoor
  • Patent number: 5484737
    Abstract: Disclosed is a fabrication of a bipolar transistor with a super self-aligned vertical structure in which emitter, base and collector are vertically self-aligned, the fabrication method comprising the steps of forming a conductive buried collector region in a silicon substrate by using ion-implantation of an impurity and thermal-annealing; sequentially forming several layers; selectively removing the nitride and polysilicon layers to form a pattern; sequentially forming a silicon oxide layer, a third layer and a silicon oxide layer thereon; forming a patterned photoresist layer thereon to define active and inactive regions and removing several layers on the active region to form an opening; forming a side wall on both sides of the opening; forming a collector on a surface portion of the buried collector region up to a lower surface of the polysilicon layer; removing the side wall and the third nitride layer to expose a side surface of the second polysilicon layer; selectively forming a base on an upper surface
    Type: Grant
    Filed: December 13, 1994
    Date of Patent: January 16, 1996
    Assignees: Electronics & Telecommunications Research Institute, Korea Telecommunication Authority
    Inventors: Byung-Ryul Ryum, Tae-Hyeon Han, Soo-Min Lee, Deok-Ho Cho, Seong-Hearn Lee, Jin-Young Kang
  • Patent number: 5330929
    Abstract: The present invention includes a static random access memory cell and a method of forming the memory cell, wherein the memory cell may comprise an active region and a first layer. The active region including a first segment, a second segment, and a third segment, wherein 1) the first segment has an adjacent end and a distal end; 2) the second segment is generally parallel to the first segment, and has an adjacent end and a distal end; and 3) the third segment is generally perpendicular to the first direction, wherein the adjacent end of the first segment lies near one end of the third segment, wherein the adjacent end of the second segment lies near the other end of the third segment. The first layer has the a shape similar to the active region except that the first layer does not lie over the first and second segments near the distal ends.
    Type: Grant
    Filed: October 5, 1992
    Date of Patent: July 19, 1994
    Assignee: Motorola, Inc.
    Inventors: James R. Pfiester, James D. Hayden
  • Patent number: 5326721
    Abstract: This is a method for fabricating a structure useful in semiconductor circuitry. The method comprises: growing a germanium layer 28 directly or indirectly on a semiconductor substrate 20; and depositing a high-dielectric constant oxide 32 (e.g. a ferroelectric oxide) on the germanium layer. Preferably, the germanium layer is epitaxially grown on the semiconductor substrate. This is also a semiconductor structure, comprising: a semiconductor substrate; a germanium layer on the semiconductor substrate; and a high-dielectric constant oxide on the germanium layer. Preferably the germanium layer is single-crystal. Preferably the substrate is silicon and the germanium layer is less than about 1 nm thick or the substrate is gallium arsenide (in which case the thickness of the germanium layer is not as important). A second germanium layer 40 may be grown on top of the high-dielectric constant oxide and a conducting layer 42 (possibly epitaxial) grown on the second germanium layer.
    Type: Grant
    Filed: May 1, 1992
    Date of Patent: July 5, 1994
    Assignee: Texas Instruments Incorporated
    Inventor: Scott R. Summerfelt
  • Patent number: 5312766
    Abstract: Germanium is used to significantly enhance the drift mobilities of minority carriers in the channels of N-channel and P-channel metal-oxide-semiconductor (MOS) transistors with silicon substrates. Germanium processing is also used to enhance the source/drain contact conductance for MOS devices. Methods are disclosed for forming the germanium-rich interfacial layer utilizing a germanium implant and wet oxidation or growing a silicon-germanium alloy by molecular beam epitaxy.
    Type: Grant
    Filed: February 7, 1992
    Date of Patent: May 17, 1994
    Assignee: National Semiconductor Corporation
    Inventors: Sheldon Aronowitz, Courtney Hart, Court Skinner
  • Patent number: 5296387
    Abstract: Germanium is used to significantly enhance the drift mobilities of minority carriers in the channels of N-channel and P-channel metal-oxide-semiconductor (MOS) transistors with silicon substrates. Germanium processing is also used to enhance the source/drain contact conductance for MOS devices. Methods are disclosed for forming a germanium-rich interfacial layer utilizing a germanium implant and wet oxidation or growing a silicon-germanium alloy by molecular beam epitaxy.
    Type: Grant
    Filed: December 2, 1992
    Date of Patent: March 22, 1994
    Assignee: National Semiconductor Corporation
    Inventors: Sheldon Aronowitz, Courtney Hart
  • Patent number: 5281299
    Abstract: A method for manufacturing a crystal comprising at least two elements wherein the proportion of at least one of the elements varies in the direction of the thickness. A CVD process is used. The proportion of the gas components from which is formed the deposition is varied with time. The invention applies to the manufacturing of Si.sub.x Ge.sub.1-x crystals.
    Type: Grant
    Filed: July 2, 1992
    Date of Patent: January 25, 1994
    Assignees: Institut Max Von Laue, Institut National Polytechnique de Grenoble
    Inventors: Alain Escoffier, Roland Madar, Andreas Magerl, Eric Mastromatteo
  • Patent number: 5281552
    Abstract: A method is described for making at least one MOS transistor on a silicon substrate. According to this method, a layer of a silicon dioxide material is formed on a principal surface of the substrate. The oxide layer is then patterned such that at least one source region and at least one drain region of the substrate are exposed. A layer of boron-doped germanium is then deposited on the exposed regions by RTCVD. The substrate is then heated such that boron diffuses from the germanium layer into the source and drain regions. The substrate principal surface can then be etched such that the germanium layer is removed with high selectivity.
    Type: Grant
    Filed: February 23, 1993
    Date of Patent: January 25, 1994
    Assignee: AT&T Bell Laboratories
    Inventors: Clifford A. King, Byung G. Park
  • Patent number: 5250452
    Abstract: The invention is a method of depositing a layer of polycrystalline silicon on a silicon dioxide substrate until the layer of polycrystalline silicon is thick enough to support the deposition of germanium thereon, but while thin enough to substantially avoid the deleterious effects on the characteristics of semiconductor device structure that the deposition of polycrystalline silicon would otherwise potentially cause. The polycrystalline layer is then exposed to a germanium containing gas at a temperature below the temperature at which germanium will deposit on silicon dioxide alone while preventing native growth of silicon dioxide on the polycrystalline silicon layer, and for a time sufficient for a desired thickness of polycrystalline germanium to be deposited on the layer of polycrystalline silicon.
    Type: Grant
    Filed: June 19, 1991
    Date of Patent: October 5, 1993
    Assignee: North Carolina State University
    Inventors: Mehmet Ozturk, Jimmie Wortman
  • Patent number: 5242847
    Abstract: Doped silicon-germanium alloy is selectively deposited on a semiconductor substrate, and the semiconductor substrate is then heated to diffuse at least some of the dopant from the silicon-germanium alloy into the semiconductor substrate to form a doped region at the face of the semiconductor substrate. The doped silicon-germanium alloy acts as a diffusion source for the dopant, so that shallow doped, regions may be formed at the face of the semiconductor substrate without ion implantation. A high performance contact to the doped region is also provided by forming a metal layer on the doped silicon-germanium alloy layer and heating to react at least part of the silicon-germanium alloy layer with at least part of the metal layer to form a layer of germanosilicide alloy over the doped regions. The method of the present invention is particularly suitable for forming shallow source and drain regions for a field effect transistor, and self-aligned source and drain contacts therefor.
    Type: Grant
    Filed: July 27, 1992
    Date of Patent: September 7, 1993
    Assignee: North Carolina State University at Raleigh
    Inventors: Mehmet C. Ozturk, Douglas T. Grider, Mahesh K. Sanganeria, Stanton P. Ashburn
  • Patent number: 5183778
    Abstract: A semiconductor device is produced by forming a crystalline substrate of a first layer of Si and a second layer of GaAs or GaAs-containing compound formed on the first layer, wherein a Ge or Ge-containing crystalline layer is formed as an intervening layer between the second layer and the first layer.
    Type: Grant
    Filed: December 30, 1991
    Date of Patent: February 2, 1993
    Assignee: Fujitsu Limited
    Inventor: Kanetake Takasaki
  • Patent number: 5180684
    Abstract: A semiconductor growth process wherein a plurality of layers, each consisting of a different king of semiconductor material, are grown, includes the steps of: heating a substrate to a first growth starting temperature at which a growth of a first semiconductor layer can be started, supplying a first material gas to the surface of the substrate to cause a growth of the first semiconductor layer, lowering the temperature of the substrate to below first growth starting temperature, and at the same time, stopping the supply of the first material gas, to stop the growth of the first semiconductor layer, heating the substrate to a second growth starting temperature at which a growth of a second semiconductor layer can be started, and supplying a second material gas to the surface of the substrate to cause a growth of the semiconductor layer.
    Type: Grant
    Filed: March 6, 1990
    Date of Patent: January 19, 1993
    Assignee: Fujitsu Limited
    Inventor: Hiroshi Fujioka
  • Patent number: 5089428
    Abstract: A method for preparing a germanium layer (22) adjacent to a germanium silicon layer (20). Initially, a P-germanium silicon layer (16) is deposited on to an N-germanium silicon layer (14). The continuous germanium layer (22) is formed by heating the layers (14 and 16) in a steam oxidation step to approximately 1000 degrees Centigrade to transform the P-germanium silicon layer (16) into the P-germanium layer (18) and a SiO.sub.2 layer (22). A method for forming a heterojunction bipolar transistor utilizing a P-germanium layer (50) is also disclosed.
    Type: Grant
    Filed: December 27, 1989
    Date of Patent: February 18, 1992
    Assignee: Texas Instruments Incorporated
    Inventors: Douglas P. Verret, Kenneth E. Bean
  • Patent number: 4983536
    Abstract: A junction field effect transistor, specifically a static induction transistor. Prior to metallization a thin layer of germanium is placed over the exposed silicon of the source and gate regions. The germanium is intermixed with the underlying silicon to form a germanium-silicon composite. A rapid thermal anneal is performed to recrystallize the germanium-silicon composite. Alternatively, a single crystal epitaxial layer may be deposited on the silicon. Conventional metallization procedures are employed to produce ohmic source and gate contact members to the germanium-silicon composite or the epitaxial germanium of the source and gate regions. By virtue of the reduced bandgap provided by the presence of the germanium, the contact resistance of the device is reduced.
    Type: Grant
    Filed: November 24, 1989
    Date of Patent: January 8, 1991
    Assignee: GTE Laboratories Incorporated
    Inventors: Emel S. Bulat, Marvin J. Tabasky
  • Patent number: 4975387
    Abstract: Epitaxial Si-Ge heterostructures are formed by depositing a layer of amorphous Si-Ge on a silicon wafer. The amorphous Si-Ge on the silicon wafer is then subjected to a wet oxidation in order to form an epitaxial Si-Ge heterostructure. Any size wafer may be used and no special precaustions need be taken to ensure a clean amorphous Si-Ge/Si interface.
    Type: Grant
    Filed: December 15, 1989
    Date of Patent: December 4, 1990
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Sharka M. Prokes, Wen F. Tseng, Aristos Christou
  • Patent number: 4962051
    Abstract: An improved method of fabricating a defect-free semiconductor layer and a semiconductor on insulator structure is provided by forming an isoelectronically doped semiconductor layer between a substrate and an semiconductor layer. The isoelectronic dopant atoms are different in atomic size than the atoms of the semiconductor material, thus misfit dislocations are created at the interface of the isoelectronically doped semiconductor layer due to lattice mismatch. Impurities and defects are not only gettered to the misfit dislocation sites, but are also prevented from propagating to the epitaxial layer. These misfit dislocations are thermally stable and are confined in a plane parallel to the interfaces of the isoelectronically doped semiconductor layer, thus very effective gettering agents. If the isoelectroncially doped semiconductor layer us also a heavily doped buried layer, no misfit dislocations are desired because the buried layer is an active device layer.
    Type: Grant
    Filed: November 18, 1988
    Date of Patent: October 9, 1990
    Assignee: Motorola, Inc.
    Inventor: H. Ming Liaw
  • Patent number: 4912066
    Abstract: A semiconductor device is programmed by a laser beam which causes an insulator between two conductors on a silicon substrate to be permanently altered, as by breakdown of the insulator. The conductors may be metals such as aluminum or tungsten, and the insulator is a layer of deposited or thermal silicon oxide. The breakdown may be enhanced by voltage applied between the conductors while the laser beam is focused on the structure.
    Type: Grant
    Filed: March 7, 1988
    Date of Patent: March 27, 1990
    Assignee: Texas Instruments Incorporated
    Inventor: Kendall S. Wills
  • Patent number: 4891329
    Abstract: A method of forming a nonsilicon semiconductor layer on an insulating layer by forming a thin heteroepitaxial layer of nonsilicon semiconductor on a first substrate having a lattice structure which matches that of the heteroepitaxial layer. A first insulating layer is formed on the heteroepitaxial layer. A second insulating layer is formed on the surface of a second substrate. The first and second insulating layers are bonded together to form a unified structure, and the first substate is etched away. In a preferred embodiment the heteroepitaxial layer is germanium, gallium arsenide or silicon-germanium alloy while the first substrate is silicon, germanium, gallium arsenide or silicon-germanium alloy.
    Type: Grant
    Filed: November 29, 1988
    Date of Patent: January 2, 1990
    Assignees: University of North Carolina, Microelectronics Center of North Carolina
    Inventors: Arnold Reisman, Wei-Kan Chu
  • Patent number: 4876210
    Abstract: The effects of excessive lattice mismatch in solution grown heterostructures are reduced by incorporating a lattice graded interface layer between the substrate and the heteroepitaxial layer. The effects of lattice mismatch are also reduced by reducing the contact area with a selective growth mask which controls where growth initiates on the substrate. The effect of mismatched solubility is reduced by double saturation of the solvent and selective supersaturation of the solvent.
    Type: Grant
    Filed: March 4, 1988
    Date of Patent: October 24, 1989
    Assignee: The University of Delaware
    Inventors: Allen M. Barnett, John C. Zolper
  • Patent number: 4861393
    Abstract: A molecular beam epitaxy method of growing Ge.sub.x Si.sub.1-x films on silicon substrate is described. Semiconductor heterostructures using Ge.sub.x Si.sub.1-x layers grown on either Ge or Si substrates are described.
    Type: Grant
    Filed: May 28, 1987
    Date of Patent: August 29, 1989
    Assignee: American Telephone and Telegraph Company, AT&T Bell Laboratories
    Inventors: John C. Bean, Leonard C. Feldman, Anthony T. Fiory
  • Patent number: 4857270
    Abstract: A process for manufacturing a silicon-germanium alloy comprising introducing SiH.sub.4 gas, GeCl.sub.4 gas and P-type or N-type doping gas into a reaction vessel, heating a substrate up to a temperature not lower than 750.degree. C., and depositing a thickly-grown, bulky silicon-germanium alloy upon the substrate within the reaction vessel.
    Type: Grant
    Filed: April 20, 1988
    Date of Patent: August 15, 1989
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Shinji Maruya, Yoshifumi Yatsurugi, Kazuya Togashi
  • Patent number: 4824798
    Abstract: A thin film bilayer composite source comprises a deposited impurity source layer, e.g. Si or Sb, heavily doped with a diffusion enabling agent, e.g. As, and capped with a passivating layer, e.g. Si.sub.3 N.sub.4, SiO.sub.2, AlN or SiO.sub.x N.sub.y. In a preferred embodiment, a thin film bilayer composite source comprises a Si layer on the surface of said structure vapor deposited at a temperature in excess of 500.degree. C. in the presence of a source of As to hevily dope the layer in the range of 5%-20% atomic weight and a thin cap layer of Si.sub.3 N.sub.4 deposited on the Si layer at a temperature in excess of 500.degree. C. having a thickness only sufficient to prevent the outdiffusion of Ga and As, which thickness may be about 400 .ANG.-700 .ANG.. An important aspect of the employment of this bilayer composite source as a diffusion source for III-V structures is that the composite source is initially deposited at high temperatures, above 500.degree.0 C., i.e.
    Type: Grant
    Filed: November 5, 1987
    Date of Patent: April 25, 1989
    Assignee: Xerox Corporation
    Inventors: Robert D. Burnham, Robert L. Thornton
  • Patent number: 4757030
    Abstract: Solid phase epitaxial growth of single crystal layers on single crystal semiconductor substrates at temperatures low enough to preserve the integrity of other entities on the substrates. Contaminants are removed by low energy ion sputtering at a pressure low enough to delay their reformation before the layer can be deposited on the surface followed by annealing for one hour at 400.degree. C. A method of solid phase epitaxially growing a single crystal layer on a single crystal semiconductor substrate is also disclosed.
    Type: Grant
    Filed: November 26, 1986
    Date of Patent: July 12, 1988
    Assignee: Cornell Research Foundation, Inc.
    Inventors: Gregory J. Galvin, Christopher J. Palmstrom
  • Patent number: 4707216
    Type: Grant
    Filed: January 24, 1986
    Date of Patent: November 17, 1987
    Assignee: University of Illinois
    Inventors: Hadis Morkoc, Russ Fischer
  • Patent number: 4588451
    Abstract: Expitaxial composite comprising thin films of a Group III-V compound semiconductor such as gallium arsenide (GaAs) or gallium aluminum arsenide (GaAlAs) on single crystal silicon substrates are disclosed. Also disclosed is a process for manufacturing, by chemical deposition from the vapor phase, epitaxial composites as above described, and to semiconductor devices based on such epitaxial composites. The composites have particular utility for use in making light sensitive solid state solar cells.
    Type: Grant
    Filed: April 27, 1984
    Date of Patent: May 13, 1986
    Assignee: Advanced Energy Fund Limited Partnership
    Inventor: Stanley M. Vernon
  • Patent number: 4561916
    Abstract: A method for the growth of a compound semiconductor comprises growing on a silicon substrate a polycrystalline layer of a desired Group III-V compound semiconductor or a crystal layer of the desired Group III-V compound semiconductor having inferior crystallinity, growing on the formed layer at least one layer of the same semiconductor as the desired Group III-V compound semiconductor and at least one layer of a Group III-V compound semiconductor having a lattice constant approximating the lattice constant of the desired Group III-V compound semiconductor, which layers are alternately disposed, and growing on the alternately disposed layers a layer of the desired Group III-V compound semiconductor.
    Type: Grant
    Filed: July 2, 1984
    Date of Patent: December 31, 1985
    Assignees: Agency of Industrial Science and Technology, Ministry of International Trade and Industry
    Inventors: Masahiro Akiyama, Yoshihiro Akiyama
  • Patent number: 4551394
    Abstract: Localized epitaxial growth of GaAs from a silicon monocrystalline substrate to provide a three-dimensional Si-GaAs structure and method. The silicon has an insulating layer deposited thereover and a window is opened through the layer to expose a small area of the underlying silicon from which silicon is epitaxially grown until the window is nearly full whereupon a thin buffer layer such as germanium is epitaxially grown over the epi-silicon to fill the window. Al.sub.x Ga.sub.1-x As (where x.gtoreq.0) is then locally epitaxially grown from the buffer layer and it grows laterally as well as vertically to cover the surrounding insulating layer surface and provide a site for high frequency electronics.
    Type: Grant
    Filed: November 26, 1984
    Date of Patent: November 5, 1985
    Assignee: Honeywell Inc.
    Inventors: Regis J. Betsch, Michael S. Liu, Obert N. Tufte