Gp Ii-vi Compounds Patents (Class 148/DIG64)
  • Patent number: 6139631
    Abstract: A crystal growth method having the steps of: preparing a growth container having a vapor generating chamber VC provided with a source material 14, a growth chamber GC provided with a seed crystal 12, and a coupling portion 18 having a cross sectional area narrower than a cross sectional area of each of the vapor generating chamber and the growth chamber, the coupling portion coupling the vapor generating chamber and the growth chamber; and vapor-phase growing a single crystal on the seed crystal by forming a temperature gradient in the growth container and by maintaining the seed crystal in the growth chamber at a growth temperature and the source material in the vapor generating chamber at a vapor supply temperature higher than the growth temperature. A crystal having a diameter larger than that of a seed crystal can be formed easily.
    Type: Grant
    Filed: August 12, 1998
    Date of Patent: October 31, 2000
    Assignee: Stanley Electric Co., Ltd.
    Inventor: Hiroyuki Kato
  • Patent number: 5882805
    Abstract: Triisopropylindium ((CH.sub.3).sub.2 CH).sub.3 In is used as an n-type dopant for II/VI semiconductor materials. This dopant precursor is particularly suited for indium doping of II/V semiconductor materials at low carrier concentrations in the range of the low 10.sup.15 cm.sup.-3 and does not exhibit an appreciable memory effect.
    Type: Grant
    Filed: May 18, 1994
    Date of Patent: March 16, 1999
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Kelvin T. Higa, Robert W. Gedridge, Jr., Ralph Korenstein, Stuart JC. Irvine
  • Patent number: 5834361
    Abstract: In a method of forming a II-VI compound semiconductor thin film on an InP substrate, a layer of III-V compound semiconductor mixed crystal is first formed on the InP substrate. The desorption rate of a group V element constituting the III-V compound semiconductor mixed crystal at a decomposition temperature of a native oxide layer formed on a surface of the III-V compound semiconductor mixed crystal layer is lower than a desorption rate of P of the InP substrate at a decomposition temperature of a native oxide layer formed on a surface of the InP substrate. A II-VI compound semiconductor thin film layer is formed on the first III-V compound semiconductor mixed crystal layer.
    Type: Grant
    Filed: April 10, 1996
    Date of Patent: November 10, 1998
    Assignee: NEC Corporation
    Inventors: Kouichi Naniwae, Toru Suzuki
  • Patent number: 5656538
    Abstract: A process for growing semi-insulating layers of indium phosphide and other group III-V materials through the use of halide dopant or etchant introduction during growth. Gas phase epitaxial growth techniques are utilized at low temperatures to produce indium phosphide layers having a resistivity greater than approximately 10.sup.7 ohm-cm. According to the preferred embodiment carbon tetrachloride is used as a dopant at flow rates above 5 sccm to grow the layers with substrate growth temperatures ranging from approximately C. to C. This temperature range provides an advantage over the transition metal techniques for doping indium phosphide since the high temperatures generally required for those techniques limit the ability to control growth. Good surface morphology is also obtained through the growth according to the present invention. The process may be used to form many types of group III-V semiconductor devices.
    Type: Grant
    Filed: March 24, 1995
    Date of Patent: August 12, 1997
    Assignee: The Board of Trustees of the University of Illinois
    Inventors: Nathan F. Gardner, Stephen A. Stockman, Quesnell J. Hartmann, Gregory E. Stillman
  • Patent number: 5547897
    Abstract: The concentration of N acceptors in an as-grown epitaxial layer of a II-VI semiconductor compound is enhanced by the use of tertiary butyl amine as the dopant carrier, and is further enhanced by the use of photo-assisted growth using illumination whose wavelength is within the range of 200-250 nm.
    Type: Grant
    Filed: June 15, 1994
    Date of Patent: August 20, 1996
    Assignee: Philips Electronics North America Corporation
    Inventors: Nikhil R. Taskar, Dennis Gallagher, Donald R. Dorman
  • Patent number: 5484736
    Abstract: A process for producing a cadmium telluride polycrystalline film having grain sizes greater than about 20 .mu.m. The process comprises providing a substrate upon which cadmium telluride can be deposited and placing that substrate within a vacuum chamber containing a cadmium telluride effusion cell. A polycrystalline film is then deposited on the substrate through the steps of evacuating the vacuum chamber to a pressure of at least 10.sup.-6 torr.; heating the effusion cell to a temperature whereat the cell releases stoichiometric amounts of cadmium telluride usable as a molecular beam source for growth of grains on the substrate; heating the substrate to a temperature whereat a stoichiometric film of cadmium telluride can be deposited; and releasing cadmium telluride from the effusion cell for deposition as a film on the substrate.
    Type: Grant
    Filed: September 19, 1994
    Date of Patent: January 16, 1996
    Assignee: Midwest Research Institute
    Inventors: Falah S. Hasoon, Art J. Nelson
  • Patent number: 5472910
    Abstract: Ohmic contacts to p-type IIB/VIB semiconductor are obtained by a process which includes the step of depositing a viscous liquid containing a Group IB metal salt on a surface of a semiconductor, substantially free of oxide groups, heating to form a dried layer, removing the dried layer, washing the surface to remove residual by-products and drying the surface.
    Type: Grant
    Filed: March 16, 1994
    Date of Patent: December 5, 1995
    Assignee: BP Solar Limited
    Inventors: Daniel R. Johnson, Sener Oktik, Mehmet E. Ozsan, Michael H. Patterson
  • Patent number: 5468678
    Abstract: A method for manufacturing a III-V Group compound or a II-VI Group compound semiconductor element by VPE, comprising the step of annealing a grown compound at C. or higher, or irradiating electron beam the grown compound at C. or higher.
    Type: Grant
    Filed: January 12, 1994
    Date of Patent: November 21, 1995
    Assignee: Nichia Chemical Industries, Ltd.
    Inventors: Shuji Nakamura, Naruhito Iwasa, Masayuki Senoh
  • Patent number: 5454885
    Abstract: A typical source of cadmium and tellurium is as a by-product of copper mining. Although attempts are made to remove impurities such as copper prior to commercially supplying them for forming material like cadmium telluride, cadmium zinc telluride and cadmium telluride selenide for use as a substrate to support electronic circuitry, processing during formation of the circuitry causes the impurities from the substrate to segregate into the circuitry, resulting in unacceptable electrical performance of the circuitry. A method for purifying the substrate prior to circuitry formation includes forming a sacrificial layer of mercury telluride or mercury cadmium telluride on the substrate, annealing the combination at elevated temperature with an overpressure of mercury and removing the sacrificial layer along with a contiguous portion of the substrate, if desired. The sacrificial layer may be formed by vapor phase type processes or even by liquid phase epitaxy.
    Type: Grant
    Filed: December 21, 1993
    Date of Patent: October 3, 1995
    Assignee: Martin Marietta Corporation
    Inventors: Gregory K. Dudoff, Karl A. Harris, Lee M. Mohnkern, Richard J. Williams, Robert W. Yanka, Thomas H. Meyers, III
  • Patent number: 5416030
    Abstract: A method is provided for reducing leakage current in an integrated circuit (24). A first doped region (18) having a first conductivity type is formed in a semiconductor layer (10) having a second conductivity type, such that a second doped region (20) having the first conductivity type is formed in the semiconductor layer (10). The second doped region (20) is less conductive than the first doped region (18). The first doped region (18) is removed from the semiconductor layer (10), such that the second doped region (20) substantially remains in the semiconductor layer (10). The integrated circuit (24) is formed to include the second doped region (20) and the semiconductor layer (10).
    Type: Grant
    Filed: October 14, 1993
    Date of Patent: May 16, 1995
    Assignee: Texas Instruments Incorporated
    Inventors: Jerome L. Elkind, Lissa K. Magel
  • Patent number: 5403760
    Abstract: Group II-VI thin film transistors, a method of making same and a monolithic device containing a detector array as well as transistors coupled thereto wherein, according to a first embodiment, there is provided a group II-VI insulating substrate, a doped layer of a group II-VI semiconductor material disposed over the substrate, an insulating gate region disposed over the doped layer, a pair of spaced contacts on the doped layer providing source and drain contacts, a gate contact disposed over the insulating gate region, an insulating layer disposed over exposed regions of the substrate, doped layer, insulating gate region and contacts and metallization disposed on the insulating layer and extending through the insulating layer to the contacts. The thickness of the doped layer is less than the maximum depletion region thickness thereof.
    Type: Grant
    Filed: November 15, 1993
    Date of Patent: April 4, 1995
    Assignee: Texas Instruments Incorporated
    Inventors: Richard A. Schiebel, Michael A. Kinch, Roland J. Koestner
  • Patent number: 5399503
    Abstract: A method for growing an epitaxial layer of a group II-VI tenary or quaternary compound on a substrate. In particular a HgCdTe semiconductor layer is grown on a substrate such as sapphire which does not interdiffuse with the materials in the semiconductor layer. Initially a crystalline CdTe semiconductor layer is formed on the substrate and then the substrate with the CdTe layer thereon is placed into an enclosure along with a Hg-Cd-Te source that is rich in Te. The substrate and the source are then heated so as to establish three-phase equilibrium conditions in the enclosure whereby vapors from the source are transported to the CdTe layer and the latter is converted into a ternary semiconductor compound having the composition Hg.sub.1-x Cd.sub.x Te. The substrate with the Hg.sub.1-x Cd.sub.x Te epitaxial layer thereon is useful as a sensing device.
    Type: Grant
    Filed: January 22, 1993
    Date of Patent: March 21, 1995
    Assignee: Fujitsu Limited
    Inventors: Tetsuo Saito, Tetsuya Kochi, Tamotsu Yamamoto, Kazuo Ozaki, Kosaku Yamamoto
  • Patent number: 5398641
    Abstract: A method and apparatus (10) for forming a p-doped layer (68, 80, 92) of Group II and Group VI elements by molecular beam epitaxial process in which a nitrogen dopant is introduced as the layer (68, 80, 92) is being grown. In one embodiment, molecular nitrogen is passed through a plasma generator (46) for converting it to activated nitrogen, and the activated nitrogen is conducted through an elongated guide tube (50) toward the substrate (66) upon which a Group II-Group VI layer (68, 80, 92) is being grown. In one embodiment, an n-type dopant source (72) is also provided, the apparatus (10) being operable for forming electrical devices (86, 88) having successive layers (78, 80, 90, 92, 94) of differing electrical characteristics.
    Type: Grant
    Filed: July 27, 1993
    Date of Patent: March 21, 1995
    Assignee: Texas Instruments Incorporated
    Inventor: Hung-Dah Shih
  • Patent number: 5386798
    Abstract: A method for growing a deposit upon a substrate of semiconductor material involves the utilization of pulsed laser deposition techniques within a low-pressure gas environment. The substrate and a target of a first material are positioned within a deposition chamber and a low-pressure gas atmosphere is developed within the chamber. The substrate is then heated, and the target is irradiated, so that atoms of the target material are ablated from the remainder of the target, while atoms of the gas simultaneously are adsorbed on the substrate/film surface. The ablated atoms build up upon the substrate, together with the adsorbed gas atoms to form the thin-film deposit on the substrate. By controlling the pressure of the gas of the chamber atmosphere, the composition of the formed deposit can be controlled, and films of continuously variable composition or doping can be grown from a single target of fixed composition.
    Type: Grant
    Filed: October 6, 1993
    Date of Patent: February 7, 1995
    Assignee: Martin Marietta Energy Systems, Inc.
    Inventors: Douglas H. Lowndes, James W. McCamy
  • Patent number: 5372970
    Abstract: A method for epitaxially growing a II-VI compound semiconductor according to this invention comprises the steps of epitaxially growing a GaAs.sub.x Se.sub.1-x layer on a GaAs substrate and epitaxially growing a ZnSe layer or a compound semiconductor layer including ZnSe on the GaAs.sub.x Se.sub.1-x layer. This method provides a II-VI compound semiconductor in which a strain caused by a lattice mismatch is prevented and the hetero interface is excellent.
    Type: Grant
    Filed: June 23, 1993
    Date of Patent: December 13, 1994
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Minoru Kubo
  • Patent number: 5366927
    Abstract: An ohmic contact to a p-type zinc selenide (ZnSe) layer in a Group II-VI semiconductor device, includes a zinc telluride selenide (ZnTe.sub.x Se.sub.1-x) layer on the zinc selenide layer, a mercury selenide (HgSe) layer on the zinc telluride selenide layer and a conductor (such as metal) layer on the mercury selenide layer. The zinc telluride selenide and mercury selenide layers between the p-type zinc selenide and the conductor layer provide an ohmic contact by eliminating the band offset between the wide bandgap zinc selenide and the conductor. Step graded, linear graded, and parabolic graded layers of zinc telluride selenide may be provided. An integrated heterostructure is formed by epitaxially depositing the ohmic contact on the Group II-VI device. A removable overcoat layer may be formed on the Group II-VI device to allow room temperature atmospheric pressure transfer of the device from a zinc based deposition chamber to a mercury based deposition chamber, for deposition of the ohmic contact.
    Type: Grant
    Filed: September 28, 1993
    Date of Patent: November 22, 1994
    Assignee: North Carolina State University
    Inventor: Jan F. Schetzina
  • Patent number: 5354708
    Abstract: The concentration of N acceptors in an as-grown epitaxial layer of a II-VI semiconductor compound is enhanced by the use of tertiary butyl amine as the dopant carrier, and is further enhanced by the use of photo-assisted growth using illumination whose wavelength is at least above the bandgap energy of the compound at the growth temperature.
    Type: Grant
    Filed: July 14, 1993
    Date of Patent: October 11, 1994
    Inventors: Nikhil R. Taskar, Babar A. Khan, Donald R. Dorman
  • Patent number: 5306660
    Abstract: Method and apparatus for vapor phase free methyl radical transport of indium dopant species for precise predetermined reproducible doping concentrations to control electrical properties for MOCVD grown materials.
    Type: Grant
    Filed: February 19, 1991
    Date of Patent: April 26, 1994
    Assignee: Rockwell International Corporation
    Inventors: Charles R. Younger, Shawn L. Johnston, Stuart J. C. Irvine, Edward R. Gertner, Kenneth L. Hess
  • Patent number: 5306653
    Abstract: A method of making a thin film transistor exhibiting a high channel conductance includes the steps of forming, on an insulating transparent substrate, a gate electrode, an insulating layer, a semiconductor layer, a photoresist, in this order and performing a back substrate exposure at the insulating transparent substrate using the gate electrode as a photo mask, to form a photoresist pattern. The photoresist pattern is then baked to make it flow outward to a desired bottom width. The semiconductor layer is etched using the photoresist pattern as an etch mask to form a semiconductor layer pattern. On the resultant entire exposed surface are formed an ohm contact layer and a metal layer. The metal layer is then subjected to photoing and etching processes, to remove its portion disposed above the semiconductor pattern and its opposite side edge portions, thereby forming a metal layer pattern for source and drain electrodes.
    Type: Grant
    Filed: August 25, 1992
    Date of Patent: April 26, 1994
    Assignee: Goldstar Co., Ltd.
    Inventor: Chang W. Hur
  • Patent number: 5306386
    Abstract: Ternary II-VI semiconductor films (16) are formed on a silicon substrate (12) by first depositing a monolayer of arsenic (14) or other Group V metal on a cleaned surface of the substrate. The ternary II-VI semiconductor film is then formed over the arsenic monolayer, either directly thereon or on top of an intermediate II-VI semiconductor buffer layer (18). The use of an arsenic passivating layer facilitates the epitaxial deposition of technologically important II-VI semiconductors such as ZnTe, CdTe, and HgCdTe on silicon substrates of arbitrary crystallographic orientation.
    Type: Grant
    Filed: April 6, 1993
    Date of Patent: April 26, 1994
    Assignee: Hughes Aircraft Company
    Inventor: Terence J. de Lyon
  • Patent number: 5306662
    Abstract: A method for manufacturing a III-V Group compound or a II-VI Group compound semiconductor element by VPE, comprising the step of annealing a grown compound at C. or higher, or irradiating electron beam the grown compound at C. or higher.
    Type: Grant
    Filed: November 2, 1992
    Date of Patent: April 26, 1994
    Assignee: Nichia Chemical Industries, Ltd.
    Inventors: Shuji Nakamura, Naruhito Iwasa, Masayuki Senoh
  • Patent number: 5304281
    Abstract: A process for preparing a film consisting of at least about 90 weight percent of cubic cadmium sulfide is disclosed.In one step of this process, a cadmium sulfide target with a density of at least about 3.8 grams per cubic centimeter is provided. In a separate step, there is provided a heated substrate which is at a temperature of from about 50 to about 300 degrees Centigrade. The heated substrate is disposed at a distance of from about 2 to about 10 centimeters from the target.Both the heated substrate and the target are subjected to a pressure of from about 10.sup.-4 to about 10.sup.-9 Torr. Thereafter, the cadmium sulfide target is contacted with a laser beam with a wavelength of from about 100 nanometers to about 30 microns, an energy of at least about 1.0 watt, and a beam width of less than about 5 millimeters.
    Type: Grant
    Filed: October 23, 1992
    Date of Patent: April 19, 1994
    Assignee: Alfred University
    Inventor: Xingwu Wang
  • Patent number: 5290394
    Abstract: In a method of manufacturing a Hg.sub.1-x Cd.sub.x Te (x=0 to 1) infrared detector using GaAs as a substrate, there is provided a method of depositing a HgCdTe film that has high crystalline quality. By changing the substrate temperature, it is possible to control the plane orientation of a CdTe buffer layer formed on a GaAs (211)B substrate. When the substrate temperature is high, the buffer layer is formed with plane orientation (133) and when the substrate temperature is low, the buffer layer is formed with plane orientation (211). In the former, it is possible to form a film having high crystalline quality as compared with that of a film in the latter.
    Type: Grant
    Filed: September 18, 1992
    Date of Patent: March 1, 1994
    Assignee: NEC Corporation
    Inventor: Tokuhito Sasaki
  • Patent number: 5273931
    Abstract: Epitaxial layers of N-doped II-VI semiconductor compounds are grown on GaAs substrates by MOCVD using FME. Separating the growth and doping by alternating introduction of (1) the semiconductor cation and anion and (2) the cation and the dopant increases the level of doping, the level of activation, and the crystal quality.
    Type: Grant
    Filed: June 4, 1992
    Date of Patent: December 28, 1993
    Assignee: North American Philips Corporation
    Inventors: Nikhil Taskar, Babar A. Khan, Donald R. Dorman
  • Patent number: 5264379
    Abstract: A method of manufacturing a heterojunction bipolar transistor is disclosed. On a base layer of a first semiconductor which contains at least one of gallium and arsenic as a constituent element, an emitter layer of a second semiconductor is formed which contains as a constituent element at least one of gallium and arsenic and which has a band gap larger that of the first semiconductor. Predetermined regions of the emitter layer and an upper portion of the base layer are removed to form a mesa structure. Then, a surface of a junction region of the base layer and the emitter layer of the formed mesa structure is treated using a phosphate etchant and a sulfur or sulfide passivating agent. After the surface treatment, the surface of the junction is covered with an insulating film.
    Type: Grant
    Filed: February 22, 1993
    Date of Patent: November 23, 1993
    Assignee: Sumitomo Electric Industries, Inc.
    Inventor: Shinichi Shikata
  • Patent number: 5264389
    Abstract: A semiconductor laser device of an AlGaInP system includes a GaAs substrate and a surface of the substrate is inclined by or more from a {100} plane in a <011> direction.
    Type: Grant
    Filed: June 10, 1992
    Date of Patent: November 23, 1993
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Hiroki Hamada, Shoji Honda, Masayuki Shono, Takao Yamaguchi
  • Patent number: 5262349
    Abstract: In a method for producing a II-VI compound semiconductor device including mercury, a thin film of a group II element or a group II element compound, which is a solid at room temperature, is deposited on a surface of a p type II-VI compound semiconductor. Annealing is carried out to diffuse the group II element from the thin film into the p type II-VI compound semiconductor whereby a region of the p type II-VI compound semiconductor on which the thin film is present is converted to n type, resulting in a p-n junction. Therefore, instruments and materials are easily handled, increasing work efficiency and productivity. In addition, the annealing is carried out without a complicated temperature profile, resulting in a simple process.
    Type: Grant
    Filed: August 18, 1992
    Date of Patent: November 16, 1993
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Yasuaki Yoshida
  • Patent number: 5229321
    Abstract: A method of diffusing mercury into a crystalline compound semiconductor film including mercury includes forming an amalgam on a region of the semiconductor film into which mercury is to be diffused, forminq a protective film on the amalgam, and annealing, whereby mercury from the amalgam diffuses into the semiconductor film and the protective film prevents the mercury from escaping. Therefore, a complicated temperature profile is not required and the mercury diffusion is carried out without sealing the semiconductor film in a quartz tube. As a result, the instruments and materials used in the diffusion process are easily handled and the diffusion of mercury into a large-sized semiconductor film is possible.
    Type: Grant
    Filed: June 9, 1992
    Date of Patent: July 20, 1993
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Akihiro Takami
  • Patent number: 5227328
    Abstract: Epitaxial layers of II-VI semiconductors in-situ doped with high concentrations of a stable acceptor-type impurity and capped with a diffusion-limiting layer, when subjected to a rapid thermal anneal at a temperature between 700 and 950 degrees C., exhibit a high conversion of the impurities to acceptors, sufficient to render the layers p-type.
    Type: Grant
    Filed: March 16, 1992
    Date of Patent: July 13, 1993
    Assignee: North American Philips Corporation
    Inventors: Babar A. Khan, Nikhil R. Taskar
  • Patent number: 5213998
    Abstract: A method for producing an ohmic contact to a p-type ZnSe semiconductor body in a molecular beam epitaxy chamber. Zinc, thermally cracked Se.sub.2 and nitrogen are injected into the chamber. A ZnSe contact layer is grown by heating the semiconductor body to a temperature less than C., but high enough to promote crystalline growth of the layer doped with nitrogen to a net acceptor concentration of at least 1.times.10.sup.18 cm.sup.-3.
    Type: Grant
    Filed: May 15, 1991
    Date of Patent: May 25, 1993
    Assignee: Minnesota Mining and Manufacturing Company
    Inventors: Jun Qiu, Hwa Cheng, Michael A. Haase, James M. DePuydt
  • Patent number: 5204283
    Abstract: A high-purity II-VI semiconducting compound can be produced by initially preparing a substrate of a II-VI semiconducting compound by a chemical transport method with a halogen as transport medium and then epitaxially growing a layer of a II-VI compound on this substrate.
    Type: Grant
    Filed: August 20, 1991
    Date of Patent: April 20, 1993
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Masahiko Kitagawa, Yoshitaka Tomomura
  • Patent number: 5182217
    Abstract: Photodetectors that produce detectivities close to the theoretical maximum detectivity include an electrically insulating substrate carrying a body of semiconductor material that includes a region of first conductivity type and a region of second conductivity type where the region of first conductivity type overlies and covers the junction with the region of second conductivity type and where the junction between the first and second regions separates minority carriers in the region of second conductivity type from majority carriers in the region of first conductivity type. These photodetectors produce high detectivities where radiation incident on the detectors has wavelengths in the range of about 1 to about 25 microns or more, particularly under low background conditions.
    Type: Grant
    Filed: August 2, 1991
    Date of Patent: January 26, 1993
    Assignee: Santa Barbara Research Center
    Inventor: Paul R. Norton
  • Patent number: 5174854
    Abstract: A ZnSe source crystal is treated in a Se vapor pressure peaks are obtained when the Se pressure is 6 to 9 atoms dissolved in a Zn solvent to the saturation concentration at a high temperature portion in the solution. A ZnSe single crystal is grown on an underlie substrate placed at a low temperature portion in the solution. When the temperature of the vapor pressure treatment is C., excellent photoluminescence peaks are obtained when the Se pressure is 6 to 9 atoms.
    Type: Grant
    Filed: May 8, 1991
    Date of Patent: December 29, 1992
    Assignee: Stanley Electric Co., Ltd.
    Inventors: Michihiro Sano, Yasuo Okuno
  • Patent number: 5156980
    Abstract: A method for producing a photodetector device includes depositing a plurality of spaced apart light absorption regions at intervals on a substrate, depositing an insulating layer on the substrate and covering the light absorption regions, producing a first conductivity type semiconductor layer on the insulating layer, and producing second conductivity type semiconductor regions by selectively diffusing impurities into regions of the first conductivity type semiconductor layer until the impurities reach the insulating layer.
    Type: Grant
    Filed: September 3, 1991
    Date of Patent: October 20, 1992
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Yoshihiro Hisa
  • Patent number: 5118365
    Abstract: A II-VI group compound crystal article comprises a substrate having a non-nucleation surface with smaller nucleation density (S.sub.NDS) and a nucleation surface (S.sub.NDL) which is arranged adjacent to said non-nucleation surface (S.sub.NDS), has a sufficiently small area for a crystal to grow only from a single nucleus and a larger nucleation density (ND.sub.L) than the nucleation density (ND.sub.S) of said non-nucleation surface (S.sub.NDS) and is comprised of an amorphous material, and a II-VI group compound monocrystal grown from said single nucleus on said substrate and spread on said non-nucleation surface (S.sub.NDS) beyond said nucleation surface (S.sub.NDL).
    Type: Grant
    Filed: March 4, 1991
    Date of Patent: June 2, 1992
    Assignee: Canon Kabushiki Kaisha
    Inventors: Hiroyuki Tokunaga, Takao Yonehara
  • Patent number: 5079192
    Abstract: The disclosure relates to a method of forming samples of alloys of group II-VI compositions having minimum dislocations, comprising the steps of providing a sample of a group II-VI compound, providing an enclosed ampoule having the sample at one end portion thereof and a group II element of the compound at an end portion remote from the one end portion, heating the sample to a temperature in the range of 350 to the melting temperature of the compound for about one hour while maintaining the group II element at a temperature more than C. below the sample temperature, heating the group II element to a temperature from about to about C. below the temperature of the sample while maintaining the sample at a temperature in the range of to C. both of about 15 minutes to about 4 hours, and then stoichiometrically annealing the sample at a temperature below C.
    Type: Grant
    Filed: August 24, 1990
    Date of Patent: January 7, 1992
    Assignee: Texas Instruments Incorporated
    Inventors: John H. Tregilgas, Dipankar Chandra
  • Patent number: 5028561
    Abstract: P-type doping of a molecular beam epitaxy (MBE) grown substrate composed of a Group II-VI combination is accomplished by forming a flux from a Group II-V combination, and applying the flux to the substrate at a pressure less than about 10.sup.-6 atmosphere. The Group II material is selected from Zn, Cd, Hg and Mg, the Group V material from As, Sb and P, and the Group VI material from S, Se and Te. The Group II-V dopant combination is preferably provided as a compound formed predominantly from the Group II material, and having the formulation X.sub.3 Y.sub.2, where X is the Group II material and Y is the Group V material. The doping concentration is controlled by controlling the temperature of the Group II-V combination. Metal vacancies in the lattice structure are tied up by the Group II constituent of the dopant combination, leaving the Group V dopant available to enter the Group VI sublattice and produce a p-type doping.
    Type: Grant
    Filed: June 15, 1989
    Date of Patent: July 2, 1991
    Assignee: Hughes Aircraft Company
    Inventors: G. Sanjiv Kamath, Owen K. Wu
  • Patent number: 5026661
    Abstract: A method of growing zinc chalcogenide in an atmosphere which contains the vapor of di-.pi.-cyclopentadienyl manganese or di-.pi.-alkyl cyclopentadienyl manganese that serves as a source of manganese. By growing zinc chalcogenide in the above atmosphere, there is obtained a manganese-doped zinc chalcogenide having a very high crystal quality, which is very suitable for the active layer in light emitting devices.
    Type: Grant
    Filed: October 13, 1989
    Date of Patent: June 25, 1991
    Assignee: Hitachi, Ltd.
    Inventors: Masahito Migita, Osamu Kanehisa, Masatoshi Shiiki, Hajime Yamamoto
  • Patent number: 4960728
    Abstract: Films of Hg.sub.1-x Cd.sub.x Te grown at low temperatures by MBE or MOCVD are homogenized by annealing at about C. for 1.25 to 3 hours.
    Type: Grant
    Filed: October 11, 1988
    Date of Patent: October 2, 1990
    Assignee: Texas Instruments Incorporated
    Inventors: Herbert F. Schaake, Roland J. Koestner
  • Patent number: 4952446
    Abstract: This invention relates to ultra-thin semiconductor films which can be in the submicron range formed from semiconductor materials such as silicon, germanium and gallium arsenide. The films are formed by creating a thin slightly damaged surface on the polished reverse side of a film (e.g., a wafer) of the semiconductor by low dose ion implantation and then etching the semiconductor material on the front side of the film to remove the semiconductor material down to the ion implanted damaged layer. While the implanted ions can be chosen from functionally desirable ions which upon annealing remain in the film to alter the original electrical characteristics, the implanted ions can also be chosen so that upon annealing, the resultant ultra-thin semiconductor film has the same electrical characteristics as the original semiconductor material.The ion implantation changes the etching characteristics of the ion implanted layer.
    Type: Grant
    Filed: December 14, 1988
    Date of Patent: August 28, 1990
    Assignee: Cornell Research Foundation, Inc.
    Inventors: Kevin C. Lee, Charles A. Lee, John Silcox
  • Patent number: 4950621
    Abstract: A method of growing an epitaxial crystalline layer on a substrate which comprises the steps of(a) providing in the reaction zone of a reaction vessel a heated substrate(b) establishing a gas stream, provided by a carrier gas which gas stream comprises at least 50% by volume of a gas which suppresses the homogeneous nucleation of particles in the vapor phase which contains, in the vapor phase, at least one alkyl of an element selected from Group 15 and Group 16 of the Periodic Table,(c) passing the gas stream through the reaction zone into contact with the heated substrate, and(d) irradiating at least a major part of the surface of the substrate with electromagnetic radiation to provide photolytic decomposition of the at least one alkyl and consequential epitaxial deposition of the layer containing the said element across at least a major part of the surface of the substrate.
    Type: Grant
    Filed: November 6, 1985
    Date of Patent: August 21, 1990
    Assignee: Secretary of the State for Defence in Her Majesty's Government of the United Kingdom of Great Britain and Northern Ireland
    Inventors: Stuart J. Irvine, John B. Mullin, Jean Giess
  • Patent number: 4950615
    Abstract: A technique is disclosed forming thin films (13) of group IIB metal-telluride, such as Cd.sub.x Zn.sub.1-x Te (0.ltoreq.x.ltoreq.1), on a substrate (10) which comprises depositing Te (18) and at least one of the elements (19) of Cd, Zn, and Hg onto a substrate and then heating the elements to form the telluride. A technique is also provided for doping this material by chemically forming a thin layer of a dopant on the surface of the unreacted elements and then heating the elements along with the layer of dopant.
    Type: Grant
    Filed: February 6, 1989
    Date of Patent: August 21, 1990
    Assignee: International Solar Electric Technology, Inc.
    Inventors: Bulent M. Basol, Vijay K. Kapur
  • Patent number: 4920068
    Abstract: A process to produce one or more Group II-VI epitazial layers over a crystalline substrate by directing flows of one or more Group II components and a Group VI metalorganic vapor to a heated substrate whereby the vapors thereby react to form the epitaxial layer(s), is improved in terms of lower reaction temperatures and higher product quality if, as the Group VI metalorganic vapor source, there is used a tellurium compound of the formula: ##STR1## wherein R.sup.1 and R.sup.2 are, independently, hydrogen or C.sub.1 -C.sub.4 alkyl, preferably, hydrogen.
    Type: Grant
    Filed: April 2, 1986
    Date of Patent: April 24, 1990
    Assignee: American Cyanamid Company
    Inventors: Donald Valentine, Jr., Duncan W. Brown
  • Patent number: 4910154
    Abstract: The manufacture of monolithic HgCdTe detectors and Si circuitry in an IR focal plane array is achieved by forming a protective layer of SiO.sub.2 or SiN.sub.x on a silicon wafer containing silicon circuits, etching steep-wall recesses into the wafer, selectively depositing epitaxial single-crystal layers of GaAs, CdTe, and HgCdTe in the recesses fabricating HgCdTe IR arrays, and depositing appropriate insulating and conductive interconnection patterns to interconnect the Si devices with one another and the HgCdTe devices with the Si devices. Little or no GaAs, CdTe, and HgCdTe grows on the SiO.sub.2 or SiN.sub.x outside the recesses. Since material grown outside the recess is polycrystalline, it is easily chemomechanically removed.
    Type: Grant
    Filed: December 23, 1988
    Date of Patent: March 20, 1990
    Assignee: Ford Aerospace Corporation
    Inventors: Ken Zanio, Ross C. Bean
  • Patent number: 4908329
    Abstract: A process for the formation of a functional deposited film containing atoms belonging to the group II and VI of the periodical table as the main constituent atoms by introducing, into a film forming space for forming a deposited film on a substrate disposed therein, a group II compound (1) and a group VI compound (2) as the film-forming raw material and, if required, a compound (3) containing an element capable of controlling valence electrons for the deposited film as the constituent element each in a gaseous state, or in a state where at least one of such compounds is previously activated in an activation space disposed separately from the film forming space, while forming hydrogen atoms in an excited state which cause chemical reaction with at least one of the compounds (1), (2) and (3) in the gaseous state or in the activated state in an activation space different from the film forming space and introducing them into the film-forming space, thereby forming the functional deposited film on the substrate, w
    Type: Grant
    Filed: January 27, 1989
    Date of Patent: March 13, 1990
    Assignee: Canon Kabushiki Kaisha
    Inventors: Masahiro Kanai, Tsutomu Murakami, Takayoshi Arai, Soichiro Kawakami
  • Patent number: 4904618
    Abstract: Non-equilibrium impurity incorporation is used to dope hard-to-dope crystals of wide band gap semiconductors, such as zinc selenide and zinc telluride. This involves incorporating into the crystal a compensating pair of primary and secondary dopants, thereby to increase the solubility of either dopant alone in the crystals. Thereafter, the secondary more mobile dopant is removed preferentially, leaving the primary dopant predominant. This technique is used to dope zinc selenide p-type by the use of nitrogen as the primary dopant and lithium as the secondary dopant.
    Type: Grant
    Filed: August 22, 1988
    Date of Patent: February 27, 1990
    Inventor: Gertrude F. Neumark
  • Patent number: 4804638
    Abstract: A method for growing a Group II-IV epitaxial layer over a substrate is described. The method includes the steps of directing a plurality of vapor flows towards the substrate, including a Group II organic vapor, a Group VI organic vapor, and a Group II elemental mercury vapor. At least one of the Group II organic vapor and Group VI organic vapor has organic groups which sterically repulse the second one of the Group II and Group VI organic vapors or which provide electron transfer to the Group II atom or electron withdrawal from the Group VI atom. With the particular arrangements described, it is believed that substantially independent pyrolsis of the Group II organic vapor is provided over the growth region of the substrate, and accordingly, Group II depletions such as cadmium depletion in the epitaxial films provided over the substrate is substantially reduced.
    Type: Grant
    Filed: March 28, 1988
    Date of Patent: February 14, 1989
    Assignee: Raytheon Company
    Inventors: William E. Hoke, Lindley T. Specht
  • Patent number: 4743310
    Abstract: A layer of HgCdTe (15) is epitaxially grown on a crystalline support (10). A single crystal CdTe substrate (5) is first epitaxially grown to a thickness of between 1 micron and 5 microns onto the support (10). Then a HgTe source (3) is spaced from the CdTe substrate (5) a distance of between 0.1 mm and 10 mm. The substrate (5) and source (3) are heated together in a thermally insulating, reusable ampoule (17) within a growth temperature range of between C. and C. for a growth time of between 5 minutes and 13 hours. In a first growth step embodiment, the source (3) and substrate (5) are non-isothermal. In a second growth step embodiment, the source (3) and substrate (5) are isothermal. Then an optional interdiffusion step is performed, in which the source (3) and substrate (5) are cooled within a temperature range of between C. and C. for a time of between 1 hour and 16 hours.
    Type: Grant
    Filed: February 2, 1987
    Date of Patent: May 10, 1988
    Assignee: Ford Aerospace & Communications Corporation
    Inventors: Robert E. Kay, Hakchill Chan, Fred Ju, Burton A. Bray
  • Patent number: 4695857
    Abstract: The superlattice type semiconductor material has a multilayered structure of first layers of semiconductor containing impurities and having a thickness thinner than electron or hole wavelength and second layers of semiconductor free from impurities or insulator having such a thickness that electrons or holes may penetrate by tunneling effect, the first and second layers being alternately piled. Electrons or holes distribute uniformly over the entire of the multilayered structure to show a property of uniform semiconductor material.
    Type: Grant
    Filed: June 25, 1984
    Date of Patent: September 22, 1987
    Assignee: NEC Corporation
    Inventors: Toshio Baba, Takashi Mizutani, Masaki Ogawa
  • Patent number: 4642142
    Abstract: Mercury cadmium telluride (Hg.sub.1-x Cd.sub.x Te) is formed from an atmosphere of mercury vapor maintained at a temperature of within about C. of a desired temperature which contacts a liquid cadmium-tellurium solution with or without mercury maintained at a temperature within about C. of a desired temperature. The resultant mercury-cadmium-tellurium solution then is cooled to solidification.
    Type: Grant
    Filed: August 28, 1985
    Date of Patent: February 10, 1987
    Assignee: Massachusetts Institute of Technology
    Inventor: Theodore C. Harman