Guard Rings And Cmos Patents (Class 148/DIG70)
  • Patent number: 5963798
    Abstract: A method for fabricating a CMOS device having BILLI (buried implanted layers for lateral isolation) structure capable of effectively preventing latch-up is disclosed, having the following steps. A mask pattern is formed on the semiconductor substrate of a predetermined conductivity type to expose a region where the MOS transistor, having a same conductivity type as that of the substrate, is to be formed wherein the mask pattern has a vertical boundary face having a gradual slope. A buried layer is then formed in the form of island by ion-implanting the impurity ions into the substrate to pass through the mask pattern, the buried layer having a same conductivity type as that of the substrate, and being formed to be continuous under the vertical boundary face of the mask pattern.
    Type: Grant
    Filed: June 25, 1997
    Date of Patent: October 5, 1999
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventors: Kwang-Soo Kim, Kyung-Dong Yoo
  • Patent number: 5814552
    Abstract: A method of fabricating high step alignment marks on a twin-well integrated circuit. An alignment mark photoresist pattern is formed overlaying the nitride layer using lithography technique. The nitride layer is partially etched to form a nitride alignment pattern using the alignment mark photoresist pattern as a mask. After the formation of N-well and P-well regions using lithography technique, the N-doped and P-doped impurities are subject to a thermally drive in process to activate and form N-well and P-well regions, respectively. At the same time, the pad oxide layer overlaying the N-well and P-well regions and the region not covered by the nitride alignment pattern is converted to a thermal oxide layer. The thermal oxide layer can be removed to reveal a recessed portion on the surface of the P-type silicon substrate, whereby the thickness of the nitride layer plus the depth of the recessed portion causes high step alignment marks to be formed.
    Type: Grant
    Filed: November 1, 1996
    Date of Patent: September 29, 1998
    Assignee: Holtek Microelectronics, Inc.
    Inventor: Bing-Yau Lu
  • Patent number: 5688710
    Abstract: A method of fabricating a twin-well integrated circuit device to implant the dopants directly through the nitride layer including steps of: The pad oxide layer and nitride layer are formed on a P-type semiconductor silicon wafer. Then, the alignment mark photoresist pattern is formed by the conventional lithography technique, where the alignment mark region is in clear field, while other regions are in dark field. Next, the nitride layer is patterned by plasma-etching technique to form the nitride alignment mark. The N-well region is formed by lithography and ion-implantation techniques. Thereafter, the P-well region is formed by lithography and ion-implantation methods again. Next, the active device region photoresist is formed by lithography technique. The nitride layer is partially etched to open the windows by plasma-etching technique. The P-well region photoresist is then formed, followed by the deep-implantation process.
    Type: Grant
    Filed: November 27, 1996
    Date of Patent: November 18, 1997
    Assignee: Holtek Microelectronics, Inc.
    Inventor: Bing-Yau Lu
  • Patent number: 5525535
    Abstract: A method of forming doped well regions for FETs and doped field regions for channel stops to prevent surface inversion under the field oxide was achieved using a single ion implantation. The method involves forming a patterned silicon oxide layer over the field regions by selective deposition using liquid phase deposition (LPD) and a patterned photoresist mask. An ion implantation through the thick LPD silicon oxide layer over the field regions and through a thinner silicon nitride layer over the well regions resulted in a shallow doped field region and a deep doped well region. After removing the LPD oxide in HF, LOCOS was used to form the field oxide drive-in the dopant and anneal out the implant damage. After removing the silicon nitride layer over the well regions, gate oxides, polysilicon gate electrodes, and source/drains areas are formed to complete the FETs. The LPD process resulted in a doped field region self-aligned to a doped well region that required fewer masking and implant steps.
    Type: Grant
    Filed: July 26, 1995
    Date of Patent: June 11, 1996
    Assignee: United Microelectronics Corporation
    Inventor: Gary Hong
  • Patent number: 5411899
    Abstract: A method for forming a twin tub semiconductor integrated circuit is disclosed. A portion of a semiconductor substrate is masked by oxide, nitride and photoresist. P-type dopant is directed towards the other portion of the substrate. Subsequently, the photoresist is removed and a protective oxide is grown over the p-tub, thereby driving the dopant into the substrate. Next, an n-type ion implantation is performed to create the n-tub. The n-type ions are directed at the substrate at an angle which is away from normal incidence. The angular direction of the n-type dopants permits the use of smaller screen oxides over the n-tub and smaller protective oxides over the already-formed p-tub. When all of the protective oxides have been removed, the inventive technique provides a twin tub substrate having a comparatively smooth upper surface.
    Type: Grant
    Filed: October 13, 1993
    Date of Patent: May 2, 1995
    Assignee: AT&T Corp.
    Inventors: Kuo-Hua Lee, Chen-Hua D. Yu
  • Patent number: 5407849
    Abstract: A method of threshold adjust implantation which involves the implanting of some of the PMOS FETs' channels on a CMOS circuit so the PMOS FETs have a threshold voltage of substantially zero volts, the implanting involves an additional implantation of ions into the PMOS FETs' channels in addition to the implantation required to raise the PMOS FETs' threshold voltage from the native threshold voltage to the normal threshold voltage.
    Type: Grant
    Filed: June 23, 1992
    Date of Patent: April 18, 1995
    Assignee: IMP, Inc.
    Inventors: Moiz Khambaty, Corey D. Petersen
  • Patent number: 5372955
    Abstract: A method of manufacture of a MOSFET device with a predetermined light positive or negative doping comprises forming a first mask upon said substrate. Dopant of a predetermined positive or negative variety is implanted through the mask. A second mask is formed over the openings in the first mask. The first mask is removed. Dopant of the opposite positive or negative variety is implanted into the openings in the second mask. The process forms a pattern of positive and negative wells in the substrate, and forms a guard ring of an opposite doping variety from the wells being protected formed in the substrate.
    Type: Grant
    Filed: August 2, 1993
    Date of Patent: December 13, 1994
    Assignee: United Microelectronics Corporation
    Inventor: Ming-Tzong Yang
  • Patent number: 5292671
    Abstract: In a method of manufacturing CMOS transistors, a well that is of a second conductivity type is formed in a semiconductor substrate of a first conductivity type and is surrounded by a high concentration buried layer of the first conductivity type which completely extends around and below the well, and which also constitutes wells of the first conductivity type. The high-concentration buried layer is formed by a self-aligned process, and the potential of the buried layer can be easily fixed from the top of the semiconductor substrate so that a high degree of resistance is obtained to CMOS latch-up.
    Type: Grant
    Filed: July 29, 1992
    Date of Patent: March 8, 1994
    Assignee: Matsushita Electric Industrial, Co., Ltd.
    Inventor: Shinji Odanaka
  • Patent number: 5252510
    Abstract: A method for manufacturing a CMOS semiconductor device having twin wells is disclosed. The method of manufacturing the CMOS device comprises the following. A silicon substrate is provided. A thick oxide layer is deposited and a first photoresist layer is coated sequentially on the silicon substrate. Then an N-well mask pattern is formed by removing a portion of the first photoresist layer, thereby defining an alignment-key region and N-well region and forming a thin oxide layer on such regions. An N-type impurity implantion process is then performed through exposed portions of the thin oxide layer into the silicon substrate, and the first photoresist layer portions remaining on the thick oxide layer are removed, to thereby expose the entire surface of the thick oxide layer. A second photoresist layer is coated on the entire surface of the oxide layer.
    Type: Grant
    Filed: April 29, 1992
    Date of Patent: October 12, 1993
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventors: Dai H. Lee, Hyung L. Ji
  • Patent number: 5130271
    Abstract: A method of manufacturing a semiconductor device includes the steps of forming an insulating film on a semiconductor substrate, selectively removing the insulating film to expose a surface of the semiconductor substrate, doping an impurity in the semiconductor substrate using the selectively formed insulating film as a mask, thereby forming an impurity region of one conductivity type, forming a photoresist film on the entire surface of the semiconductor substrate in an area including the insulating film used as the mask, selectively removing only the photoresist film on the insulating film to leave the photoresist film on only the impurity region of one conductivity type, removing the insulating film at a portion from which the photoresist film is removed, thereby exposing the surface of the semiconductor substrate, and doping an impurity using a remaining photoresist as a mask to form an impurity region of the other conductivity type in the exposed surface of the semiconductor substrate.
    Type: Grant
    Filed: October 9, 1990
    Date of Patent: July 14, 1992
    Assignee: NEC Corporation
    Inventor: Takahisa Migita
  • Patent number: 5045495
    Abstract: A method of forming a well of one conductivity type in a silicon substrate having a first surface region thereof which is doped with a dopant of one conductivity type and a second surface region thereof which is doped with a dopant of opposite conductivity type. The first and second regions are covered by respective first and second portions of an oxide layer which has been grown on the silicon substrate, the first portion being thicker than the second portion. The substrate is oxidized thereby to increase the thickness of the oxide layer such that the difference in thickness between the first and second portions is reduced. The substrate is also heated to cause diffusion of the dopant of one conductivity type thereby to form a well and of the dopant of opposite conductivity type down into the substrate. The heating step is carried out before, during or after the oxidizing step.
    Type: Grant
    Filed: March 30, 1990
    Date of Patent: September 3, 1991
    Assignee: Inmos Limited
    Inventors: Martin J. Teague, Andrew D. Strachan, Martin A. Henry
  • Patent number: 5028548
    Abstract: A method of manufacturing a semiconductor device of the "planar" type comprising a highly doped substrate having a doping concentration c.sub.o and an epitaxial surface layer having a carrier concentration c<c.sub.o, in which are formed a main pn junction having a depth x.sub.j and a structure of floating guard rings. According to the invention, this device also includes between the substrate and the epitaxial surface layer, a second epitaxial layer having a carrier concentration c' such that c.sub.o >c'>c. This permits the production of devices with different maximum operating voltages using the same configuration of guard rings.
    Type: Grant
    Filed: June 26, 1990
    Date of Patent: July 2, 1991
    Assignee: U.S. Philips Corp.
    Inventor: Minh-Chau Nguyen
  • Patent number: 4925806
    Abstract: A method for making a dopant well in a semiconductor substrate, wherein a dopant is implanted directly into an exposed surface of a semiconductor substrate through an opening in a dopant-absorbing coating and the substrate is heated to drive the implanted dopant further into the substrate. The method requires fewer steps than the conventional method, and is particularly applicable in the fabrication of CMOS devices.
    Type: Grant
    Filed: March 17, 1988
    Date of Patent: May 15, 1990
    Assignee: Northern Telecom Limited
    Inventor: John K. Grosse
  • Patent number: 4876209
    Abstract: The disclosed invention as directed to a semiconductor material avalanche photodiode of a separate multiplication and absorption region heterostructure design (SAM-APD). The improved SAM-APD of this invention is characterized by a plurality of floating guard rings which are separated about a central region and doped in the opposite high concentration from that of the multiplication region in which they are positioned. These rings float in the sense that they have no contact with the metalized p-contact of the photodiode; and, therefore, no direct contact with the current source. This structure results in an enhanced avalanche effect in the central region with limited edge breakdown undesirable consequences.
    Type: Grant
    Filed: May 12, 1989
    Date of Patent: October 24, 1989
    Assignee: U.S.C.
    Inventor: Stephen R. Forrest
  • Patent number: 4682408
    Abstract: A process is described for forming semiconductor device which include forming step of coating of silicon oxide derivative before ion implanting step: The coating prevents unnecessary extention of channel stop regions thus produces high speed and high current drive ability of produced semiconductor device.
    Type: Grant
    Filed: April 1, 1986
    Date of Patent: July 28, 1987
    Assignee: Matsushita Electronics Corporation
    Inventor: Koji Takebayashi
  • Patent number: 4593459
    Abstract: Method of forming a substrate for fabricating CMOS FET's by forming sections of N and P-type conductivity in a body of silicon. Grooves are etched in the N and P-type sections to produce N and P-type sectors encircled by grooves. The surfaces of the grooves are oxidized, the grooves are filled with polycrystalline silicon, and exposed surfaces of the polycrystalline silicon are oxidized to form barriers which encircle the sectors and electrically isolate them. Shallow trenches are etched in regions of the body outside the N and P-type sectors and the trenches are filled with regions of silicon dioxide. A pair of complementary FET's are fabricated in the two sectors and a metal interconnection between them overlies a portion of a region of silicon dioxide.
    Type: Grant
    Filed: December 28, 1984
    Date of Patent: June 10, 1986
    Assignee: GTE Laboratories Incorporated
    Inventors: Paul E. Poppert, Marvin J. Tabasky, Eugene O. Degenkolb
  • Patent number: 4586238
    Abstract: The present invention deals with a semiconductor memory circuit device, in which a memory array portion of a rectangular shape consisting of semiconductor non-volatile memory elements is formed on a main surface of the semiconductor substrate, a low voltage driver circuit (decoder) is formed along a side of the memory array portion, and a high voltage driver circuit is formed along an opposite side of the memory array portion. This permits a reduction in word line length and avoids crossing of the word lines to permit increased operation speed and, particularly, increased reading speed.
    Type: Grant
    Filed: April 21, 1983
    Date of Patent: May 6, 1986
    Assignee: Hitachi, Ltd.
    Inventors: Yuji Yatsuda, Takaaki Hagiwara, Ryuji Kondo, Shinichi Minami, Yokichi Itoh
  • Patent number: 4559694
    Abstract: A method is provided for manufacturing a reference voltage generator device which detects a voltage corresponding to an energy gap of a semiconductor, or a voltage of a value close thereto, or a voltage based on an energy level of a semiconductor, and generates the detected voltage as a reference voltage. The reference voltage is generated by detecting a difference of threshold voltages of first and second insulated gate field-effect transistors (IGFETs). Gate electrodes of the first and second IGFETs are formed on gate insulating films which are formed on different surface areas of an identical semiconductor substrate under substantially the same conditions.
    Type: Grant
    Filed: April 12, 1983
    Date of Patent: December 24, 1985
    Assignee: Hitachi, Ltd.
    Inventors: Kanji Yoh, Osamu Yamashiro, Satoshi Meguro
  • Patent number: 4554726
    Abstract: To minimize the number of independent masking operations in the manufacture of a CMOS integrated circuit device using twin tub technology, the n-tub is made by separate phosphorus and arsenic implants through a common mask, and the p-tub is made by two separate boron implants through a common mask, complementary to that used for forming the n-tub. One of the boron implants occurs before, the other after, the drive-in heating step. After tub formation, further movement of the implanted ions is kept small by use of a high pressure process for growing the field oxide and by only limited further heating. Transistors are then formed in the tubs.
    Type: Grant
    Filed: April 17, 1984
    Date of Patent: November 26, 1985
    Assignee: AT&T Bell Laboratories
    Inventors: Steven J. Hillenius, Louis C. Parrillo