Heating, Selective Patents (Class 148/DIG71)
  • Patent number: 5870021
    Abstract: A control element for a magnetomechanical EAS marker is formed of an amorphous metalloid that has been annealed so as to be at least partially crystallized while remaining substantially flat. The annealing is preferably a two-stage process applied to induce semi-hard magnetic characteristics in an amorphous metallic material that is magnetically soft as cast. The two stages include a first stage in which the material is annealed for at least one hour at a temperature that is below a crystallization temperature of the material. The first stage results in a reduction in the volume of the material. The second stage is carried out at a temperature that is above the crystallization temperature and for a time sufficient to crystallize the bulk of the material and give it semi-hard magnetic properties. The two-stage annealing process prevents deformation of the material which has resulted from conventional crystallization processes.
    Type: Grant
    Filed: July 1, 1996
    Date of Patent: February 9, 1999
    Assignee: Sensormatic Electronics Corporation
    Inventor: Dennis Michael Gadonniex
  • Patent number: 5563094
    Abstract: In situ removal of selected or patterned portions of semiconductor layers is accomplished by induced evaporation enhancement to form reversed bias current confinement structures in semiconductor devices, such as heterostructure lasers and array lasers.
    Type: Grant
    Filed: September 6, 1990
    Date of Patent: October 8, 1996
    Assignee: Xerox Corporation
    Inventors: Thomas L. Paoli, John E. Epler
  • Patent number: 5519193
    Abstract: The described invention is directed to microwave methods for burning-in, electrical stressing, thermal stressing and reducing rectifying junction leakage current in fully processed semiconductor chips individually and at wafer level, as well as burning in and stressing semiconductor chip packaging substrates and the combination of a semiconductor chip mounted onto a semiconductor chip packaging substrate. Microwaves burn-in devices in a substantially shorter period of time than conventional burn-in techniques and avoid the need for special workpiece holders which are required by conventional stress and burn-in techniques. Additionally, microwave methods are described for reducing the leakage current of recitfying junctions, such as PN junctions and Schottky barrier diode junctions of semiconductor devices on fully processed semiconductor chips and wafers.
    Type: Grant
    Filed: October 27, 1992
    Date of Patent: May 21, 1996
    Assignee: International Business Machines Corporation
    Inventors: Peter E. Freiermuth, Kathleen S. Ginn, Jeffrey A. Haley, Susan J. Lamaire, David A. Lewis, Gavin T. Mills, Timothy A. Redmond, Yuk L. Tsang, Joseph J. Van Horn, Alfred Viehbeck, George F. Walker, Jer-Ming Yang, Clarence S. Long
  • Patent number: 5409867
    Abstract: After partially crystallizing an amorphous semiconductor deposited on a substrate, the irradition of infrared ray is conducted to grow a polycrystalline semiconductor layer on the crystallized region and the amorphous region by thermal decomposition while the temperature of the crystallized region is kept higher than that of the amorphous region. Since the polycystalline layer is formed of polycystalline grains grown from nuclei of the cystallized region, the crystal grain thereof is large.
    Type: Grant
    Filed: June 15, 1994
    Date of Patent: April 25, 1995
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Akihiko Asano
  • Patent number: 5284795
    Abstract: A method of processing a semiconductor device in which a microwave field is generated to surround the semiconductor device while a focussed electron beam or ion beam is applied to the substrate of the device whereby the presence of the electron or ion beam creates a conductive region which increases the microwave field intensity in that region, so that the intensified microwave field creates a local heating effect in the substrate to perform a local annealing action.
    Type: Grant
    Filed: December 9, 1991
    Date of Patent: February 8, 1994
    Assignee: Motorola, Inc.
    Inventors: Henri Gay, Denis Griot, Irenee Pages
  • Patent number: 5153148
    Abstract: The invention is directed to a semiconductor laser wherein the first embodiment is characterized in that the first upper portion cladding layer is assumed to be a double layer construction, the upper layer portion is assumed to be higher in carrier concentration than the lower layer portion, the series resistance component is restrained, so that the sequential direction voltage V.sub.F may be lowered without damaging the other characteristics such as oscillation start current I th and so on.
    Type: Grant
    Filed: October 30, 1990
    Date of Patent: October 6, 1992
    Assignee: Rohm Co., Ltd.
    Inventors: Hajime Sakiyama, Haruo Tanaka, Masato Mushiage
  • Patent number: 5110404
    Abstract: In a method for heat process of silicon, a single crystal silicon produced by the Czochralski process is thermally processed at a low temperature ranging from 400.degree. C. to 550.degree. C. Outside this temperature range, the oxygen precipitate is not adequate. The result is that a predetermined oxygen precipitate can be obtained uniformly in the crystal growth direction without any reduction especially at the crystal bottom part. The resulting silicon is particularly suitable for manufacture of LSI.
    Type: Grant
    Filed: March 21, 1990
    Date of Patent: May 5, 1992
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Izumi Fusegawa, Hirotoshi Yamagishi, Takao Abe
  • Patent number: 5110758
    Abstract: An improved method of trimming resistors by metal migration by local heating (18,21) of the resistor (23) to allow a reduced level of electric current to be used. The resistor is then trimmed by application of short pulses of high current causing metal migration (22). Each pulse decreases the resistance progressively until a desired final value is achieved. The reduced level of current of the improved method requires a reduced voltage across the resistor thus extending the earlier method to allow higher valued resistors, or lower breakdown voltages. The localized heating (18,21) is also used to anneal the migrated metal after trimming to increase the long term stability of the resistor (23). The intensity of the localized heating (18,21) can be varied to induce a desired shape in the migrated metal (22).
    Type: Grant
    Filed: June 3, 1991
    Date of Patent: May 5, 1992
    Assignee: Motorola, Inc.
    Inventor: Ira E. Baskett
  • Patent number: 5079187
    Abstract: A method for processing semiconductor material for annealing or circuitizing purposes, includes establishing a high intensity light which is controlled at a high repetition rate, and exposing it toward the surface of the semiconductor material to process it in an improved manner. The high speed light is directed transversely to the surface of the material to be processed, only to a shallow depth.
    Type: Grant
    Filed: May 4, 1989
    Date of Patent: January 7, 1992
    Assignee: The Regents of the University of California
    Inventors: John F. Asmus, Ralph H. Lovberg
  • Patent number: 5066610
    Abstract: Wetting of encapsulated silicon-on-insulator (SOI) films during a zone-melting recrystallization (ZMR) process is enhanced by a high temperature anneal of the SOI structure in a reactive nitrogen-containing ambient to introduce nitrogen atoms to the polysilicon/silicon dioxide cap interface. The technique is not only more effective in present in cap fracture and enhancing crystal quality but is also susceptible to batch processing with noncritical parameters in a highly efficient, uniform manner. Preferably, the cap is exposed to 100% ammonia at 1100.degree. C. for one to three hours followed by a pure oxygen purge for twenty minutes. The ammonia atmosphere is reintroduced at the same temperature for another one to three hour period before ZMR. The process is believed to result in less than a half monolayer of nitrogen at the interior cap interface thereby significantly lowering the contact angle and improving the wetting character of the SOI structure.
    Type: Grant
    Filed: September 22, 1989
    Date of Patent: November 19, 1991
    Assignee: Massachusetts Institute of Technology
    Inventors: Chenson K. Chen, Bor-Yeu Tsaur
  • Patent number: 5024967
    Abstract: A process is described for making semiconductor devices with highly controlled doping profiles. The process involves minimizing or eliminating segregation effects caused by surface electric fields created by Fermi-level pinning. These electric fields act on dopant ions and cause migration from the original deposition site of the doplant ions. Dopant ions are effectively shielded from the surface electric fields by illumination of the growth surfaces and by background doping. Also, certain crystallographic directions in certain semiconductors do not show Fermi-level pinning and lower growth temperatures retard or eliminate segregation effects. Devices are described which exhibit enhanced characteristics with highly accurate and other very narrow doping profiles.
    Type: Grant
    Filed: June 30, 1989
    Date of Patent: June 18, 1991
    Assignee: AT&T Bell Laboratories
    Inventors: Rose F. Kopf, J. M. Kuo, Henry S. Luftman, Erdmann F. Schubert
  • Patent number: 5011794
    Abstract: This invention is directed to the fabrication of semiconductor devices, especially those comprising III-V and II-VI compound semiconductor materials, and involves Rapid Thermal Annealing (RTA) of semiconductor wafers, especially those implanted with a dopant(s). The invention is also concerned with a black-box implement used in combination with the RTA. The process includes enclosing a wafer to be annealed within a "black-box" comprising components of a black body material and subjecting the black box with the wafer therein to an RTA.
    Type: Grant
    Filed: May 1, 1989
    Date of Patent: April 30, 1991
    Assignee: AT&T Bell Laboratories
    Inventors: Karen A. Grim, Shobha Singh, LeGrand G. Van Uitert, George J. Zydzik
  • Patent number: 4981549
    Abstract: A silicon single-crystal growing method is disclosed which immerses a seed crystal in a silicon melt and pulls the seed crystal from the melt to thereby grow a silicon single-crystal, and in which the dwelling time of the silicon single-crystal, which is being pulled in a temperature range of between 1,050.degree. to 850.degree. C., is set to be no longer than 140 min. The apparatus suitable for practicing the above method has a crucible, a pulling mechanism, and a temperature control shell. The temperature control shell is located above the crucible for cooling said silicon single-crystal at a cooling rate such that the dwelling time of said silicon single-crystal, which is being pulled in a temperature range of between 1,050.degree. to 850.degree. C., is not longer than 140 min.
    Type: Grant
    Filed: February 22, 1989
    Date of Patent: January 1, 1991
    Assignees: Mitsubishi Kinzoku Kabushiki Kaisha, Japan Silicon Co., Ltd.
    Inventors: Ichiro Yamashita, Koutaro Shimizu, Yoshiaki Banba, Yasushi Shimanuki, Akira Higuchi, Hisashi Furuya
  • Patent number: 4962057
    Abstract: In situ evaporation of selected surface regions or layers of compound semiconductors is accomplished without breaking the growth system environment employing photo induced evaporation enhancement in chemical vapor deposition epitaxy. Intense radiation from an energy source desorbs or causes evaporation of consecutive monolayers of atoms or combined atoms from the surface crystal by thermal evaporation. The desorbed atoms from the growth surface are removed atomic layer by atomic layer in a fairly uniform and systematic manner and may be characterized as "monolayer peeling" resulting in a morphology that is sculpturally smooth and molecularly continuous. In this sense, the method of this invention is analogous to erasing or the etching of crystal material and is the antithesis to laser deposition patterning wherein erasure after growth or reduced rate of growth during growth provide "negative growth patterning".
    Type: Grant
    Filed: October 13, 1988
    Date of Patent: October 9, 1990
    Assignee: Xerox Corporation
    Inventors: John E. Epler, David W. Treat, Thomas L. Paoli
  • Patent number: 4960721
    Abstract: A method of heat treatment for purifying a Groups II-VI compound semiconductor and for producing a purity Groups II-VI compound semiconductor crystal using a sealed container placed a Groups II-VI compound semiconductor crystal as a raw material is disclosed. The process includes heating means applied to the sealed container having a temperature difference which has a high-temperature zone and a low-temperature zone into the sealed container, placing the raw material into the high-temperature zone of the sealed container, using a heat atom making an atmosphere of either a Group II element or a Group VI element, or a mixed atmosphere of either which is necessary to treat the Groups II-VI compound semiconductor into the sealed container, and using a Groups II-VI compound semiconductor as raw material.
    Type: Grant
    Filed: November 9, 1988
    Date of Patent: October 2, 1990
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazutaka Terashima, Masaru Kawachi, Hiroaki Yoshida
  • Patent number: 4957880
    Abstract: In the production method of a semiconductor device, a connection layer is formed on an insulating layer according to two steps of irradiating, in the atmosphere of a reaction gas, a region in which the connection layer is to be formed selectively by light having a wavelength in a range of from 200 to 1000 nm, and depositing selectively a connection layer forming substrate by a CVD method in the light irradiated region until a desired thickness of the substance is obtained.
    Type: Grant
    Filed: April 28, 1989
    Date of Patent: September 18, 1990
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hitoshi Itoh, Takahiko Moriya
  • Patent number: 4933299
    Abstract: MOVPE growth and photoetching are integrated into a unified sequence which is carried out without removing a workpiece from a MOVPE reactor. Growth may be carried out before, after or before and after the etching.To prevent pattern broadening by diffussion of the active species the substrate is preferably protected by a fugitive coating which is removed by the illumination. Native oxide coatings are particularly suitable for InGaAsP substrates. These are conveniently applied for exposing to substrate to 20.degree./o O.sub.2 +80.degree./oN.sub.2 for about 3 minutes at 450.degree. C.
    Type: Grant
    Filed: March 13, 1989
    Date of Patent: June 12, 1990
    Assignee: British Telecommunications public limited company
    Inventor: Kenneth Durose
  • Patent number: 4916809
    Abstract: A method for creating a programmable connection by a laser beam in superimposed conductors of an interconnect system of an integrated circuit is provided wherein each of the conductors is formed of a metal strip provided with an upper and a lower film of a material having a melting point substantially higher than a melting point of said metal strip. The conductors are separated by a dielectric layer and the upper conductor is covered by an insulating passivation layer. The connection is effected through an opening in the insulating layer, the upper conductor, the dielectric layer, and at least a portion of said lower conductor. The method for creating the connection consists of applying at least a first laser beam pulse to make an initial opening in at least said insulating layer; and selectively controlling one or more of the parameters of the laser beam, such as power, diameter, number of pulses and duration of pulses.
    Type: Grant
    Filed: August 17, 1988
    Date of Patent: April 17, 1990
    Assignee: Bull S.A.
    Inventors: Alain Boudou, Marie-Francoise Bonnal
  • Patent number: 4902642
    Abstract: The present invention provides products and methods of forming an epitaxial silicon layer on an implanted buried insulator silicon on insulator structure (10). A silicon film (16) is pre-treated to remove residual oxide and surface damage layers, but in such a way as to not damage the silicon film (16) or insulating layer (14) below the silicon film (16). A layer of amorphous silicon (18) is formed on the silicon film (16) in processes to avoid formation of polycrystalline silicon, and also to avoid damage to the silicon film (16). The layer of amorphous silicon (18) is annealed to form an epitaxial layer of single crystalline silicon (20).
    Type: Grant
    Filed: August 24, 1988
    Date of Patent: February 20, 1990
    Assignee: Texas Instruments, Incorporated
    Inventors: Bor-Yen Mao, Richard L. Yeakley
  • Patent number: 4891335
    Abstract: A reaction system and process for uniformly heating semiconductor substrates and a device for supporting the same and direct conductive heating of IC wafers within a reactor are described. The substrate is held in direct contact with the heating source positioned within the reactor. The heat source is a thermal delivery module made of material such as solid silicon carbide, or high temperature material containing resistive heating elements. The heat is uniformly transferred to the walls of the module by a molten metal having a low melting point and high boiling point such as essentially indium or bismuth or a eutectic or indium and bismuth.
    Type: Grant
    Filed: September 29, 1988
    Date of Patent: January 2, 1990
    Assignee: Advantage Production Technology Inc.
    Inventor: Michael A. McNeilly
  • Patent number: 4888302
    Abstract: A defect free monocrystalline layer of silicon on an insulator is produced by forming a thin layer of silicon dioxide on a monocrystalline silicon substrate, forming a thin layer of polycrystalline or amorphous silicon on the silicon dioxide layer and focussing two beams from lamps on the thin silicon layer to form a line image providing a melt zone surrounded by two narrow heated zones having temperatures lower than the melt zone and having a temperature differential of from 2.degree.-10.degree. C./mm decreasing form the melt zone while heating the substrate to a temperature below that of the zones heated by the lamps and scanning the structure.
    Type: Grant
    Filed: March 29, 1989
    Date of Patent: December 19, 1989
    Assignee: North American Philips Corporation
    Inventor: Subramanian Ramesh
  • Patent number: 4851358
    Abstract: The concentration of internal gettering sites within a semiconductor wafer is controlled by two-step thermal processing. In a concentration reduction phase, the wafer is rapidly heated to an elevated temperature in the range from about 900.degree. to 1350.degree. C., resulting in the partial or total dissolution of precipitable impurities within the wafer. In a concentration enhancement step, the wafers are subjected to a relatively low temperature anneal process where the density of potential internal gettering sites is increased. By properly controlling the processing temperatures and treatment times, the two steps may be performed in either order to obtain wafers having internal gettering site concentrations within a desired range.
    Type: Grant
    Filed: February 11, 1988
    Date of Patent: July 25, 1989
    Assignee: DNS Electronic Materials, Inc.
    Inventor: Walter Huber
  • Patent number: 4843031
    Abstract: Disclosed is a method of fabricating a compound semiconductor device which is capable of forming a multi-wavelength semiconductor laser structure, double cavity type semiconductor laser structure, stripe type semiconductor laser structure transverse junction stripe type semiconductor laser structure, or semiconductor grating by a single step of epitaxial growth while illuminating a desired part of substrate surface selectively with light at the time of epitaxial growth.
    Type: Grant
    Filed: March 15, 1988
    Date of Patent: June 27, 1989
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yuzaburo Ban, Hiraaki Tsujii, Youichi Sasai, Mototsugu Ogura, Hiroyuki Serizawa
  • Patent number: 4843032
    Abstract: A semiconductor optical element having a layer which exhibits a function of diffraction grating between a first cladding layer and a second cladding layer, wherein the layer which exhibits the function of diffraction grating consists of a superlattice layer in which crystal layers are periodically mixed to constitute a semiconductor grating layer.
    Type: Grant
    Filed: June 30, 1988
    Date of Patent: June 27, 1989
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yasunori Tokuda, Kenzo Fujiwara
  • Patent number: 4843030
    Abstract: A semiconductor processing method is provided for growing a semiconductor film from a semiconductorbearing gas on a substrate at a substrate temperature below the pyrolytic threshold of the gas. The gas is photodissociated to a collisionally stable species which migrates and travels in the gas phase the entire distance to the substrate, surving hundreds of collisions, and is pyrolyzed at the surface of the substrate and forms several monolayers of semiconductor material which is substantially more catalytically active than the substrate and which subsequently catalyzes decomposition of the gas.
    Type: Grant
    Filed: November 30, 1987
    Date of Patent: June 27, 1989
    Assignee: Eaton Corporation
    Inventors: J. Gary Eden, Kevin K. King, Viken Tavitian
  • Patent number: 4840922
    Abstract: A masking layer is formed on the light-emitting mirror surface of a semiconductor laser body. The masking layer is capable of blocking or cutting off light emitted from the semiconductor laser body and of being made optically transparent by exposure to the light emitted from the semiconductor laser body dependent on the amount of energy of the emitted light. When the light is emitted from the semiconductor laser body on which the masking layer is deposited, a small light-emitting hole is defined in the masking layer, the light-emitting hole having a desired diameter commensurate with the amount of energy of the emitted light which is applied to the masking layer.
    Type: Grant
    Filed: October 13, 1987
    Date of Patent: June 20, 1989
    Assignees: Ricoh Company, Ltd., Hiroshi Kobayashi, Haruhiko Machida
    Inventors: Hiroshi Kobayashi, Haruhiko Machida, Hideaki Ema, Jun Akedo, Makoto Harigaya, Yasushi Ide
  • Patent number: 4834809
    Abstract: A semiconductor substrate includes: a first monocrystalline semiconductive layer formed on the surface of a crystalline silicon substrate with the intervension of a first insulation film; a second insulation film set to the upper surface of the first monocrystalline semiconductive layer and provided with a plurality of apertures each having a specific pattern; and a second monocrystalline semiconductive layer which is epitaxially grown by the seed crystallization process and provided with the same crystalline characteristics as that of the first monocrystalline semiconductive layer.Accordingly, the preferred embodiment of the present invention provides an extremely useful semiconductor substrate which easily isolates the elements of semiconductor devices between layers of insulating film described above.
    Type: Grant
    Filed: September 9, 1987
    Date of Patent: May 30, 1989
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Yoshinobu Kakihara
  • Patent number: 4784963
    Abstract: Semiconductor components which have a plurality of layers lying on top of one another are manufactured with the assistance of a method for light-induced, photolytic deposition. Particularly, periodically alternating layers (hyperfine structure elements) and/or doping patterns are produced simultaneously with deposition of layers and/or with randomly selected doping gradients. In particular, the method is also suited for simultaneous deposition of layers lying laterally side-by-side or of laterally side-by-side differing dopings of a layer being deposited. In the context of doping, the radiation damage known from implantation is avoided.
    Type: Grant
    Filed: May 11, 1987
    Date of Patent: November 15, 1988
    Assignee: Siemens Aktiengesellschaft
    Inventors: Eberhard F. Krimmel, Adolf G. K. Lutsch
  • Patent number: 4778775
    Abstract: Improved processing for forming an interconnect in a process where a recrystallized polysilicon layer is formed over an insulative layer and where recrystallization takes place through a plurality of seed windows formed in the insulative layer. A doped region is formed in the substrate prior to deposition of the polysilicon layer. The polysilicon layer is in contact with at least a portion of the doped region through an opening in the insulative layer. Recrystallization takes place through this opening, and, for instance, the doped region is electrically connected to a source or drain region of a semiconductor device formed in the recrystallized layer.
    Type: Grant
    Filed: May 27, 1987
    Date of Patent: October 18, 1988
    Assignee: Intel Corporation
    Inventor: J. C. Tzeng
  • Patent number: 4774195
    Abstract: The invention relates to a process for the manufacture of semiconductor layers on semiconductor bodies or for the diffusion of impurities from compounds into semiconductor bodies, with fission products which are to be withdrawn during the process being formed. The gist of the invention is that the reactivity of certain fission products is increased by plasma excitation or by the supplying of photons. In particular, active hydrogen is made available for entry into a highly volatile, gaseous combination with existing fission products.
    Type: Grant
    Filed: August 1, 1985
    Date of Patent: September 27, 1988
    Assignee: Telefunken Electronic GmbH
    Inventor: Heinz Beneking
  • Patent number: 4757030
    Abstract: Solid phase epitaxial growth of single crystal layers on single crystal semiconductor substrates at temperatures low enough to preserve the integrity of other entities on the substrates. Contaminants are removed by low energy ion sputtering at a pressure low enough to delay their reformation before the layer can be deposited on the surface followed by annealing for one hour at 400.degree. C. A method of solid phase epitaxially growing a single crystal layer on a single crystal semiconductor substrate is also disclosed.
    Type: Grant
    Filed: November 26, 1986
    Date of Patent: July 12, 1988
    Assignee: Cornell Research Foundation, Inc.
    Inventors: Gregory J. Galvin, Christopher J. Palmstrom
  • Patent number: 4707909
    Abstract: A process of providing semi-insulating thin film resistors with closer tolerance values by furnance-annealing the film to increase is resistance to less than the final intended value, and then focused heat source-annealing the film to within a close tolerance of the final intended value.
    Type: Grant
    Filed: August 8, 1986
    Date of Patent: November 24, 1987
    Assignee: Siliconix Incorporated
    Inventor: Richard A. Blanchard
  • Patent number: 4604159
    Abstract: Disclosed is a method of forming a large number of monocrystalline silicon regions, of uniform orientation, on the surface of an insulator material. Initially, a large number of island regions of amorphous or polycrystalline silicon, thermally connected to one another in a predetermined direction by connecting regions, are provided. Then such island regions are sequentially melted and regrown in such predetermined direction so as to form the monocrystalline semiconductor regions, with such regions having a uniform orientation. Thereafter, such connecting regions can be removed in order to isolate the island regions. The connecting regions can be formed with gaps, whereby such connecting regions need not be removed. The connecting regions can be formed of materials having a higher heat conductivity than that of the material of the island regions, and/or the connecting regions can have a smaller cross-sectional area at right angles to the predetermined direction than that of the island regions.
    Type: Grant
    Filed: June 13, 1984
    Date of Patent: August 5, 1986
    Assignee: Hitachi, Ltd.
    Inventors: Yutaka Kobayashi, Akira Fukami, Takaya Suzuki
  • Patent number: 4559086
    Abstract: There is disclosed a process and the resulting semiconductor wafer wherein the backside of the wafer has applied thereto a layer of polysilicon. Portions of this layer are exposed to an energy beam to recrystallize them into single crystal silicon fused to and extending from the underlying wafer. The recrystallized portions contact adjacent portions of the polysilicon layer, thereby providing a path for impurities migrating from the wafer to the polysilicon.
    Type: Grant
    Filed: July 2, 1984
    Date of Patent: December 17, 1985
    Assignee: Eastman Kodak Company
    Inventor: Gilbert A. Hawkins
  • Patent number: 4555273
    Abstract: A method for annealing semiconductor samples, especially following ion-implantation of semiconductor samples is disclosed. A furnace on a set of rails is passed over the semiconductor sample which is supported on a stationary wire basket made of low thermal mass, fine tungsten wire. The furnace temperature may be about 5.degree. above the desired anneal temperature of the semiconductor sample such that the sample temperature rises to within a few degrees of the furnace temperature within seconds. Utilizing the moveable furnace insures uniform heating without elaborate temperature control or expensive beam generating equipment.The apparatus and process of the present invention are utilized for rapid annealing of ion-implanted indium phosphide semiconductors within 10 to 30 seconds and at temperatures of approximately 700.degree. C., thereby eliminating undesired and damaging movement of impurities within the ion-implanted InP.
    Type: Grant
    Filed: February 27, 1984
    Date of Patent: November 26, 1985
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: David A. Collins, Derek L. Lile, Carl R. Zeisse