Imide Resists Patents (Class 148/DIG75)
  • Patent number: 5242864
    Abstract: A process for forming a protective polyimide layer over a semiconductor substrate includes the steps of curing a deposited polyamic acid layer at a temperature which is sufficient to reduce the etch rate of the acid layer when subsequently exposed to a developer. After formation of a photoresist masking layer over the polyamic acid, the substrate is exposed to a developer to define a plurality of bonding pad openings therein. The developer permeates into the acid layer to form a salt in the regions beneath the openings. Subsequent hardbaking imidizes the polyamic acid, but not the salt regions. Removing the photoresist layer also develops the polyimide which removes the salt regions to expose the underlying bonding pads.
    Type: Grant
    Filed: June 5, 1992
    Date of Patent: September 7, 1993
    Assignee: Intel Corporation
    Inventors: Maxine Fassberg, Melton C. Bost, Krishnamurthy Murali, Peter K. Charvat, Lynn A. Price, Robert C. Lindstedt
  • Patent number: 5006488
    Abstract: Disclosed is a process for forming a pattern of metallization on a processed semiconductor substrate, under high temperature conditions, employing a polyimide precursor material as a lift-off layer. Advantageously, the material is photosensitive, and, after exposure and development, the portions of the layer remaining on the substrate can be completely and readily removed with conventional solvents.
    Type: Grant
    Filed: October 6, 1989
    Date of Patent: April 9, 1991
    Assignee: International Business Machines Corporation
    Inventor: Rosemary A. Previti-Kelly
  • Patent number: 4996165
    Abstract: A method for planarizing surfaces in multi-layered semiconductor structures using elevated features in the form of semiconductor materials, such as for forming heterojunctions, or interconnection metal. A process of forming the features includes leaving residual photoresist on the features. After feature formation and definition of transistor or other structure locations, dielectric material is deposited across the structure. Remaining photoresist is subsequently removed along with dielectric deposited thereon leaving dielectric between the features. A layer of polyimide is spun on the structure and into depressions between the dielectric and features. Typically material deposition, etching, dielectric backfilling and spin-coating steps are repeated until a predetermined number of contact or conductivity regions or interconnection metal layers are formed in the desired multi-layered structure.
    Type: Grant
    Filed: April 21, 1989
    Date of Patent: February 26, 1991
    Assignee: Rockwell International Corporation
    Inventors: Mau-Chung F. Chang, Peter M. Asbeck
  • Patent number: 4824798
    Abstract: A thin film bilayer composite source comprises a deposited impurity source layer, e.g. Si or Sb, heavily doped with a diffusion enabling agent, e.g. As, and capped with a passivating layer, e.g. Si.sub.3 N.sub.4, SiO.sub.2, AlN or SiO.sub.x N.sub.y. In a preferred embodiment, a thin film bilayer composite source comprises a Si layer on the surface of said structure vapor deposited at a temperature in excess of C. in the presence of a source of As to hevily dope the layer in the range of 5%-20% atomic weight and a thin cap layer of Si.sub.3 N.sub.4 deposited on the Si layer at a temperature in excess of C. having a thickness only sufficient to prevent the outdiffusion of Ga and As, which thickness may be about 400 .ANG.-700 .ANG.. An important aspect of the employment of this bilayer composite source as a diffusion source for III-V structures is that the composite source is initially deposited at high temperatures, above C., i.e.
    Type: Grant
    Filed: November 5, 1987
    Date of Patent: April 25, 1989
    Assignee: Xerox Corporation
    Inventors: Robert D. Burnham, Robert L. Thornton
  • Patent number: 4608749
    Abstract: A method of manufacturing a "two-level" solid-state image pickup device wherein a portion of a first metallic electrode electrically connected to a signal storage region is made to project to the highest position above a substrate on which it is formed. A coating of an organic insulating film is then applied to produce a flat surface. The entire surface of the organic film is then etched to expose the projections of the first metallic electrode. A second metallic electrode constituting a pixel electrode is connected to the first electrode at the exposed portion thereof.
    Type: Grant
    Filed: August 22, 1984
    Date of Patent: September 2, 1986
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Nozomu Harada, Yoshiaki Komatsubara
  • Patent number: 4596070
    Abstract: The disclosure relates to a semiconductor substrate having an active area for formation of an IMPATT device which is formed as a plurality of separated fingers having a common n+ region to spread the area over which the IMPATT is disposed and which provides such additional area for dissipation of heat through the substrate.
    Type: Grant
    Filed: July 13, 1984
    Date of Patent: June 24, 1986
    Assignee: Texas Instruments Incorporated
    Inventor: Burhan Bayraktaroglu
  • Patent number: 4596069
    Abstract: The disclosure relates to a monolithic circuit and method of making same which includes the use of two substrates of different semiconductor materials or two substrates of the same semiconductor material wherein the processing steps required for certain parts of the circuit are incompatible with the processing steps required for other parts of the circuit.
    Type: Grant
    Filed: July 13, 1984
    Date of Patent: June 24, 1986
    Assignee: Texas Instruments Incorporated
    Inventor: Burhan Bayraktaroglu