Impurity Redistribution By Oxidation Patents (Class 148/DIG78)
  • Patent number: 5213988
    Abstract: To manufacture a semiconductor device, a buried layer, epitaxial layer and an element separating layer are formed on a substrate, in order; a first resist film is formed thereon and an opening at which a first base is to be formed in patterned in the epitaxial layer; a first base is formed by ion-injection with the first resist film as a mask; the first resist film is removed and an interlayer insulating film is formed; a second resist film is formed thereon and an opening at which a second base is to be formed is removed by etching; the bottom surface of the opening portion is oxidized to form a second base under the same opening due to reduction of impurity concentration; the oxide film is removed and a polysilicon film is formed; an emitter electrode is patterned; and an emitter layer is formed on the second base by ion injection and thermal diffusion. Since the first and second base can be formed in self-alignment condition, the element can be minimized without providing a mask matching margin.
    Type: Grant
    Filed: February 7, 1991
    Date of Patent: May 25, 1993
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomohiro Yamauchi, Yasunobu Kodaira
  • Patent number: 5015593
    Abstract: In order to eliminate unwanted crystal defects generated by an ion implantation, a semiconductor substrate or an epitaxial layer, which is selectively subjected to an impurity ion implantation, is heat-treated in an inert gas atmosphere at 850.degree. to 1050.degree. C. to recrystallize the implanted region. Thereafter, the semiconductor substrate is heat-treated at 900.degree. to 1250.degree. C. in an atmosphere containing oxygen. For eliminating abnormal growth of grain boundaries in a polycrystalline semiconductor layer deposited on an insulating film the semiconductor layer is heat-treated at 900.degree. to 1100.degree. C. in an atmosphere containing oxygen. By applying at least one of these processes to usual fabrication methods, semiconductor devices with high reliabilty such as power MOSFETs will be provided.
    Type: Grant
    Filed: May 14, 1990
    Date of Patent: May 14, 1991
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shigeo Yawata, Kazuhisa Shibao, Shun-ichi Hiraki