Ion Implantation, General Patents (Class 148/DIG83)
  • Patent number: 6136385
    Abstract: A surface reforming method of a metal product, wherein a platinum film is formed on the surface of a metal product by injecting onto that surface a nitrogen ion, a carbon ion and a platinum ion in that order, and then injected onto said platinum film a second platinum ion with the aim of improving the exfoliation resistance of the platinum film being formed on the metal surface, and the abrasion resistance of the surface.
    Type: Grant
    Filed: July 29, 1999
    Date of Patent: October 24, 2000
    Assignee: Saatec Engineering Corporation
    Inventor: Yasuaki Sakamoto
  • Patent number: 5451529
    Abstract: A novel technique for the real time monitoring of ion implant doses has been invented. This is the first real-time monitor to cover the high dosage range (10E13 to 10E16 ions/sq. cm.). The underlying principle of this new technique is the increase in the resistance of a metal silicide film after ion implantation. Measurement of this increase in a silicide film that has been included in a standard production wafer provides an index for correlation with the implanted ion dose.
    Type: Grant
    Filed: July 5, 1994
    Date of Patent: September 19, 1995
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Shun-Liang Hsu, Chun-Yi Shih
  • Patent number: 5294557
    Abstract: A method for ion-implanting a dopant species in semiconductors includes the steps of implanting a dopant species in a semiconductor material at a predetermined rate, the predetermined rate being based on a rate corresponding to a maximum in a characteristic graph of percent activation as a function of dopant species implantation rate; and annealing the dopant implanted semiconductor.
    Type: Grant
    Filed: August 26, 1991
    Date of Patent: March 15, 1994
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Frederick G. Moore, Harry B. Dietrich
  • Patent number: 5290709
    Abstract: According to the present invention, in the ion implantation step in manufacturing a semiconductor device, a resist of a resist pattern formed on a portion of a semiconductor wafer is removed from the outer peripheral portion of the semiconductor wafer, and ion implantation is performed through the resist pattern.Since the resist is removed from the outer peripheral portion, a contact portion between a semiconductor wafer fixing portion of an ion implantation unit and the semiconductor wafer is conductive. Therefore, charges generated by the ion implantation escape from the wafer fixing portion, and the semiconductor wafer is not charged, thereby preventing electrostatic breakdown.
    Type: Grant
    Filed: April 9, 1992
    Date of Patent: March 1, 1994
    Assignee: NEC Corporation
    Inventor: Akira Sato
  • Patent number: 5244820
    Abstract: The present invention relates to an ion implantation process in a wafer process for a semiconductor integrated circuit device. Particularly, according to the present invention, a shallow junction can be formed by performing the implantation of ion while holding a wafer to be processed at a low temperature.
    Type: Grant
    Filed: August 3, 1992
    Date of Patent: September 14, 1993
    Inventors: Tadashi Kamata, Mitsuharu Honda, Jun Sugiura, Nobuo Owada, Hizuru Yamaguchi
  • Patent number: 5082793
    Abstract: A method of making a dielectric isolation integrated circuit structure in which dielectric material grooves formed by ion implantation extend down into the structure and intersect a PN junction or other active region at intersection lines such that each intersection line is within microns both laterally from the center of the groove and vertically from the bottom of the groove and the grooves continuously curve at least at the intersection lines at a radius of curvature less than 1 cm.
    Type: Grant
    Filed: November 17, 1989
    Date of Patent: January 21, 1992
    Inventor: Chou H. Li
  • Patent number: 5073507
    Abstract: A plasma containing both beryllium ions and beryllium fluoride ions is achieved. Beryllium crystals are used as a cathode in an ionization chamber containing boron trifluoride gas. The boron trifluoride gas and the beryllium are ionized to produce both beryllium fluoride ions (BeF.sup.+) and beryllium ions (Be.sup.+). Beryllium fluoride ions are emitted to impact a semiconductor target and where they divide thereby implanting beryllium and fluorine.
    Type: Grant
    Filed: March 4, 1991
    Date of Patent: December 17, 1991
    Assignee: Motorola, Inc.
    Inventors: Charles T. Keller, Schyi-Yi Wu
  • Patent number: 5023191
    Abstract: A single mask method for providing multiple masking patterns, using excess etching techniques, which is usable for developing a semiconductor substrate for a semiconductor device which results in an increased current being required before latchup occurs in the semiconductor device.
    Type: Grant
    Filed: December 1, 1989
    Date of Patent: June 11, 1991
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Kenya Sakurai
  • Patent number: 4988640
    Abstract: The present invention addresses the use of at least partially fluorinated organometallic compounds in reactive deposition applications. More specifically, the present invention addresses the use of the fluoroorganometallic compounds M(CF.sub.3).sub.3, or any M(C.sub.n F.sub.(2n+1)).sub.3-y H.sub.y compound where (y.ltoreq.2), M(CH.sub.2 CF.sub.3).sub.3 or any fluoroalkyl organometallics of the general formula M(C.sub.n H.sub.[(2n+1)-x] F.sub.x).sub.3-y H.sub.y, where y.ltoreq.2; x has a value 1.ltoreq.x.ltoreq.2n+1; and M=As, P, or Sb, in processes requiring deposition of the corresponding element. These uses include a number of different processes; the organometallic vapor phase epitaxy of compound semiconductor materials such as GaAs, InP, AlGaAs, InSb, etc. doping of SiO.sub.
    Type: Grant
    Filed: November 6, 1989
    Date of Patent: January 29, 1991
    Assignee: Air Products and Chemicals, Inc.
    Inventors: David A. Bohling, Gregory T. Muhr, David A. Roberts
  • Patent number: 4952446
    Abstract: This invention relates to ultra-thin semiconductor films which can be in the submicron range formed from semiconductor materials such as silicon, germanium and gallium arsenide. The films are formed by creating a thin slightly damaged surface on the polished reverse side of a film (e.g., a wafer) of the semiconductor by low dose ion implantation and then etching the semiconductor material on the front side of the film to remove the semiconductor material down to the ion implanted damaged layer. While the implanted ions can be chosen from functionally desirable ions which upon annealing remain in the film to alter the original electrical characteristics, the implanted ions can also be chosen so that upon annealing, the resultant ultra-thin semiconductor film has the same electrical characteristics as the original semiconductor material.The ion implantation changes the etching characteristics of the ion implanted layer.
    Type: Grant
    Filed: December 14, 1988
    Date of Patent: August 28, 1990
    Assignee: Cornell Research Foundation, Inc.
    Inventors: Kevin C. Lee, Charles A. Lee, John Silcox
  • Patent number: 4946735
    Abstract: This invention relates to ultra-thin semiconductor films which can be in the submicron range formed from semiconductor materials such as silicon, germanium and gallium aresenide. The films are formed by creating a thin slightly damaged surface on the polished reverse side of a film (e.g., a wafer) of the semiconductor by low dose ion implantation and then etching the semiconductor material on the front side of the film to remove the semiconductor material down to the ion implanted damaged layer. While the implanted ions can be chosen from functionally desirable ions which upon annealing remain in the film to alter the original electrical characteristics, the implanted ions can also be chosen so that upon annealing, the resultant ultra-thin semiconductor film has the same electrical characteristics as the original semiconductor material.The ion implantation changes the etching characteristics of the ion implanted layer.
    Type: Grant
    Filed: December 14, 1988
    Date of Patent: August 7, 1990
    Assignee: Cornell Research Foundation, Inc.
    Inventors: Kevin C. Lee, Charles A. Lee, John Silcox
  • Patent number: 4937206
    Abstract: A method for preventing cross-contamination of semiconductor wafers during processing comprising covering a surface portion of a support assembly with a process compatible material, engaging a semiconductor wafer with the support assembly, processing the wafer while it is engaged with the support member, and removing the process compatible material from the support assembly after said material is considered to be contaminated. A shield particularly adapted for this process includes a shield portion made from a process compatible material and a process-compatible adhesive for attaching the shield portion to the support assembly.
    Type: Grant
    Filed: July 10, 1989
    Date of Patent: June 26, 1990
    Assignee: Applied Materials, Inc.
    Inventors: Peter R. Jaffe, Kevin Fairbairn
  • Patent number: 4885257
    Abstract: A semiconductor substrate and process for making are disclosed. The substrate is suitable for use in manufacturing large scale integrated circuits. The process comprises the steps of heating a semiconductor substrate at a temperature not lower than C., implanting electrically inert impurities into the major surface of the substrate, heating the substrate at a temperature ranging from to C. and providing a single crystal semiconductor layer.
    Type: Grant
    Filed: June 2, 1987
    Date of Patent: December 5, 1989
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoshiaki Matsushita
  • Patent number: 4861732
    Abstract: In the present invention, a method for removing an organic resin material layer reduces residual substances upon removing an ion-implanted organic resin material layer. Inorganic contaminants adhered to the surface of organic resin material layer during ion-implantation are removed by etching, and thereafter, the layer is decomposed and removed by plasma irradiation of the organic resin material layer. An alkaline etchant is used for etching off inorganic contaminants.
    Type: Grant
    Filed: September 13, 1988
    Date of Patent: August 29, 1989
    Assignee: Fujitsu Limited
    Inventors: Shuzo Fujimura, Junichi Konno
  • Patent number: 4837174
    Abstract: A method for producing thin conductive or semiconductive layers embedded in silicon in the manufacture of structures for integrated circuits and the like. The invention is characterized by implanting metal atoms (14) in a silicon substrate (15) to a pre-determined nominal depth, and subsequently causing the implanted metal atoms to be redistributed, to form a conductive or a semiconductive layer (16), by heat-treating the silicon substrate (15).
    Type: Grant
    Filed: July 30, 1987
    Date of Patent: June 6, 1989
    Assignee: Stiftelsen Institutet for Microvagsteknik VID
    Inventor: Sture Peterson
  • Patent number: 4801555
    Abstract: A process for forming graded source/drain regions in semiconductor devices involves two ion implantation steps and an optional drive-in step. The first implantation is a low dose implant with high energy and/or low mass ions to form the deeper grading region. The second implant is a high does implant with low energy and/or high mass ions to form the shallower, lower resistivity source/drain region. Without the optional drive-in step, virtually no lateral grading takes place, resulting in little encroachment of the grading region under the gate. The use of a drive-in step between the two implant steps causes diffusion of the grading dopant, which increases the grading both laterally and vertically, resulting in better breakdown and capacitance characteristics, but increased encroachment under the gate. The present invention allows control over the lateral and vertical grading separately to optimize the trade-offs for a particular application.
    Type: Grant
    Filed: January 14, 1987
    Date of Patent: January 31, 1989
    Assignee: Motorola, Inc.
    Inventors: Patrick J. Holly, Louis C. Parrillo, Frank K. Baker
  • Patent number: 4777150
    Abstract: There is described a process for the formation on a substrate of a refractory metal silicide layer, usable particularly for producing the interconnection layers of integrated circuits. This process consists of successively depositing on the substrate a first amorphous hydrogenated silicon layer, a second amorphous hydrogenated refractory metal layer, e.g. of tungsten, titanium, molybdenum or tantalum, and a third amorphous hydrogenated silicon layer. The thus coated substrate is then subjected to an annealing treatment at a temperature equal to or higher than C. in a hydrogen atmosphere. Preferably, following the deposition of the three layers, the coated substrate undergoes ionic implantation, e.g. using tungsten ions, for producing defects in the layers, which makes it possible to speed up the formation of the refractory metal silicide layer during the annealing stage.
    Type: Grant
    Filed: February 26, 1986
    Date of Patent: October 11, 1988
    Assignee: Centre de La Recherch Scientifique
    Inventors: Alain Deneuville, Pierre Mandeville
  • Patent number: 4743570
    Abstract: In a vacuum chamber wafer treating apparatus a wafer is heated or cooled by introducing a gas at a pressure of approximately 100 to 1000 microns in a region between the wafer and a heating element or heat sink. The gas conducts thermal energy between the wafer and heating element or heat sink.
    Type: Grant
    Filed: July 10, 1987
    Date of Patent: May 10, 1988
    Assignee: Varian Associates, Inc.
    Inventor: Lawrence T. Lamont, Jr.
  • Patent number: 4740481
    Abstract: Hillock formation as a result of heating uncapped polycrystalline silicon layers can be avoided by first implanting the uncapped poly layers with silicon, oxygen, or nitrogen prior to heating. Equivalent mono-atomic oxygen or nitrogen doses in the range of about 10.sup.15 to about 5.times.10.sup.16 ions/cm.sup.2 at energies in the range 10-50 keV are useful with good results being obtained with equivalent oxygen doses of 2.times.10.sup.15 ions/cm.sup.2 at 30 keV. When polysilicon layers with this oxygen implant are heated to about 1150 degrees C., a temperature which would ordinarily produce pronounced hillock formation in un-capped, un-treated poly layers, it is found that hillock formation is suppressed. The implanted oxygen concentrations are far below what is required to produce a separate oxide layer or phase. Some effect on poly layer sheet resistance is observed for implanted oxygen but the implanted layers have sheet resistances within a factor of two of those without the oxygen implants.
    Type: Grant
    Filed: January 21, 1986
    Date of Patent: April 26, 1988
    Assignee: Motorola Inc.
    Inventors: Syd R. Wilson, Richard B. Gregory, Charles J. Varker
  • Patent number: 4732867
    Abstract: Indicia are formed in a sapphire substrate by ion implantation with a sufficient amount of silicon ions to establish a contrast with the remainder of the substrate. The implant is annealed at to C. under an oxygen or inert atmosphere. The implants are stable to repeated heatings to elevated temperature. The implants are further beneficial in that they do not introduce a source of contamination into the substrate.
    Type: Grant
    Filed: November 3, 1986
    Date of Patent: March 22, 1988
    Assignee: General Electric Company
    Inventor: George L. Schnable
  • Patent number: 4676841
    Abstract: Dielectrically isolated devices are produced by a series of steps including the implantation of a silicon substrate to produce a precursor to the silicon oxide region and subsequently heat treating this region. In contrast to previous techniques, the extent of such heating is substantially increased to remove a non-oxidic intermediary region typically remaining.
    Type: Grant
    Filed: September 27, 1985
    Date of Patent: June 30, 1987
    Assignee: American Telephone and Telegraph Company, AT&T Bell Laboratories
    Inventor: George K. Celler
  • Patent number: 4670968
    Abstract: A method of manufacturing a semiconductor device involves the step of carrying out the implantation of an impurity in the main plane of a GaAs substrate for the simultaneous formation of a plurality of regions. When the angles formed with the perpendicular implantation of silicon ions in the GaAs main plane and the main orientations of GaAs substrate are expressed by the Euler angles (.lambda.,.mu.,.theta.), then the crystal orientation is so prescribed as to satisfy the following<.lambda.<<.mu.<,thereby suppressing the occurrence of channeling in the implantation of ions in the substrate main plane and consequently ensuring substantially uniform impurity concentration in the plural regions.
    Type: Grant
    Filed: November 18, 1985
    Date of Patent: June 9, 1987
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hitoshi Mikami, Katsuyoshi Fukuda, Shigeru Yasuami
  • Patent number: 4671845
    Abstract: The present invention relates to the production of a stable insulator of a germanium and a device produced thereby. A germanium substrate is provided with a layer of silicon nitride deposited on one of the outer surfaces. Ionized nitrogen is implanted by an ion beam into the silicon nitride layer. An electric field is applied across the substrate and layer. In one embodiment the substrate and layer are annealed while maintaining the electric field, the electric field is removed, and a second annealing step grows the germanium nitride insulator layer subcutaneously. In another embodiment the subcutaneous germanium nitride insulator layer is grown during a single annealing step by continued application of the electric field to the substrate and the layer.
    Type: Grant
    Filed: March 22, 1985
    Date of Patent: June 9, 1987
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventor: Max N. Yoder
  • Patent number: 4670064
    Abstract: A semiconductor ion implantation processing technique is disclosed for implanting high purity, high flux density ions in a semiconductor wafer substrate. A reactant gas is irradiated with excimer pulsed ultraviolet laser radiation at a discrete designated pulsed wavelength corresponding to a discrete designated ionization excitation energy of the gas photochemically breaking bonds of the gas to nonthermally photolytically ionize the gas. The ions are then accelerated by an electric field for subsequent implantation into a surface.
    Type: Grant
    Filed: April 10, 1985
    Date of Patent: June 2, 1987
    Assignee: Eaton Corporation
    Inventors: Steven R. Schachameyer, James A. Benjamin, John B. Pardee, Lyle O. Hoppie
  • Patent number: 4658497
    Abstract: An imaging array of the charge transfer type having improved sensitivity is disclosed. The array includes a plurality of substantially parallel charge transfer channels with channel stops therebetween which extend a distance into a semiconductor body. At least some of the channel stops have blooming drains therein for the removal of excess photogenerated charge. The improvement comprises potential barrier means which constrain electrical charge generated by absorption of light in the body to flow into the channels while preventing the loss of such charge by direct flow to the blooming drains. Potential barrier means include buried barrier regions extending a further distance into the body from those channel stops having blooming drain regions therein.The invention also includes an improved method of forming this array wherein the improvement comprises forming buried barrier regions containing a greater concentration of conductivity modifiers than the channel stops after the blooming drains are formed.
    Type: Grant
    Filed: June 3, 1985
    Date of Patent: April 21, 1987
    Assignee: RCA Corporation
    Inventors: Eugene D. Savoye, Walter F. Kosonocky, Lloyd F. Wallace
  • Patent number: 4653176
    Abstract: A method of simultaneously manufacturing semiconductor regions having different doping concentrations, for example, for obtaining semiconductor resistors having differences values. Due to difference in the rate of oxidation, oxide edges of different widths can be formed by oxidation of n-type silicon regions thus obtained. According to the invention, ion implantation or deposition takes place through doping windows for each of which the ratio between the window surface area and the surface area to be doped is different. Subsequently, homogeneous doping concentrations are obtained by diffusion.
    Type: Grant
    Filed: March 7, 1985
    Date of Patent: March 31, 1987
    Assignee: U.S. Philips Corporation
    Inventor: Alfred H. Van Ommen
  • Patent number: 4634473
    Abstract: A method for making a partially radiation hardened oxide adjacent an edge comprises forming an oxide layer on another layer with a temperature between about C. and C., preferably between about C. and C. Then the structure of the oxide layer is damaged, such as by ion implantation, preferably with an inert element. Thereafter the oxide layer is annealed at a temperature between about C. and C., preferably at about C.
    Type: Grant
    Filed: September 9, 1985
    Date of Patent: January 6, 1987
    Assignee: RCA Corporation
    Inventors: George A. Swartz, Carl W. Benyon, Jr.
  • Patent number: 4584763
    Abstract: A one mask technique for making substrate contact from the top surface of an integrated circuit device. A thin ion implanted region of one conductivity type is formed over the entirety of a major surface of the semiconductor substrate. By lithography and etching, a shallow etched region is formed to a depth below the region of the first conductivity type at the substrate surface in an area designated for substitute contacting. A region of a second conductivity type is then formed at the central portion of the etched region. The substrate is then heated to form a buried collector region of the first conductivity type and a portion of the reach-through region of the second conductivity type in the substrate. An epitaxial layer is next formed on the major surface of the substrate. A base region of the second conductivity type for the integrated circuit is then formed.
    Type: Grant
    Filed: December 15, 1983
    Date of Patent: April 29, 1986
    Assignee: International Business Machines Corporation
    Inventors: Chakrapani G. Jambotkar, Shashi D. Malaviya
  • Patent number: 4574469
    Abstract: A process is described for producing isolated semiconductor devices in a common substrate which have self-aligned and pre-located isolation walls, buried layers, and channel-stops. The isolation walls are formed from a stacked arrangement of a dielectric region and a non-single crystal semiconductor region, above a doped channel-stop region. A single mask layer determines the location and spacing of the non-single crystal portion of the isolation walls, the channel-stops, and the buried layers.
    Type: Grant
    Filed: September 14, 1984
    Date of Patent: March 11, 1986
    Assignee: Motorola, Inc.
    Inventors: Sal Mastroianni, Carroll Casteel, Terry S. Hulseweh
  • Patent number: 4569124
    Abstract: A thin conducting line such as a gate pattern is defined on a semiconductor chip (10) by applying a narrow ion beam, suitably a focused-ion-beam (16) having a submicrometer thickness from a source (18) onto a thin layer (14) of an inorganic material such as silicon or aluminum overlying a layer (12) of refractory metal on a substrate (11). The ion beam is translated to form a gate pattern at a dose between about 0.1 to 50.times.10.sup.15 cm.sup.-2 and an energy from about 1 to 1000 KeV. Ions are implanted into the silicon and aluminum layers and into the underlying portions of the refractory metal layer and to render the exposed portions of the layers preferentially resistant to wet-etchant. The portions of layers which are not exposed nor protected by layers which are exposed, are preferentially removed to form a gate. Conventional MOSFET or MESFET processing to implant ions to form source and drain regions may then be performed.
    Type: Grant
    Filed: May 22, 1984
    Date of Patent: February 11, 1986
    Assignee: Hughes Aircraft Company
    Inventors: David B. Rensch, John Y. Chen
  • Patent number: 4553315
    Abstract: The contact for N channel devices in a CMOS process is formed by ion implanting N-type impurities through contact apertures in the dielectric layer to a depth less than the source and drain regions and a layer of conductive material is applied without intermediate etching and delineated.
    Type: Grant
    Filed: April 5, 1984
    Date of Patent: November 19, 1985
    Assignee: Harris Corporation
    Inventor: Chris McCarty
  • Patent number: 4546540
    Abstract: This specification discloses a self-aligned manufacturing method of a Schottky gate FET. This method comprises the steps: forming a gate metallic layer on a semiconductor substrate and a mask overhanged on the metallic layer; ion-implanting impurity ions into the semiconductor substrate using the mask to form a source/drain region; depositing an insulator on the gate metallic layer side surface and the other surface below the mask; directionally etching said deposited insulator using the mask to expose the source/drain region; depositing a source/drain electrode using the mask; and removing the mask.
    Type: Grant
    Filed: September 13, 1983
    Date of Patent: October 15, 1985
    Assignee: Hitachi, Ltd.
    Inventors: Kiichi Ueyanagi, Yasunari Umemoto, Susumu Takahashi, Michiharu Nakamura
  • Patent number: H948
    Abstract: A process for the interdisposition of a semiconductor compound by high dose oxygen ion implantation after a high quality single crystal semiconductor film has been formed on an insulator substrate. Specifically, in one embodiment, after the formation of a single crystal silicon semiconductor film on an insulator substrate of either sapphire or spinel, oxygen ion implantation is formed to create a silicon dioxide layer at the interface between the silicon semiconductor film and the insulator substrate in order to reduce the interface states and form a diffusion barrier between the semiconductor material and the electrical insulator substrate.
    Type: Grant
    Filed: August 17, 1990
    Date of Patent: August 6, 1991
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventor: Monti E. Aklufi