Abstract: This invention is a processing method for electrically isolating CMOS transistors. The method involves implanting a channel stop dopant into field regions between transistor active regions, self aligning relatively thick silicon dioxide over these field regions and providing thin oxide in the active regions that are self aligned to the field regions. The method does not require any shallow trench isolation (STI), and does not require Local Oxidation of Silicon (LOCOS), thereby resulting in little damage to the silicon.

Abstract: Integrated circuits suitable for high-performance applications, especially mixed signal products that have analog and digital sections, are fabricated from a semiconductor structure in which lower buried regions of opposite conductivity types are situated along a lower semiconductor interface between a semiconductive substrate and an overlying lower semiconductive layer. An upper buried region of a selected conductivity type is situated along an upper semiconductor interface between the lower semiconductive layer and an overlying upper semiconductive layer. Another upper buried region of opposite conductivity type to the first-mentioned upper buried region is preferably situated along the upper semiconductor interface. The upper semiconductive layer contains P-type and N-type device regions in which transistor zones are situated. The semiconductor structure is configured so that at least one of each of the P-type and N-type device regions is electrically isolated from the substrate.

Abstract: A trench is formed in a substrate, the trench defining an active region surface on the substrate, the trench having a trench sidewall. A trench insulation region is then formed in the trench. The substrate underlying the trench sidewall is doped with impurities, and after the first doping, the substrate underlying the active region surface is doped with impurities to form a well having an impurity concentration which increases towards the trench sidewall in a predetermined manner. To form the trench, an insulation layer preferably is formed on the substrate, a barrier layer is formed on the insulation layer, and the barrier layer and the insulation layer are patterned to form an insulation region on the substrate and a barrier region on the insulation region. The substrate is then etched using the barrier region and the insulation region as a mask to thereby form a trench in the substrate.

Abstract: The preferred embodiment of the present invention overcomes the limitations of the prior art and provides a device and method to increase the latch-up immunity of CMOS devices by reducing the mobility of carriers between the devices. The preferred embodiment uses an implant formed beneath trench isolation between n-channel and p-channel devices. This implant preferably comprises relatively large/heavy elements implanted into the wafer beneath the trench isolation. The implant elements reduce the mobility of the charge carriers. This increases the latch-up holding voltage and thus reduces the likelihood of latch-up. The implants can be formed without the need for additional photolithography masks.

Abstract: A semiconductor device includes a p-type silicon substrate, a first well of p-type formed in a major surface of the silicon substrate, and a second well of n-type formed close to the first well in the major surface of the silicon substrate. A third well of p-type is formed inside the second well and, furthermore, a conductive layer including p-type impurities of higher concentration than that of the first well is formed as extending immediately below both the first well and the second well. In accordance with this structure, even if minority carriers are injected, they recombine and disappear in the conductive layer, so that the implantation of the carriers into the first well is prevented. As a result, various disadvantageous phenomena due to the injection of the minority carriers are prevented and a semiconductor device having a stable device characteristic and high integration density is provided.

Abstract: A dielectrics dividing wafer, and a method of manufacturing the wafer, is disclosed in which embedded dielectric films are provided in the interior of the wafer in a predetermined pattern extending laterally parallel to a face surface of the wafer, and partition dielectric films, in the form of vertical walls extending from the face surface and the rear surface of the wafer, to the embedded dielectric films, are provided to define semiconductor areas extending continuously from the face surface of the wafer to the rear surface of the wafer. The semiconductor areas can be used for vertical circuit elements. The partition dielectric films in conjunction with the embedded dielectric films and the face surface of the wafer also define additional planar semiconductor areas that can be used for planar structure circuit elements.

Abstract: A process is disclosed which simultaneously forms high quality complementary bipolar transistors, relatively high voltage CMOS transistors, relatively low voltage CMOS transistors, DMOS transistors, zener diodes and thin-film resistors, or any desired combination of these, all on the same integrated circuit chip. The process uses a small number of masking steps, forms high performance transistor structures, and results in a high yield of functioning die. Isolation structures, bipolar transistor structures, CMOS transistor structures, DMOS transistor structures, zener diode structures, and thin-film resistor structures are also disclosed.

Abstract: A method of manufacturing various types of silicon devices, such as complementary bipolar PNP and NPN transistors, in a Silicon On Insulator ("SOI") Integrated Circuit ("IC"), the SOI IC having a substrate, a buried insulating layer disposed above the substrate, and a silicon device layer disposed above the insulating layer. Vertical transistors may be formed in the device layer such that each transistor is fully dielectrically isolated from another and also from other similarly manufactured silicon devices in the silicon device layer.

Abstract: A vertical transistor comprises a semiconductor layer of a first conductivity type having a first doped region (48) formed therein. A second doped region (50) is formed within the first doped region (48). A gate overlies the first doped region such that a low impedance path between the second doped region and the semiconductor layer may be created responsive to a voltage applied to the gate. Isolation regions (38 and 58) are formed through the semiconductor layer to isolate the transistor from other devices.

Abstract: A process sequence that produces a plurality of pretransistor structures from which a variety of high voltage, isolated integrated circuits and low voltage integrated circuits are easily fabricated.

Abstract: A method is disclosed which produces a high voltage MOS transistor with a deep retrograde N-well region, which includes a buried layer, said deep retrograde well region acting to increase the breakdown voltage of the MOS transistor and reduce the current gain of the inherent parasitic bipolar transistor. To achieve a high degree of control over the impurity concentration of the buried layer without affecting the impurity concentration in the N-well region, two dopants species are diffused or implanted in the N+ buried layer: one, a slow diffusing dopant, such as antimony or arsenic, and the other, a more rapidly diffusing dopant, such as phosphorus. A P- type epitaxial layer is grown over the buried layer and an N-well is formed in the epitaxial layer over the buried layer.

Abstract: Series resistance in the low impurity portion of a high breakdown PN junction of a three or four layer device is reduced by providing an increased inpurity region at the junction of the same conductivity type as the low impurity portion and having an impurity profile such that the increased impurity region is depleted under reverse biasing before critical field is reached therein. The three layer devices include insulated gate field effect transistors and bipolar devices and the four layer device is a semiconductor controlled rectifier (SCR).

Abstract: A method of making a dielectric isolation integrated circuit structure in which dielectric material grooves formed by ion implantation extend down into the structure and intersect a PN junction or other active region at intersection lines such that each intersection line is within microns both laterally from the center of the groove and vertically from the bottom of the groove and the grooves continuously curve at least at the intersection lines at a radius of curvature less than 1 cm.

Abstract: A method for forming an array of single crystalline seed crystals separated by an insulator and suitable for use in the formation of infrared detector elements is disclosed. The seed crystals are formed from a single crystalline substrate having first and second planar surfaces. An array of grooves is formed in the first planar surface of the single crystalline substrate such that a plurality of protrusions are formed upon the first planar surface of the single crystalline substrate. The grooves are then filled with an insulator. A portion of the second planar surface of the substrate is then removed to expose the insulator disposed within the grooves to form an array of single crystalline seed crystals. The single crystalline seed crystals are separated by the insulator. The single crystalline seed crystals and the insulator are exposed upon both the first and second surfaces of the array.

Abstract: The method for making an improved, surface-passivated and electrically isolated silicon device (including integrated circuit) comprises providing in a silicon wafer with a pn junction or other electronic rectifying barrier; and thermally oxidizing or ion-implanting oxygen or nitrogen into selected silicon surface regions to form electrically isolating grooves. The grooves have symmetrical, centrally rounded bottoms which are located within a few microns below the pn junction or rectifying barrier. Through these unique oxide/nitride forming conditions and curvature, symmetry, and proximity effects, novel passivation and isolation results obtain.

Abstract: According to the present invention, an SOI film of a monocrystalline silicon film is formed by making solid phase epitaxial growth of an amorphous silicon layer formed on an oxide film. A through hole portion formed in the oxide film is formed in such a shape that an epitaxial growth region growing with the through hole portion as a nucleus covers the entire region of the amorphous silicon layer. After the SOI film is formed, oxygen ions are ioin-implanted into the through hole portion in the oxide film, to be embedded by an oxide film layer by thermal processing.

Abstract: The method of forming a multiwafer integrated circuit for abutting electrical connection to external electronics is disclosed. The method comprises forming a plurality of grooves in the first surface of each of first and second wafers. The grooves are filled with a body of insulating material and joined along the groove surfaces thereof. In one embodiment active circuitry is formed in one of the abutting wafer surfaces. In another embodiment active circuitry is formed in a non-abutting surface of one of the wafers. Conductive leads are applied to the surface of one of the wafers to be in electrical communication with the doped regions. At least one of the conductive leads extends across at least a portion of the grooves. The wafers are trimmed in length so that the lengthwise edges of the wafers are defined by the grooves and the butt end of at least one of the conductive leads is exposed.

Abstract: A process is described for forming semiconductor device which include forming step of coating of silicon oxide derivative before ion implanting step: The coating prevents unnecessary extention of channel stop regions thus produces high speed and high current drive ability of produced semiconductor device.

Abstract: A void-free isolated semiconductor substrate is described which contains a pattern of substantially vertically sided trenches within a semiconductor body. The pattern of isolation trenches isolate regions of monocrystalline semiconductor material which may contain active and passive semiconductor devices. A first insulating layer is located upon the sidewalls of the trenches. The base or bottom of the trenches is open to the monocrystalline semiconductor body. An epitaxial layer extending from the base of the trenches fills the pattern of trenches up to a level from the upper surface of the trenches as specified approximately by the equation:y=0.34xwhere y is the distance between the epitaxial layer and the top surface and x is the trench width. The preferred range for the trench width x is about 10 micrometers or less. A polycrystalline silicon layer fills the additional portion of the pattern of trenches above the upper surfaces of the epitaxial layer.

Abstract: A semiconductor structure is provided by forming an isolation region in a portion of a semiconductor layer, forming a doped region in the semiconductor layer adjacent the isolation region, such doped region having a conductivity type opposite the conductivity type of the semiconductor layer, selectively masking a surface of the semiconductor layer exposing a portion of the doped region adjacent to the isolation region, and selectively etching the exposed portions of the adjacent doped region forming a depression having converging side walls separated from the isolation region by portions of the doped region. The semiconductor layer is an epitaxial layer providing the collector region of a transistor. The bottom portion of the depression is lightly doped to provide an active base region for the transistor. The active base region is electrically connected to the base contact through the more heavily doped region formed in the semiconductor layer.

Abstract: A process is disclosed for controllably providing dielectrically isolated semiconductor regions having a uniform and well defined thickness. Grooves are formed in a first surface of a semiconductor substrate and then a dielectric layer is formed covering that surface and the grooves extending into the surface. A layer of backing material such as polycrystalline silicon is formed overlying the dielectric layer. A semiconductor substrate is then thinned to form a new surface with portions of the dielectric layer and backing material exposed at that surface. A semiconductor layer is epitaxially grown overlying the new surface with the semiconductor layer having a monocrystalline structure where it is grown on exposed regions of the original substrate and having a polycrystalline structure otherwise. An oxidation masking layer is formed overlying those portions of the semiconductor layer which have a monocrystalline structure.

Abstract: A method for manufacturing a semiconductor device comprises a first step of forming a field insulation layer on a p-type semiconductor substrate and a second step of forming an n.sup.+ -type region and n-type region in an element area surrounded by the field insulation layer. In particular, the second step includes a step of forming, in the element area, a recess having an inclined portion and flat bottom portion, a step of forming an SiO.sub.2 film of a uniform thickness on the inclined portion and flat bottom portion, and a step of ion-implanting an n-type impurity into the substrate through the SiO.sub.2 and effecting an annealing process.

Abstract: The invention comprises an improved integrated circuit structure wherein an active device is formed in a silicon substrate for forming an intrinsic base region over a buried collector and an emitter is formed on the intrinsic base region to comprise three electrodes of the active device and at least one extrinsic base segment is formed in the substrate adjacent to the intrinsic base region to provide a contact for the intrinsic base; the improvement which comprises: separating the extrinsic base segment from the emitter formed on the intrinsic base to prevent the formation of a parasitic P-N junction between the extrinsic base and the emitter.

Abstract: A method of producing a semiconductor device comprises an isolation step for forming an n-type region in contact with p.sup.+ -type source and drain regions of a p-channel floating gate MOS transistor in the surface area of an n-type semiconductor substrate and an n.sup.+ -type region in contact with the n-type region. In this isolation step, and oxidation resistant film pattern is formed on the element region of the MOS transistor. An anisotropic etching is applied to the substrate with the oxidation resistant film pattern used as a mask to form an inclined portion and a flat portion, followed by forming a SiO.sub.2 film of a prescribed thickness to cover both the inclined and flat portions. Further, an n-type impurity is introduced by ion implantation into the substrate through the SiO.sub.2 film in a direction perpendicular to the flat portion, followed by annealing the ion-implanted region.

Abstract: A process is disclosed for manufacturing electrically isolated semiconductor device structures. The process includes the steps of providing a semiconductor substrate and selectively etching one surface of that substrate to form etched regions and unetched regions. In a single epitaxial growth step three separate epitaxial layers are grown overlying both the etched and unetched regions. The epitaxial layers are then shaped back to form a substantially planar surface and to expose portions of the first epitaxial layer. The exposed portion of the first epitaxial layer, in combination with the substrate, is suitable for the fabrication of a back contact power transistor. The second epitaxial layer, which follows the contour of the etched surface, bends upwardly and intersects the planar surface to substantially surround portions of the third epitaxial layer and to electrically isolate those portions of the third epitaxial layer from the substrate and first epitaxial layer.

Abstract: A semiconductor device and the method of manufacturing the same are disclosed, the semiconductor device having a plurality of elements isolated by a groove having a gentle slope at the upper side wall, and a steep slope at the lower side wall. This groove provides low steps on its mouth and occupies a small area on the substrate, thus enabling an extremely high-density integrated circuit to be formed.

Abstract: The specification discloses an isolation trench (36) formed in a semiconductor body. A stress relief layer (38) of oxide is formed on the interior walls of the trench (36), the layer (38) being sufficiently thin to prevent stressing of the lower corners of the trench (36). A masking layer (40) of nitride is formed over the layer (38). An isolation body (42) of oxide or polysilicon then refills the remainder of the trench and a cap oxide (43) and layer (44) of field oxide is formed over the semiconductor body and the filled trench.

Abstract: A technique is disclosed for the artificial introduction of a localized subsurface strained layer within a thick polysilicon layer to minimize the large change in warpage (defined as springback) which occurs in a (100) Si substrate thinning operation during the mechanical processing of dielectrically isolated (DI) wafers. This novel technique is capable of favorably altering the state of stress and the stress profile in the multicomponent "polysilicon/SiO.sub.2 /(100) Si" DI structure so as to reduce the natural springback in warpage that occurs when the stiffening member, the (100) Si substrate, is removed. This subsurface disturbed layer is retained within the polysilicon layer during subsequent processing to maintain the favorable stress profile with a minimum of wafer warpage. In one embodiment of the present invention, the subsurface strained layer is generated by growing an interface layer (SiO.sub.2 or Si.sub.3 N.sub.

Abstract: Full oxide isolation of epitaxial islands can be accomplished by oxidizing suitably porous silicon. The porous silicon can be created by anodizing highly doped n+ silicon in hydroflouric acid. Lesser doped epitaxial regions will not become porous and will become isolated islands suitable for the fabrication of semiconductor devices.

Abstract: A method for fabricating isolated regions for a dielectric isolated complementary integrated circuit which avoids the difficulty of mask alignment and patterning on a deeply etched uneven surface of the substrate by aligning the patterns before etching and thereby forming p-type and n-type islands at the same time. A poly-silicon layer is grown on the surface of the substrate covering the islands and the substrate is removed from its back surface, leaving the islands embedded in the poly-silicon layer which becomes a new substrate.

Abstract: A method of manufacturing a semiconductor device which comprises a step of forming a first groove in a semiconductor layer, a step of filling the first groove with a first insulating film, a step of selectively etching the first insulating film in the first groove to form at least one second groove having a small width, and a step of filling the second groove with a second insulating film to form an isolation layer having a large width and substantially flush with the semiconductor layer.

Abstract: A method of manufacturing a semiconductor device which comprises a step of forming a first groove in a semiconductor layer, a step of filling the first groove with a first insulating film, a step of selectively etching the first insulating film in the first groove to form at least one second groove having a small width, and a step of filling the second groove with a second insulating film to form an isolation layer having a large width and substantially flush with the semiconductor layer.

Abstract: The purity and perfection of a semiconductor is improved by depositing a patterned mask (12) of a material impervious to impurities of the semiconductor on a surface (14) of a blank (10). When a layer (40) of semiconductor is grown on the mask, the semiconductor will first grow from the surface portions exposed by the openings (16) in the mask (12) and will bridge the connecting portions of the mask to form a continuous layer (40) having improved purity, since only the portions (42) overlying the openings (16) are exposed to defects and impurities. The process can be reiterated and the mask translated to further improve the quality of grown layers.

Abstract: An improved means and method is provided for forming isolated device regions suitable for the construction of control circuits and devices, in the presence of and isolated from other device regions suitable for the construction of bottom-contact power devices. In a preferred embodiment the desired structure is obtained by growing a first epitaxial layer on a semiconductor substrate, providing a patterned mask in which areas of the epitaxial layer are exposed to be etched, etching recesses in the exposed areas to a first depth to leave pedestals beneath the masked areas, and forming a second and third epitaxial layer on the substrate to fill the recesses. The second epitaxial layer is U-shaped and conformally coats the bottom and sides of the recesses. The U-shaped layer acts as the isolation layer separating the first epitaxial layer portions in the pedestals wherein the power devices will be built, from the third epitaxial layer regions which fill in the U, where the control devices will be built.

Abstract: Method of forming a substrate for fabricating CMOS FET's by forming sections of N and P-type conductivity in a body of silicon. Grooves are etched in the N and P-type sections to produce N and P-type sectors encircled by grooves. The surfaces of the grooves are oxidized, the grooves are filled with polycrystalline silicon, and exposed surfaces of the polycrystalline silicon are oxidized to form barriers which encircle the sectors and electrically isolate them. Shallow trenches are etched in regions of the body outside the N and P-type sectors and the trenches are filled with regions of silicon dioxide. A pair of complementary FET's are fabricated in the two sectors and a metal interconnection between them overlies a portion of a region of silicon dioxide.

Abstract: Disclosed is the use of metal silicide (e.g. Pt-Si) contacts in boron lightly doped P.sup.- type silicon between two contiguous but not adjacent N.sup.+ type regions instead of employing the usual P.sup.+ implanted or diffused channel stoppers. The invention finds a particularly interesting application in polyimide filled deep trench isolated integrated circuits.The trench sidewalls are coated with an insulating material which is removed from the trench bottom at the all contact etch step. The Pt-Si is formed at the bottom of the trenches at the same time that the device contacts are made.

Abstract: A process is described for producing isolated semiconductor devices in a common substrate which have self-aligned and pre-located isolation walls, buried layers, and channel-stops. The isolation walls are formed from a stacked arrangement of a dielectric region and a polycrystalline semiconductor region, above a doped channel-stop region which acts as a field guard. A single mask layer determines the location and spacing of the buried portions of the isolation walls, the channel-stops, and the buried layers.

Abstract: The efficacy of dielectrically isolated device formation on a substrate is substantially enhanced through a specific set of processing steps. In particular, before silicon oxide regions, e.g., gate oxide regions, are produced, bulk polycrystalline areas are heat treated to substantially increase their polycrystalline silicon grain size.

Abstract: Reduction of the encroachment of a grown field oxide layer during MOS device fabrication by covering a masking anti-oxidant layer that defines the active element area of a semiconductor substrate with a layer of passivation material which extends over the edge of the anti-oxidant layer to contact the pad oxide over the semiconductor substrate surface.

Abstract: A process is described for fabricating self-aligned buried doped regions in semiconductor devices and integrated circuits which avoids any need for delineation of the buried doped regions in the active portions of the device. Avoiding delineation improves the quality of the epitaxial layer used to cover the buried doped regions thereby improving overall performance and yield. Multiple mask layers are used in connection with a single mask pattern to achieve self-alignment. One mask layer consists of a material with a modifiable etch rate, e.g. polysilicon. A portion of the single crystal substrate is rendered non-single crystal and used as an alignment key which is propagated through the epitaxial layer grown over the undelineated buried doped regions. The dimensions and separations of the self-aligned buried doped regions can be precisely controlled.

Abstract: A semiconductor structure including a pair of single-crystal semiconductor bulk regions (10.3, 12.2) of differing first and second bulk conductivities, respectively, for forming semiconductor circuits therein, is fabricated whereby each such region is electrically isolated from the other and from a rigid body (20) supporting these regions. The structure is formed by forming at a major surface of a single crystal semiconductor water (10) having the first bulk conductivity a bulk zone (12.1) having the second bulk conductivity, followed by the steps of (1) forming in the wafer (10) at the major surface (10.6) thereof a V-shaped groove (10.2) at the boundary of the bulk zone (12.1) using a crystallographic orientation dependent etch, in order to define the regions (10.3, 12.2) of differing conductivities, (2) forming a dielectric layer (15.1, 15.

Abstract: Grooves are formed in a single crystal silicon wafer in a pattern to encircle surface areas. Silicon dioxide is placed in the grooves and on the surface and then removed from certain of the areas. Layers of silicon are epitaxially grown only on these areas and their surfaces are oxidized. Polycrystalline silicon is deposited to a thickness greater than that of the epitaxial layers. Both sides of the wafer are ground and polished to produce flat, planar, opposite surfaces; one surface exposing surface areas of the epitaxial layers, the other surface exposing the silicon dioxide in the grooves. The resulting substrate has two types of silicon sections, each of which is electrically isolated from the other by silicon dioxide partitions. One type of section is of silicon of the original wafer, has a surface area in only one surface, and is suitable for the fabrication of low voltage, low power devices therein.

Abstract: A method for fabricating a wafer for a dielectric isolation (DI) integrated circuit device is provided, wherein the substrate of the wafer, comprises portions of polycrystalline silicon positioned beneath regions for electrical elements, namely, "islands", and portions of single crystal silicon are positioned in other areas of the wafer such as scribing regions, peripheral regions and contact regions. The single crystal portions of the substrate are grown during its fabricating steps by exposing surfaces of an original substrate of single crystal silicon, before the deposition of silicon onto the original substrate, by removing a dielectric isolation layer over the predetermined regions to be exposed. The single crystal silicon portions of the wafer provide various advantages for subsequent mechanical processing of the wafer such as shaping and rounding of the peripheral region and the scribing of the wafer into dice.

Abstract: A sidewall-nitride isolation technology refines process control over lateral oxide encroachment by preventing any thinning of the nitride moat-masking layer during the nitride etch step which clears the sidewall nitride layer from the bottom of the etched recesses in silicon. This is done by initially patterning the moat regions in an oxide/nitride/oxide stack, rather than the nitride/oxide stack of the prior art.

Abstract: In a semiconductor device comprising at least one bipolar transistor and a VIP isolating layer which are formed in both an epitaxial layer and a semiconductor substrate, an impurity-introduced region having the same conductivity type as that of the semiconductor substrate is formed so as to surround the V-groove. A buried layer of the bipolar transistor comes into contact with the VIP isolating layer to divide the impurity-introduced region into two parts, one of which is combined with a base region and the other one of which serves as a channel stopper.

Abstract: A method of making semiconductor integrated circuit devices with narrow and deep isolation regions of polycrystalline silicon and wide and thick isolation regions of thermally grown silicon oxide. A multi-layer of a first silicon nitride layer, a polycrystalline silicon layer, a second silicon nitride layer and a silicon oxide layer are formed on a semiconductor body. A photoresist layer is applied on the surface of the silicon oxide layer. An opening is formed in the photoresist layer and the multi-layer. The silicon oxide layer under the photoresist layer is side-etched through the opening. The exposed polycrystalline layer is converted into another silicon oxide layer. Another opening surrounding the silicon oxide layer is formed to expose surfaces of the semiconductor body. Deep grooves are formed in the semiconductor body.

Abstract: An integrated circuit wherein the base and surface collector regions of the I.sup.2 L vertical transistor are formed by the same steps used to form the collector and base, respectively, of complementary bipolar transistors. Thus, a high voltage bipolar transistor of the same type as the vertical I.sup.2 L transistor may be formed using separate process steps, thereby optimizing the design of both devices.

Abstract: In the fabrication of integrated circuits, a method is provided for forming dielectrically isolated regions in a semiconductor substrate comprising forming over the semiconductor substrate surface an electrically insulating layer of dielectric material having a plurality of openings therethrough and etching to form recesses in the semiconductor substrate exposed in the openings. Then, aluminum is deposited over the substrate so that an aluminum layer is formed on said layer of dielectric material as well as in said recesses. Next, the aluminum in the recesses is selectively anodized to form aluminum oxide, and the remaining aluminum on said layer of dielectric material is removed either by selectively etching away the aluminum layer or by a "lift-off" technique wherein the insulating layer of dielectric material under the aluminum is etched away thereby "lifting-off" and removing the aluminum.

Abstract: A sidewall-nitride isolation technology avoids stress-induced defects, while permitting a heavy channel stop implant to avoid turn-on of the field oxide transistor, by performing a two-step silicon etch. The first channel stop implant is performed after the first silicon etch, before the sidewall nitride is deposited. A further silicon etch is performed after the sidewall nitride is in place, and a second channel stop implant follows. The first implant can be a light dose, to avoid excess subthreshold leakage in the active devices due to field-assisted turn on at the corners of the moat regions, and the second implant can be a very heavy dose to provide complete isolation without any danger of the channel stop species encroaching on the active device regions.

Abstract: A method is provided for manufacturing semiconductor structures having dielectrically isolated silicon regions on one side of a silicon body. This is accomplished by forming in the silicon body a set of buried regions and a set of surface regions having characteristics which make them anodically etch slower than the remaining portion of the silicon body. These two sets of regions define portions in the silicon body which are anodically etched to form porous silicon regions which are oxidized to form an isolation structure that isolates the silicon surface regions from each other and the remaining portion of the silicon body. Typically in a P-type silicon body the buried and surface regions are N-type regions formed through ion implantation.