Isolated Zones Patents (Class 148/DIG86)
  • Patent number: 5795801
    Abstract: A trench is formed in a substrate, the trench defining an active region surface on the substrate, the trench having a trench sidewall. A trench insulation region is then formed in the trench. The substrate underlying the trench sidewall is doped with impurities, and after the first doping, the substrate underlying the active region surface is doped with impurities to form a well having an impurity concentration which increases towards the trench sidewall in a predetermined manner. To form the trench, an insulation layer preferably is formed on the substrate, a barrier layer is formed on the insulation layer, and the barrier layer and the insulation layer are patterned to form an insulation region on the substrate and a barrier region on the insulation region. The substrate is then etched using the barrier region and the insulation region as a mask to thereby form a trench in the substrate.
    Type: Grant
    Filed: August 9, 1996
    Date of Patent: August 18, 1998
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Kang-yoon Lee
  • Patent number: 5770504
    Abstract: The preferred embodiment of the present invention overcomes the limitations of the prior art and provides a device and method to increase the latch-up immunity of CMOS devices by reducing the mobility of carriers between the devices. The preferred embodiment uses an implant formed beneath trench isolation between n-channel and p-channel devices. This implant preferably comprises relatively large/heavy elements implanted into the wafer beneath the trench isolation. The implant elements reduce the mobility of the charge carriers. This increases the latch-up holding voltage and thus reduces the likelihood of latch-up. The implants can be formed without the need for additional photolithography masks.
    Type: Grant
    Filed: March 17, 1997
    Date of Patent: June 23, 1998
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey S. Brown, Robert J. Gauthier, Jr., Xiaowei Tlan
  • Patent number: 5496760
    Abstract: A dielectrics dividing wafer, and a method of manufacturing the wafer, is disclosed in which embedded dielectric films are provided in the interior of the wafer in a predetermined pattern extending laterally parallel to a face surface of the wafer, and partition dielectric films, in the form of vertical walls extending from the face surface and the rear surface of the wafer, to the embedded dielectric films, are provided to define semiconductor areas extending continuously from the face surface of the wafer to the rear surface of the wafer. The semiconductor areas can be used for vertical circuit elements. The partition dielectric films in conjunction with the embedded dielectric films and the face surface of the wafer also define additional planar semiconductor areas that can be used for planar structure circuit elements.
    Type: Grant
    Filed: August 18, 1994
    Date of Patent: March 5, 1996
    Assignee: Fuji Electric Company, Ltd.
    Inventor: Kazuo Matsuzaki
  • Patent number: 5389563
    Abstract: A semiconductor device having a reduced leakage current is fabricated in a short time at a low cost with excellent controllability. A buried layer (20) which includes a principal buried layer (21) of high ion concentration containing secondary defects (22) sandwiched between secondary buried layers (3a, 3b) of low ion concentration from upper and lower directions is formed on a semiconductor substrate (1). The secondary defects (22) have stable gettering effects for reducing defects caused during formation of a transistor (200) and contamination by heavy metals. Further, the secondary buried layers (3a, 3b) prevent depletion layers from reaching the secondary defects (22). The semiconductor device can be formed in a short time since no epitaxial growth is employed.
    Type: Grant
    Filed: May 13, 1994
    Date of Patent: February 14, 1995
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Takashi Kuroi, Shigeru Kusunoki
  • Patent number: 5225358
    Abstract: Isolation and passivation structures are formed in a single step, after transistor fabrication, by CVD deposition of a layer of oxide or BPSG over the wafer. The passivation/isolation layer overfills trenches formed for isolation and covers the patterned transistor device The layer is subsequently planarized by chem-mech polishing. With only one deposition step involved, to form both isolation structures and a passivation layer, there is significantly less strain on the thermal budget. Process and product by process are disclosed.
    Type: Grant
    Filed: August 23, 1991
    Date of Patent: July 6, 1993
    Assignee: LSI Logic Corporation
    Inventor: Nicholas F. Pasch
  • Patent number: 5045492
    Abstract: A method for making an integrated circuit includes forming patches of a silicon nitride mask over the areas where a high-current vertical DMOS and/or NPN transistor, where a vertical NPN transistor and where the NMOS and PMOS transistors of a CMOS pair are to be formed. The nitride mask also includes patches over a network of P-type isolation walls, and two special patches over two special areas at which N+ plugs for the DMOS and NPN transistors are to be formed. A heavy field oxide is grown everywhere except at the nitride patches. The two special patches are selectively removed and by heating and diffusing phosphorous from a POCl.sub.3 source from C. to C. for at least 30 minutes, two very high conductivity N+ phosphorous plugs are formed through the epitaxial layer at a concentration of over 10.sup.20 phosphorous atoms/cm.sup.3, while the nitride serves to prevent the sensitive channel regions of the DMOS and CMOS transistors from phosphorous doping.
    Type: Grant
    Filed: September 25, 1989
    Date of Patent: September 3, 1991
    Assignee: Allegro Microsystems, Inc.
    Inventors: Wing K. Huie, Alexander H. Owens, David S. Pan
  • Patent number: 5039625
    Abstract: A Maximum Areal Density Recessed Oxide Isolation (MADROX) process for forming semiconductor devices, in which forms an insulating layer is formed on a monocrystalline silicon substrate and a patterned polycrystalline silicon-containing layer is formed on the insulating layer. The substrate is then subjected to a low temperature plasma assisted oxidation to form recessed oxide isolation areas in the exposed regions of the substrate, with minimal encroachment under the patterned polycrystalline silicon-containing layer. The patterned polycrystalline silicon-containing layer acts as a mask, without itself being oxidized. Low temperature recessed oxide isolation regions may thereby be formed, without "bird's beak" formation. Maximum Areal Density Bipolar and Field Effect Transistor (MADFET) devices may be formed, using the patterned polycrystalline silicon-containing layer as a device contact if desired.
    Type: Grant
    Filed: April 27, 1990
    Date of Patent: August 13, 1991
    Assignee: MCNC
    Inventors: Arnold Reisman, Mark Kellam, Charles K. Williams, Nandini Tandon
  • Patent number: 4874718
    Abstract: According to the present invention, an SOI film of a monocrystalline silicon film is formed by making solid phase epitaxial growth of an amorphous silicon layer formed on an oxide film. A through hole portion formed in the oxide film is formed in such a shape that an epitaxial growth region growing with the through hole portion as a nucleus covers the entire region of the amorphous silicon layer. After the SOI film is formed, oxygen ions are ioin-implanted into the through hole portion in the oxide film, to be embedded by an oxide film layer by thermal processing.
    Type: Grant
    Filed: July 28, 1988
    Date of Patent: October 17, 1989
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Yasuo Inoue
  • Patent number: 4818725
    Abstract: A direct moat wafer processing for maximizing the functional continuity of a field oxide layer employs a processing sequence through which respective differently sized apertures are successively formed in the oxide layer. A first of these apertures prescribes the size of the polysilicon gate, while a second aperture is formed around the completed gate structure and prescribes the geometry of source/drain regions to be introduced into exposed surface areas of the substrate on either side of the gate. The sidewalls of the first and subsequently formed, second aperture are effectively perpendicular to the substrate surface, thereby maintaining the functional continuity of the field oxide layer across the entirety thereof. Thereafter, a separate gate interconnect layer is selectively formed atop the field oxide layer to provide a conductive path to the gate.
    Type: Grant
    Filed: July 26, 1988
    Date of Patent: April 4, 1989
    Assignee: Harris Corp.
    Inventors: Richard L. Lichtel, Jr., Lawrence G. Pearce, Dryer A. Matlock
  • Patent number: 4702000
    Abstract: The problem of unwanted residual polysilicon stringers along the sidewalls of a field oxide layer employed in direct moat wafer processing is avoided by a processing scheme in which the sidewalls of the aperture in the field oxide layer are initially tapered prior to formation of the polysilicon layer to be used for the gate electrode(s). Because of the graduated thickness of the sidewalls of the field oxide layer, the thickness of the polysilicon layer formed thereon is substantially uniform over the entirety of the substrate. As a result, during subsequent masking of the polysilicon layer to define the gate electrode(s), all unmasked portions of the polysilicon are completely etched, leaving no residual material (e.g. stringers) that could be a source of device contamination.
    Type: Grant
    Filed: March 19, 1986
    Date of Patent: October 27, 1987
    Assignee: Harris Corporation
    Inventors: Dyer A. Matlock, Richard L. Lichtel, Jr., Lawrence G. Pearce
  • Patent number: 4631804
    Abstract: A technique is disclosed for the artificial introduction of a localized subsurface strained layer within a thick polysilicon layer to minimize the large change in warpage (defined as springback) which occurs in a (100) Si substrate thinning operation during the mechanical processing of dielectrically isolated (DI) wafers. This novel technique is capable of favorably altering the state of stress and the stress profile in the multicomponent "polysilicon/SiO.sub.2 /(100) Si" DI structure so as to reduce the natural springback in warpage that occurs when the stiffening member, the (100) Si substrate, is removed. This subsurface disturbed layer is retained within the polysilicon layer during subsequent processing to maintain the favorable stress profile with a minimum of wafer warpage. In one embodiment of the present invention, the subsurface strained layer is generated by growing an interface layer (SiO.sub.2 or Si.sub.3 N.sub.
    Type: Grant
    Filed: December 10, 1984
    Date of Patent: December 30, 1986
    Assignee: AT&T Bell Laboratories
    Inventor: Pradip K. Roy
  • Patent number: 4593459
    Abstract: Method of forming a substrate for fabricating CMOS FET's by forming sections of N and P-type conductivity in a body of silicon. Grooves are etched in the N and P-type sections to produce N and P-type sectors encircled by grooves. The surfaces of the grooves are oxidized, the grooves are filled with polycrystalline silicon, and exposed surfaces of the polycrystalline silicon are oxidized to form barriers which encircle the sectors and electrically isolate them. Shallow trenches are etched in regions of the body outside the N and P-type sectors and the trenches are filled with regions of silicon dioxide. A pair of complementary FET's are fabricated in the two sectors and a metal interconnection between them overlies a portion of a region of silicon dioxide.
    Type: Grant
    Filed: December 28, 1984
    Date of Patent: June 10, 1986
    Assignee: GTE Laboratories Incorporated
    Inventors: Paul E. Poppert, Marvin J. Tabasky, Eugene O. Degenkolb
  • Patent number: 4589193
    Abstract: Disclosed is the use of metal silicide (e.g. Pt-Si) contacts in boron lightly doped P.sup.- type silicon between two contiguous but not adjacent N.sup.+ type regions instead of employing the usual P.sup.+ implanted or diffused channel stoppers. The invention finds a particularly interesting application in polyimide filled deep trench isolated integrated circuits.The trench sidewalls are coated with an insulating material which is removed from the trench bottom at the all contact etch step. The Pt-Si is formed at the bottom of the trenches at the same time that the device contacts are made.
    Type: Grant
    Filed: June 29, 1984
    Date of Patent: May 20, 1986
    Assignee: International Business Machines Corporation
    Inventors: George R. Goth, Thomas A. Hansen, Robert T. Villetto, Jr.
  • Patent number: 4583281
    Abstract: A method of forming in a silicon substrate an active region bounded by a field of silicon dioxide is described. On top of a mesa formed in the silicon substrate is provided a three layered structure including a first thin layer of silicon dioxide in contact with the top of the mesa, a second thicker layer of silicon nitride overlying the thin layer of silicon dioxide and a third layer of silicon dioxide overlying the layer of silicon nitride. A further layer of silicon nitride is formed over the three layered structure and the exposed surfaces of the silicon substrate. Spacer portions of silicon nitride are formed on the sides of the mesa and the three layered structure by anisotropically etching the fourth layer of silicon nitride. By controlling the thicknesses of the first, second and third layers, the width of the spacer portions is optimized to prevent lateral oxidation of the active region.
    Type: Grant
    Filed: March 13, 1985
    Date of Patent: April 22, 1986
    Assignee: General Electric Company
    Inventors: Mario Ghezzo, Manjin J. Kim
  • Patent number: 4581814
    Abstract: The efficacy of dielectrically isolated device formation on a substrate is substantially enhanced through a specific set of processing steps. In particular, before silicon oxide regions, e.g., gate oxide regions, are produced, bulk polycrystalline areas are heat treated to substantially increase their polycrystalline silicon grain size.
    Type: Grant
    Filed: December 13, 1984
    Date of Patent: April 15, 1986
    Assignee: AT&T Bell Laboratories
    Inventors: George K. Celler, Pradip K. Roy, Donald G. Schimmel, Lee E. Trimble
  • Patent number: 4577394
    Abstract: Reduction of the encroachment of a grown field oxide layer during MOS device fabrication by covering a masking anti-oxidant layer that defines the active element area of a semiconductor substrate with a layer of passivation material which extends over the edge of the anti-oxidant layer to contact the pad oxide over the semiconductor substrate surface.
    Type: Grant
    Filed: October 1, 1984
    Date of Patent: March 25, 1986
    Assignee: National Semiconductor Corporation
    Inventor: John L. Peel
  • Patent number: 4574469
    Abstract: A process is described for producing isolated semiconductor devices in a common substrate which have self-aligned and pre-located isolation walls, buried layers, and channel-stops. The isolation walls are formed from a stacked arrangement of a dielectric region and a non-single crystal semiconductor region, above a doped channel-stop region. A single mask layer determines the location and spacing of the non-single crystal portion of the isolation walls, the channel-stops, and the buried layers.
    Type: Grant
    Filed: September 14, 1984
    Date of Patent: March 11, 1986
    Assignee: Motorola, Inc.
    Inventors: Sal Mastroianni, Carroll Casteel, Terry S. Hulseweh
  • Patent number: 4561172
    Abstract: A sidewall-nitride isolation technology refines process control over lateral oxide encroachment by preventing any thinning of the nitride moat-masking layer during the nitride etch step which clears the sidewall nitride layer from the bottom of the etched recesses in silicon. This is done by initially patterning the moat regions in an oxide/nitride/oxide stack, rather than the nitride/oxide stack of the prior art.
    Type: Grant
    Filed: June 15, 1984
    Date of Patent: December 31, 1985
    Assignee: Texas Instruments Incorporated
    Inventors: Christopher Slawinski, Robert R. Doering, Clarence W. Teng
  • Patent number: 4532700
    Abstract: A method is provided for manufacturing semiconductor structures having dielectrically isolated silicon regions on one side of a silicon body. This is accomplished by forming in the silicon body a set of buried regions and a set of surface regions having characteristics which make them anodically etch slower than the remaining portion of the silicon body. These two sets of regions define portions in the silicon body which are anodically etched to form porous silicon regions which are oxidized to form an isolation structure that isolates the silicon surface regions from each other and the remaining portion of the silicon body. Typically in a P-type silicon body the buried and surface regions are N-type regions formed through ion implantation.
    Type: Grant
    Filed: April 27, 1984
    Date of Patent: August 6, 1985
    Assignee: International Business Machines Corporation
    Inventors: Wayne I. Kinney, Jerome B. Lasky, Larry A. Nesbit