J-fet (junction Field Effect Transistor) Patents (Class 148/DIG88)
  • Patent number: 5670393
    Abstract: An electrical circuit and method combine junction field effect transistors (JFET) and metal oxide semiconductor (MOS) circuits in series between V.sub.DD and ground, with a feedback of output voltage to control current from V.sub.DD to ground. The electrical circuit comprises a complementary metal oxide semiconductor (CMOS) inverter circuit with an input and an output, and a JFET having a gate coupled to the CMOS inverter for feedback to control the JFET. The JFET and CMOS circuitry is formed on a common substrate with the JFET gate junction being formed by implanting impurity dopants through a layer of gate oxide.
    Type: Grant
    Filed: July 12, 1995
    Date of Patent: September 23, 1997
    Assignee: LSI Logic Corporation
    Inventor: Ashok K. Kapoor
  • Patent number: 5652153
    Abstract: A semiconductor device may include complementary NPN and PNP transistors and a JFET that is formed in the same steps as used to form the transistors. The bottom gate of the JFET and the back collector layer of the PNP transistor are doped and up-diffused in the same steps to cause the channel of the JFET and distance between the base and back collector layer of the PNP transistor to be the same. The JFET may have a low voltage capability (less than 5 volt pinch-off voltage) and the PNP transistor may have a breakdown voltage of at least 30 volts.
    Type: Grant
    Filed: October 16, 1995
    Date of Patent: July 29, 1997
    Assignee: Harris Corporation
    Inventor: James D. Beasom
  • Patent number: 5418178
    Abstract: A method for fabricating read-only memory ("ROM") devices utilizing junction field-effect transistors ("JFETs") having a conductive channel orthogonally oriented with respect to the surface of the semiconductor material composing the JFET. A fixed-position ion beam is employed to create this narrow gate channel, which extends between the JFET's source and drain contact. Employing such JFETs as basic memory sites within a semiconductor ROM circuit allows for an architecture that conforms to a minimum lattice structure layout. In addition, the resulting ROM offers high speed access of data. Although JFETs have not been utilized as the transistor of choice within ROMs because of their seemingly inferior performance when compared to MOSFETs, the invention provides a novel architecture which significantly enhances the practicality of the JFET as a memory device.
    Type: Grant
    Filed: June 17, 1994
    Date of Patent: May 23, 1995
    Assignee: AT&T Corp.
    Inventor: Masakazu Shoji
  • Patent number: 5118632
    Abstract: Radiation insensitivity and breakdown voltage characteristics of a dual region top gate JFET are improved by a top gate structure in which the entirety of the lower concentration region of the top gate is separated from the oxide/silicon interface by the top surface high impurity concentration region. The dual region top gate extends from the substrate/insulator interface to a channel region beneath the top surface of the JFET substrate and extends laterally to bridge the source and drain regions. The lateral extent of the dual region top gate may be deliminated by barrier regions, respectively separating the top gate regions from the source and drain regions. The barrier regions extend from the substrate/oxide interface to the channel and may comprise dielectric material or a combination of dielectric material and doped semiconductor material.
    Type: Grant
    Filed: November 5, 1990
    Date of Patent: June 2, 1992
    Assignee: Harris Corporation
    Inventor: Gregory A. Schrantz
  • Patent number: 5106770
    Abstract: In the fabrication of a junction field effect transistor, specifically a static induction transistor, an epitaxial layer of high resistivity N-type silicon is grown on a substrate of low resistivity N-type silicon. A plurality of elongated parallel grooves separated by interposed ridges are formed by reactive ion etching. A layer of silicon oxide is grown on all exposed surfaces including the side walls and bottoms of the grooves. Fluorine is ion implanted into the silicon oxide. The grooves are filled with deposited silicon oxide or polycrystalline silicon, and material is removed to form a flat planar surface with the silicon at the surfaces of the ridges exposed. P-type doping material is ion implanted into alternate (gate) ridges. The wafer is heated to diffuse the P-type doping material and form gate regions. Heating also activates the implanted fluorine ions which react with unbonded silicon atoms at the silicon oxide-silicon interface thus quenching vacant bond sites.
    Type: Grant
    Filed: November 16, 1990
    Date of Patent: April 21, 1992
    Assignee: GTE Laboratories Incorporated
    Inventors: Emel S. Bulat, Richard M. Klein
  • Patent number: 5106778
    Abstract: A vertical transistor device is characterized by active regions vertically separated by a narrower control region. The control region is defined by conducting layer extensions which extend into a groove within which semiconductor material is regrown during device fabrication. The device is further characterized by regions of isolating material, located horizontally adjacent to the active regions, said isolating material serving to reduce parasitic capacitance and improve thermal distribution within the device, thereby improving frequency and power performance.
    Type: Grant
    Filed: February 16, 1990
    Date of Patent: April 21, 1992
    Assignee: Massachusetts Institute of Technology
    Inventors: Mark A. Hollis, Carl O. Bozler, Kirby B. Nichols, Normand J. Bergeron, Jr.
  • Patent number: 5045497
    Abstract: A semiconductor device includes a semiconductor body and a metal contact forming a Schottky barrier with said body, the metal contact including a layer of nickel disposed on the semiconductor body, an aluminum layer disposed on the nickel layer, and a nickel aluminum alloy disposed at the interface of the layers. The alloy is formed by heating the metal layers.
    Type: Grant
    Filed: October 25, 1989
    Date of Patent: September 3, 1991
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Kazuo Hayashi, Takuji Sonoda
  • Patent number: 5015596
    Abstract: A GaAs JFET according to the present invention is formed as follows. First, an n type active layer is formed on a GaAs substrate. Then, a gate electrode containing a group II element is formed on the n type active layer. With the gate electrode being used as a mask, an n type impurity is ion-implanted in the GaAs substrate with a high concentration in a self-aligned fashion with respect to the gate electrode. Heat-treatment is then performed on the resultant structure to diffuse the group II element in the gate electrode into the n type active layer, forming a p type gate region. At the same time, the ion-implanted n type impurity is activated, forming source and drain regions.
    Type: Grant
    Filed: February 8, 1990
    Date of Patent: May 14, 1991
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Nobuyuki Toyoda, Naotaka Uchitomi, Akimichi Hojo
  • Patent number: 4895811
    Abstract: In a method of manufacturing a GaAsFET, an insulating film used as a mask for implanting ions to form a gate region is used as a mask for sputtering a material of a gate electrode. Consequently, the gate electrode is formed to be aligned with the gate region. A GaAsFET in which the gate electrode can be stably positioned with respect to the small gate region with a high degree of accuracy and which is suitable for high frequency applications can be manufactured.
    Type: Grant
    Filed: October 4, 1988
    Date of Patent: January 23, 1990
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kazuhiko Inoue
  • Patent number: 4889826
    Abstract: A static induction transistor has in a surface region of a first type of high-resistance semiconductor a source region formed by a first type of diffusion layer and a gate region which surrounds said source region from at least two directions and which is formed by a second type of diffusion layer which is diffused deeper than the layer of source region, the static induction transistor also having a first or second type of impurity layer formed immediately beneath the source region thereof. A second type of impurity layer is further formed in the surface region of the first type of high-resistance semiconductor outside of the gate region. Furthermore, a first type of impurity layer is formed in the surface region of the first type of high-resistance semiconductor, or a first or a second type of impurity layer is formed in the surface region of the first type of high-resistance semiconductor between the source region and the gate region at the same depth as or shallower than the source region.
    Type: Grant
    Filed: October 3, 1988
    Date of Patent: December 26, 1989
    Assignee: Olympus Optical Co., Ltd.
    Inventor: Yoshinori Ohta
  • Patent number: 4833095
    Abstract: The fabrication of high performance and reliable Buried Channel Field Effect Transistor (BCFET) using Schottky gate junction and heavily doped N layers for the source and drain electrode is described. The BCFET is composed of a semi-insulating substrate in which two N layers for the drain electrodes and one N layer for the source electrode are formed in one of the semi-insulating surface. The N source electrode is centrally located between the two N drain electrodes and all three lie in the same plane. The source and drain electrodes are separated by a thin semi-insulating layer, the length of which can range from 0.5 micron to several micron range, depending on the desired voltage breakdown. A Schottky gate is defined in an active N layer directly above the source N Layer. The ohmic contacts for the source and drain N layers are defined several microns away from the schottky junction, resulting in a considerable improvement in device reliability.
    Type: Grant
    Filed: December 4, 1987
    Date of Patent: May 23, 1989
    Assignee: Eaton Corporation
    Inventor: Calviello, Joseph A.
  • Patent number: 4808547
    Abstract: A high voltage bipolar and JFET have their gate and base connected and source and collector connected and the appropriate geometry for the bipolar to operate to its BV.sub.CBO limit. The collector and channel regions have the same depth and impurity concentration, the base and top gate regions have the same depth and impurity concentration and the emitter and source and drain regions have the same depth and impurity concentration.
    Type: Grant
    Filed: December 9, 1987
    Date of Patent: February 28, 1989
    Assignee: Harris Corporation
    Inventor: James D. Beasom
  • Patent number: 4729967
    Abstract: Method of fabricating a junction field effect transistor, specifically a static induction transistor, which may be of GaAs. Elongated N-type source regions are formed in an N-type epitaxial layer of semiconductor material grown on a substrate. A tri-level mask is formed having elongated openings exposing portions of the epitaxial layer intermediate between the source regions. The openings are wider at the bottom than at the top. P-type gate regions are formed by ion-implanting P-type doping material through the mask openings. Silicon dioxide is deposited through the openings by angle evaporation to form generally trapezoidal-shaped temporary gate members over the gate regions. The tri-level mask is removed, a layer of silicon nitride is deposited, and a layer of masking material is deposited. Some of the masking material is removed; then the temporary gate members and silicon nitride immediately adjacent thereto are removed.
    Type: Grant
    Filed: April 9, 1987
    Date of Patent: March 8, 1988
    Assignee: GTE Laboratories Incorporated
    Inventor: Craig A. Armiento
  • Patent number: 4724220
    Abstract: The fabrication of high performance and reliable Buried Channel Field Effect Transistor (BCFET) using Schottky gate junction and heavily doped N layers for the source and drain electrode is described. The BCFET is composed of a semi-insulating substrate in which two N layers for the drain electrodes and one N layer for the source electrode are formed in one of the semi-insulating surface. The N source electrode is centrally located between the two N electrodes and all three lie in the same plane. The source and drain electrodes are separated by a thin semi-insulating layer, the length of which can range from 0.5 micron to several micron range, depending on the desired voltage breakdown. A Schottky gate is defined in an active N layer directly above the source N layer. The ohmic contacts for the source and drain N layers are defined several microns away from the Schottky junction, resulting in a considerable improvement in device reliability.
    Type: Grant
    Filed: January 10, 1986
    Date of Patent: February 9, 1988
    Assignee: Eaton Corporation
    Inventor: Joseph A. Calviello
  • Patent number: 4698653
    Abstract: A field effect transistor is disclosed similar to a junction field effect transistor, but in which the depletion width in the channel due to a PN junction adjoining the channel is controlled not by directly controlling the reverse voltage on the PN junction, but by reverse biasing a second PN junction such that the depletion region from the second PN junction meets the depletion region from the first PN junction (on the side other than the channel side) to thus restrict the width of the depletion regions due to the first PN junction.
    Type: Grant
    Filed: October 9, 1979
    Date of Patent: October 6, 1987
    Inventor: Walter T. Cardwell, Jr.
  • Patent number: 4698652
    Abstract: Herein disclosed is a semiconductor device in which control means for carriers migrating in a first semiconductor includes an interface state layer lying on the first semiconductor and a second conductor layer lying on the interface state layer. The interface state layer has its Fermi level pinned to that of the second semiconductor layer. By thus constructing an FET or the semiconductor device, an inversion or accumulation layer can be easily formed in the interface merely by applying a voltage to the control means.
    Type: Grant
    Filed: May 8, 1985
    Date of Patent: October 6, 1987
    Assignee: Hitachi, Ltd.
    Inventors: Yasunari Umemoto, Susumu Takahashi, Yuichi Ono
  • Patent number: 4651407
    Abstract: Junction field effect transistor and method of fabrication. An epitaxial layer of high resistivity N-type silicon is grown on a substrate of low resistivity silicon. A layer of silicon dioxide is grown on the surface of the epitaxial layer and selectively removed to expose silicon in a pattern of a plurality of parallel surface areas with parallel strips of silicon dioxide in between. A second epitaxial layer is deposited over the exposed surface areas and the strips of silicon dioxide. Barriers of silicon dioxide are formed in the second epitaxial layer extending from the surface to adjacent to but spaced from the edges of the buried strips. P-type conductivity imparting material is implanted and then diffused into the zones of the second epitaxial layer defined by adjacent barriers and overlying the buried strips to form gate regions.
    Type: Grant
    Filed: May 8, 1985
    Date of Patent: March 24, 1987
    Assignee: GTE Laboratories Incorporated
    Inventor: Izak Bencuya
  • Patent number: 4632710
    Abstract: An epitaxially grown high resistivity crystalline layer of gallium arsenide is produced in a reactor vessel with a predetermined amount of carbon dioxide introduced during growth of the high resistivity gallium arsenide (GaAs) crystalline layer to provide carbon as a dopant. Thus, a plurality of carbon atoms is provided in the crystal, such carbon atoms having electrons at energy levels between a valance energy band and a conduction energy band of the GaAs crystal. With these energy levels, the carbon atoms are substantially ionized at room temperature by accepting a plurality of electrons from the valance band of the GaAs. The presence of these carbon ions in the crystal compensates for a stoichiometric defect which occurs during epitaxial growth of the GaAs crystalline layer. This results in a high resistivity layer which provides a buffer layer between a GaAs substrate and an active GaAs layer.
    Type: Grant
    Filed: May 10, 1983
    Date of Patent: December 30, 1986
    Assignee: Raytheon Company
    Inventor: H. Barteld Van Rees
  • Patent number: 4601096
    Abstract: The fabrication of high performance and reliable Buried Channel Field Effect Transistor (BCFET) using Schottky gate junction and heavily doped N layers for the source and drain electrode is described. The BCFET is composed of a semi-insulating substrate in which two N layers for the drain electrodes and one N layer for the source electrode are formed in one of the semi-insulating surface. The N source electrode is centrally located between the two N drain electrodes and all three lie in the same plane. The source and drain electrodes are separated by a thin semi-insulating layer, the length of which can range from 0.5 micron to several micron range, depending on the desired voltage breakdown. A Schottky gate is defined in an active N layer directly above the source N layer. The ohmic contacts for the source and drain N layers are defined several mcirons away from the Schottky junction, resulting in a considerable improvement in device reliability.
    Type: Grant
    Filed: February 19, 1985
    Date of Patent: July 22, 1986
    Assignee: Eaton Corporation
    Inventor: Joseph A. Calviello
  • Patent number: 4545109
    Abstract: A method of producing a high frequency III-V FET and the resultant structure is described wherein a doped layer is formed on a wafer of undoped, semi-insulating III-V material. The structure is then etched to form a mesa after which, a channel region is regrown from an exposed portion of the III-V substrate. The formation of the channel region defines the source and drain regions. Ohmic contacts are then made to the source and drain regions after which a Schottky contact is made to the channel region.
    Type: Grant
    Filed: January 21, 1983
    Date of Patent: October 8, 1985
    Assignee: RCA Corporation
    Inventor: Walter F. Reichert
  • Patent number: 4528745
    Abstract: A method for the formation of buried gates in a semiconductor device using epitaxial growing method combined with diffusion method or diffusion by an additional heat treatment. The buried gate has smaller gate resistance by providing relatively high impurity concentration and also having good reverse characteristic by providing relatively low impurity concentration at the top of the buried gates.
    Type: Grant
    Filed: July 6, 1983
    Date of Patent: July 16, 1985
    Assignee: Toyo Denki Seizo Kabushiki Kaisha
    Inventor: Kimihiro Muraoka
  • Patent number: H390
    Abstract: An improved performance MESFET device incorporating a structure fabricated utilized self-aligned gate process technology. The edges of the gate electrode formed are separated from the edges of the dopant regions implanted in the device substrate by a distance which optimizes device performance. In order to increase process yield, a layer of dielectric material is deposited on the substrate surface and then annealed to protect the gate electrode and both stabilize and planarize the substrate surface.
    Type: Grant
    Filed: May 28, 1986
    Date of Patent: December 1, 1987
    Assignee: The United States of America as represented by the Secretary of the Air Force
    Inventors: Robert E. Lee, Harold M. Levy