Laser Beam Processing Of Fets Patents (Class 148/DIG91)
  • Patent number: 6130120
    Abstract: A method and structure for crystallizing film is disclosed. The method includes the steps of forming a film on a substrate, forming a lens on the film to focus an electro-magnetic wave on the film and directing the electro-magnetic wave on the film inclusive of the lens to crystallize the film.
    Type: Grant
    Filed: July 17, 1997
    Date of Patent: October 10, 2000
    Assignee: Goldstar Electron Co., Ltd.
    Inventor: Min Hwa Park
  • Patent number: 5858807
    Abstract: A method of manufacturing a liquid crystal display device, which comprises the steps of forming an amorphous silicon layer on a substrate, and irradiating, by way of scanning, a linear energy beam onto the amorphous silicon layer, thereby converting an irradiated portion of the an amorphous silicon layer into a polycrystalline silicon layer. The irradiation and scanning of the linear energy beam are performed plural times while shifting the scanning of the linear energy beam so as to allow the irradiation of the linear energy beam to cover every region of the amorphous silicon layer that is desired to be converted into a polycrystalline silicon layer.
    Type: Grant
    Filed: August 23, 1996
    Date of Patent: January 12, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Shinichi Kawamura
  • Patent number: 5851859
    Abstract: The present invention is related to a method for manufacturing a thin film transistor which can improve the yield, characteristics and reliability of the thin film transistor by selectively forming a semiconductor layer on a desired portion using a of a substrate using a temperature difference of the surface of a substrate achieve by heating the substrate with a lamp. The method comprises the steps of forming a black matrix layer of metal on a portion of the whole surface of an insulating glass substrate, forming an insulating layer for protecting the substrate on the whole substrate including the black matrix layer, forming source/drain electrodes on the insulating layer over the black matrix, selectively forming a semiconductor layer on the insulating layer including the source/drain electrodes, forming a gate insulating layer and forming a gate electrode.
    Type: Grant
    Filed: March 7, 1997
    Date of Patent: December 22, 1998
    Assignee: Goldstar Co., Ltd.
    Inventor: Jeong Hyun Kim
  • Patent number: 5817548
    Abstract: A method for crystallizing a portion of a semiconductor thin film while forming a semiconductor device comprises providing a transparent substrate supporting a metallic gate electrode and an amorphous semiconductor thin film which are separated from each other by a gate insulating film, heating the gate electrode by subjecting it to light rays, and applying a laser beam to the amorphous semiconductor thin film so that the portion of the semiconductor thin film adjacent the metallic gate electrode is heated by both the laser beam and the heat of the gate electrode to cause a crystallization of a portion of the amorphous thin film and then processing the remaining amorphous portions of the thin film to form the transistor structure.
    Type: Grant
    Filed: November 8, 1996
    Date of Patent: October 6, 1998
    Assignee: Sony Corporation
    Inventors: Takashi Noguchi, Yasushi Shimogaichi
  • Patent number: 5466617
    Abstract: Body portions (36) of semiconductor crystalline silicon material of sufficient quality to form high-mobility TFTs (thin-film transistors) and other semiconductor devices of a driver circuit are formed by depositing on a substrate (14) a layer of insulating silicon-based non-stoichiometric compound material (32) and then converting this material (32) into the semiconductive crystalline material (36) by heating with an energy beam (40), for example from an excimer laser. The use of an energy beam (40) permits easy localization of the heating (and consequent conversion) both vertically and laterally. The deposition (e.g. by plasma-enhanced chemical vapour deposition) and the beam annealing can both be carried out without heating the substrate (14) to high temperatures, and so a glass or other low-cost substrate (14) can be used. An unconverted part (32a) underlying the crystalline silicon body portion (36) can form at least part of a gate insulator of the TFT.
    Type: Grant
    Filed: June 15, 1994
    Date of Patent: November 14, 1995
    Assignee: U.S. Philips Corporation
    Inventor: John M. Shannon
  • Patent number: 5403762
    Abstract: Two kinds of TFTs are fabricated by the same process with a high production yield to manufacture an active-matrix circuit and a peripheral driver circuit on the same substrate. The active-matrix circuit is required to have a high mobility and a high ON/OFF current ratio. The peripheral driver circuit needs a complex interconnection structure. The active-matrix circuit and the peripheral driver circuit comprising the TFTs are fabricated monolithically. In this step, the gate electrodes of the TFTs of the active-matrix circuit are coated with an anodic oxide on their top and side surfaces. The gate electrodes of the TFTs of the peripheral driver circuit are coated with the anodic oxide on only their top surfaces; substantially no anodic oxide is present on the side surfaces.
    Type: Grant
    Filed: June 28, 1994
    Date of Patent: April 4, 1995
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yasuhiko Takemura
  • Patent number: 5306651
    Abstract: A process for preparing a polycrystalline semiconductor thin film transistor wherein a non-singlecrystalline semiconductor formed on a transparent insulating substrate is annealed by laser beams, such process comprising forming a gate insulation layer and a gate electrode on the non-singlecrystalline semiconductor; implanting impurity ions into a source-drain region of the semiconductor wherein the gate electrode is used as a mask, and irradiating laser beams from the rear surface side of the transparent insulating substrate to thereby polycrystallize the non-singlecrystalline semiconductor under the gate electrode or improve the crystallinity of the semiconductor without causing the non-singlecrystalline semiconductor in a completely molten state.
    Type: Grant
    Filed: May 10, 1991
    Date of Patent: April 26, 1994
    Assignee: Asahi Glass Company Ltd.
    Inventors: Kunio Masumo, Masanori Yuki
  • Patent number: 5281553
    Abstract: The state of conduction of an MOS transistor 11 is definitively controlled by a laser beam 21, by forming an electrical connection 22 between the gate 16 and the subjacent portion d of the source region 14 or drain region 15. The invention is applicable in particular to the correction (reconfiguration, redundancy) of integrated circuits and to the programming of integrated PROMs.
    Type: Grant
    Filed: February 22, 1991
    Date of Patent: January 25, 1994
    Assignee: Bull, S.A.
    Inventors: Alain Boudou, Marie-Francois Bonnal, Martine Rouillon-Martin
  • Patent number: 5091334
    Abstract: A semiconductor device which has a non-single crystal semiconductor layer formed on a substrate and in which the non-single crystal semiconductor layer is composed of a first semiconductor region formed primarily of non-single crystal semiconductor and a second semiconductor region formed primarily of semi-amorphous semiconductor. The second semiconductor region has a higher degree of conductivity than the first semiconductor region so that a semiconductor element may be formed.
    Type: Grant
    Filed: March 5, 1990
    Date of Patent: February 25, 1992
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yujiro Nagata
  • Patent number: 5077233
    Abstract: A random layout of devices, or at least active regions of devices, is achieved in fabricating semiconductor integrated circuits based on SOI technology using an anti-reflecting film. Windows are opened in the anti-reflecting film at positions corresponding to preselected regions of the semiconductor layer in which corresponding devices are to be formed, thereby to expose at least the surface area of each preselected region corresponding to the active region of the device to be formed therein. For each window, an energy beam substantially uniformly irradiates the exposed surface area including a portion of the anti-reflecting film bordering the window, sufficiently to heat the semiconductor layer and recrystallize the region thereof corresponding to the exposed surface area to a single crystalline form, free of grain boundaries. Self-aligned single crystal regions thus are fabricated in the polycrystalline silicon layer at the respective predetermined device regions.
    Type: Grant
    Filed: April 23, 1990
    Date of Patent: December 31, 1991
    Assignee: Fujitsu Limited
    Inventor: Ryoichi Mukai
  • Patent number: 5045501
    Abstract: An integrated circuit structure and method of forming the same is described in which a plurality of common signal planes are provided for an integrated circuit formed on a layer of semiconductive material (30). The common planes consist of a single crystal semiconductive substrate (2) and at least one conductive layer (26, 66) between the substrate (2) and the semiconductive circuit layer (30), with insulative layers (24, 28, 68) separating the conductive layers (26, 66) from each other and from the substrate (2) and semiconductive layer (30). When one conductive layer (26) is used, a power supply signal (V+) is preferably applied to the substrate (2) and a ground reference to the conductive layer (26). Contacts are made between the integrated circuit and the desired common planes by metallized contacts (56, 60) formed in openings (54, 58) through the underlying material. Various circuit signals can also be introduced through additional conductive layers.
    Type: Grant
    Filed: August 15, 1988
    Date of Patent: September 3, 1991
    Assignee: Hughes Aircraft Company
    Inventor: Jan Grinberg
  • Patent number: 5024968
    Abstract: A method and apparatus for removing surface contaminants from the surface of a substrate by high-energy irradiation is provided. The invention enables removal of surface contaminants without altering of the substrate's underlying molecular structure. The source of high-energy irradiation may comprise a pulsed laser.
    Type: Grant
    Filed: July 8, 1988
    Date of Patent: June 18, 1991
    Inventor: Audrey C. Engelsberg
  • Patent number: 5008211
    Abstract: An improved FET is disclosed. The transistor is characterized in that its channel is constituted in the form of a super lattice. The super lattice structure provides a number of square well potential areas through which carriers can pass with little interaction with the gate insulating film.
    Type: Grant
    Filed: September 14, 1989
    Date of Patent: April 16, 1991
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 4997780
    Abstract: The structure of a pair of concentrically disposed field effect transistors responsive to a common gate electrode, and a process for the fabrication thereof. In one form, a dielectric region is surrounded by an active region of monocrystalline silicon and has situated upon the dielectric region a layer of recrystallized silicon as a second active region. A gate electrode overlies both active regions and serves as a mask to form in such respective regions self-aligned channels. The concentric placement of the active substrate monocrystalline silicon region, and inner perimeter of dielectric, and a further inner active region of recrystallized silicon situated over a dielectric region, facilitates recrystallization from seed of monocrystalline silicon irrespective of the direction of translation taken by the energy beam, and associated melt, in scanning across the structure.
    Type: Grant
    Filed: September 21, 1988
    Date of Patent: March 5, 1991
    Assignee: NCR Corporation
    Inventors: Nicholas J. Szluk, Jay T. Fukumoto
  • Patent number: 4988634
    Abstract: An improved FET is disclosed. The transistor is characterized in that its channel is constituted in the form of a super lattice. The super lattice structure provides a number of square well potential areas through which carriers can pass with little interaction with the gate insulating film.
    Type: Grant
    Filed: April 16, 1990
    Date of Patent: January 29, 1991
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 4963503
    Abstract: A liquid crystal display device comprises, a plurality of display electrodes which are selectively energized through on-off control of thin film transistors. In order to reduce the channel length of the thin film transistors to increase operation speed and obtain uniform characteristics each display electrode and an associated transistor source electrode is formed on one of a pair of transparent substrates of the liquid crystal display device, a semiconductor layer is formed between the display electrode and source electrode, a gate insulating film is formed on the semiconductor layer, and a gate electrode is formed on a portion of the gate insulating film between the display electrode and source electrode. Then, ions are implanted into the semiconductor layer with the gate electrode used as a mask, thus rendering portions of the semiconductor layer contiguous to the display electrode and source electrode into ohmic layers.
    Type: Grant
    Filed: March 29, 1989
    Date of Patent: October 16, 1990
    Assignee: Hosiden Electronics Co., Ltd.
    Inventors: Shigeo Aoki, Yasuhiro Ugai, Katsumi Miyake, Kotaro Okamoto
  • Patent number: 4822752
    Abstract: Disclosed herein is a process for producing a single crystal layer of a semiconductor device, which comprises the steps of providing an oxide insulator layer separated by an opening part for seeding, on a major surface of a single crystal semiconductor substrate of the cubic system, providing a polycrystalline or amorphous semiconductor layer on the entire surface of the insulator layer inclusive of the opening part, then providing a protective layer comprising at least a reflective or anti-reflection film comprising strips of a predetermined width, in a predetermined direction relative to the opening part and at a predetermined interval, the protective layer capable of controlling the temperature distributions in the semiconductor layer at the parts corresponding to the stripes or the parts not corresponding to the stripes, thereby completing a base for producing a semiconductor device, thereafter the surface of the base is irradiated with an energy beam through the striped reflective or anti-reflection film
    Type: Grant
    Filed: March 6, 1987
    Date of Patent: April 18, 1989
    Assignee: Agency of Industrial Science and Technology
    Inventors: Kazuyuki Sugahara, Tadashi Nishimura, Shigeru Kusunoki, Yasuo Inoue
  • Patent number: 4822751
    Abstract: A thin film semiconductor device is formed by preparing a substrate, forming a pattern of metal thin film on the substrate, forming an insulating layer on the metal thin film, and forming a pattern of a semiconductor thin film active layer, which is self-aligned to the pattern of the metal thin film, by laser CVD.
    Type: Grant
    Filed: March 31, 1987
    Date of Patent: April 18, 1989
    Assignee: Mitsubishi Denki Kabushi Kaisha
    Inventors: Akira Ishizu, Tadashi Nishimura, Yasuo Inoue
  • Patent number: 4783424
    Abstract: A semiconductor device comprising a first conductor having first and second portions which are electrically disconnected from each other, and a second conductor, formed on an insulating film separating it from the first conductor, which is electrically conductive. A radiated energy beam renders the second conductor non-conductive, while simultaneously electrically connecting the first and second portions, rendering the first conductor conductive, as needed.
    Type: Grant
    Filed: February 21, 1986
    Date of Patent: November 8, 1988
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Jun-ichi Ohno, Satoshi Konishi
  • Patent number: 4778775
    Abstract: Improved processing for forming an interconnect in a process where a recrystallized polysilicon layer is formed over an insulative layer and where recrystallization takes place through a plurality of seed windows formed in the insulative layer. A doped region is formed in the substrate prior to deposition of the polysilicon layer. The polysilicon layer is in contact with at least a portion of the doped region through an opening in the insulative layer. Recrystallization takes place through this opening, and, for instance, the doped region is electrically connected to a source or drain region of a semiconductor device formed in the recrystallized layer.
    Type: Grant
    Filed: May 27, 1987
    Date of Patent: October 18, 1988
    Assignee: Intel Corporation
    Inventor: J. C. Tzeng
  • Patent number: 4764485
    Abstract: A method for producing a hole in a polymer film includes the steps of depositing a conductive layer onto the polymer film and irradiating a spot on the layer with a burst of focused laser energy at a level sufficient to form an opening in the film and, subsequently, plasma etching the film so as to form a hole of desired depth in the polymer film underlying the opening in the conductive layer. This method is particularly applicable to the formation of multichip intergrated circuit packages in which a plurality of chips formed in a semiconductor wafer are coated with a polymer film covering the chips and the substrates. The holes are provided for the purpose of interconnecting selected chip contact pads via a deposited conductive layer which overlies the film and fills the holes.
    Type: Grant
    Filed: January 5, 1987
    Date of Patent: August 16, 1988
    Assignee: General Electric Company
    Inventors: James A. Loughran, James G. McMullen, Alexander J. Yerman
  • Patent number: 4708747
    Abstract: The thickness of the dielectric material of an integrated circuit on top of which is provided a semiconductor layer, is selected to be an integer multiple of one-half the wavelength of the laser light in the dielectric material in order to make the dielectric material layer invisible to the laser-trimming light.
    Type: Grant
    Filed: October 16, 1986
    Date of Patent: November 24, 1987
    Assignee: Harris Corporation
    Inventor: William E. O'Mara, Jr.
  • Patent number: 4651408
    Abstract: In a process for manufacturing vertically integrated MOS devices and circuits, gate oxide and a gate are formed on a semiconductor substrate such as a silicon substrate. A layer of polysilicon is then deposited over the wafer, the polysilicon contacting the substrate silicon through a window in the gate oxide. The substrate silicon and the polysilicon are then laser melted and cooled under conditions that encourage crystal seeding from the substrate into the polysilicon over the gate. Subsequently, ions are implanted into the silicon substrate and the polysilicon to form source and drain regions. By introducing the source and drain dopants after melt associated seeding of the polysilicon, the risk of dopant diffusion into the device channel regions is avoided.
    Type: Grant
    Filed: May 17, 1984
    Date of Patent: March 24, 1987
    Assignee: Northern Telecom Limited
    Inventors: Thomas W. MacElwee, Iain D. Calder, James J. White
  • Patent number: 4646426
    Abstract: In the production of an MOS transistor or a one-MOS transistor one-capacitor memory cell, a gate electrode is made of aluminum, doped regions are formed by an ion-implantation method using the gate electrode as a mask, and the doped regions are annealed by a laser beam.
    Type: Grant
    Filed: April 8, 1985
    Date of Patent: March 3, 1987
    Assignee: Fujitsu Limited
    Inventor: Nobuo Sasaki
  • Patent number: 4621411
    Abstract: Optical illumination rather than furnace heating is used to drive in MOSFET source and drain diffusions, preferably using a surface layer of antimony as the dopant source. This results in substantially less overlap between the gate and the source and drain diffusions. Similarly, if the present invention is practiced in a process having gate sidewalls less than zero overlap can be achieved.
    Type: Grant
    Filed: September 28, 1984
    Date of Patent: November 11, 1986
    Assignee: Texas Instruments Incorporated
    Inventors: Robert H. Havemann, Vernon R. Porter
  • Patent number: 4619034
    Abstract: Disclosed is a nonvolatile memory device which utilizes a laser beam recrystallized silicon layer having source-channel-drain regions. Underlying the recrystallized layer and separated therefrom by a memory dielectric is a gate in alignment with the source and drain. The gate is formed directly on a substrate of an insulative material (e.g. non-silicon material).The process of forming the above device comprises forming a conductive polysilicon gate on a substrate followed by a memory nitride layer deposition thereon. A thick oxide layer is formed over the nitride followed by removal of the thick oxide corresponding to a central portion of the gate thereby exposing the nitride therebeneath. The exposed nitride surface is thermally converted into a thin, stoichiometric memory SiO.sub.2. A doped polysilicon layer is then formed on the structure and thereafter converted to recrystallized silicon by subjecting it to laser radiation.
    Type: Grant
    Filed: March 11, 1985
    Date of Patent: October 28, 1986
    Assignee: NCR Corporation
    Inventor: John L. Janning
  • Patent number: 4587720
    Abstract: The process consists in producing the grid (4) of the transistor on a glass substrate (2), depositing an insulating layer (6) on the substrate and grid, depositing a thick layer (8) of hydrogenated amorphous silicon on the insulating layer, depositing on the silicon layer a layer (10) of positive photosensitive resin sensitive to light of a wavelength greater than 550 nm, irradiating the resin layer through the substrate, the grid serving as a mask for the irradiation, developing the resin, etching the silicon layer until the insulating layer is bared, the remanent resin serving as a mask for the etching, depositing the layers permitting the making of the electrical contacts and the electrodes of the source and of the drain, eliminating the remanent resin (10a), and etching the electrodes of the source and of the drain.
    Type: Grant
    Filed: October 10, 1984
    Date of Patent: May 13, 1986
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Andre Chenevas-Paule, Bernard Diem
  • Patent number: 4523962
    Abstract: A method for fabricating a monocrystalline semiconductor layer on an insulating layer in the production of a semiconductor device wherein the location of grain boundaries is accurately controlled, thereby making the crystal orientation of the monocrystalline semiconductor layer uniform over a large area. An antireflection layer is formed above a polycrystalline of amorphous semiconductor layer formed on a main face of a monocrystalline semiconductor substrate which contacts the monocrystalline semiconductor substrate through windows formed in a thick insulating layer. The antireflection layer includes a first portion which covers all of the area of the polycrystalline or amorphous semiconductor layer above the windows, and a second portion, which has the form of a grid composed of parallel lines extending from the first portion in the direction of the crystallographic axis of the monocrystalline semiconductor substrate and partially covering a second area between the first areas.
    Type: Grant
    Filed: December 13, 1983
    Date of Patent: June 18, 1985
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Tadashi Nishimura