Laser Beam Treatment In General Patents (Class 148/DIG93)
  • Patent number: 5904550
    Abstract: A method of preparing a semiconductor device, comprising: forming an amorphous silicon layer on a substrate, and applying shots of an excimer laser beam to the amorphous silicon layer to convert the amorphous silicon layer into a polysilicon layer having a plurality of silicon grains, each of the grains having a grain size and including a crystallite having a crystallite size on the (111) plane, an average value of the crystallite sizes on the (111) plane of the crystallites included in the polysilicon layer being sixty percent or greater of an average value of the grain size.
    Type: Grant
    Filed: November 19, 1996
    Date of Patent: May 18, 1999
    Assignee: Casio Computer Co., Ltd.
    Inventor: Michiya Yamaguchi
  • Patent number: 5897381
    Abstract: Rapid Thermal Processing of a semiconductor wafer is performed by scanning a laser beam across a silicon dioxide film in contact with a surface of the wafer. The silicon dioxide film absorbs the energy from the laser beam and converts the energy to heat. The heat, in turn, is transferred to the wafer. Temperature feedback can be obtained to increase control and uniformity of temperatures across the wafer.
    Type: Grant
    Filed: October 21, 1997
    Date of Patent: April 27, 1999
    Assignee: LSI Logic Corporation
    Inventors: Sheldon Aronowitz, Nicholas Eib, Jon S. Owyang
  • Patent number: 5851859
    Abstract: The present invention is related to a method for manufacturing a thin film transistor which can improve the yield, characteristics and reliability of the thin film transistor by selectively forming a semiconductor layer on a desired portion using a of a substrate using a temperature difference of the surface of a substrate achieve by heating the substrate with a lamp. The method comprises the steps of forming a black matrix layer of metal on a portion of the whole surface of an insulating glass substrate, forming an insulating layer for protecting the substrate on the whole substrate including the black matrix layer, forming source/drain electrodes on the insulating layer over the black matrix, selectively forming a semiconductor layer on the insulating layer including the source/drain electrodes, forming a gate insulating layer and forming a gate electrode.
    Type: Grant
    Filed: March 7, 1997
    Date of Patent: December 22, 1998
    Assignee: Goldstar Co., Ltd.
    Inventor: Jeong Hyun Kim
  • Patent number: 5840592
    Abstract: A method of simultaneously improving the spectral response and dark current characteristics of an image gathering detector is disclosed. The method uses an excimer laser to redistribute and activate ion implanted dopant species in the backside of an image gathering device such as a backside-illuminated CCD. Alternately, the excimer laser is used to incorporate dopants from a gaseous ambient into the backside of the image gathering device and simultaneously redistribute and activate the dopants. The redistribution of the dopant is controlled by the laser pulses and provides for a peak dopant concentration at the back surface of the image gathering device which provides for improved spectral response and simultaneously improves dark current characteristics.
    Type: Grant
    Filed: July 5, 1994
    Date of Patent: November 24, 1998
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Stephen D. Russell, Douglas A. Sexton, Eugene P. Kelley, Ronald E. Reedy
  • Patent number: 5756364
    Abstract: It is intended to provide a technique of separately forming thin-film transistors disposed in a peripheral circuit area and those disposed in a pixel area in accordance with characteristics required therefor in a manufacturing process of semiconductor devices to constitute a liquid crystal display device. In an annealing step by laser light illumination, laser light is selectively applied to a semiconductor thin-film by partially masking it. For example, to illuminate the peripheral circuit area and the pixel area with laser light under different conditions in manufacture of an active matrix liquid crystal display device, laser light is applied at necessary illumination energy densities by using a mask. In this manner, a crystalline silicon film having a necessary degree of crystallinity in a selective manner can be obtained.
    Type: Grant
    Filed: November 22, 1995
    Date of Patent: May 26, 1998
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Koichiro Tanaka, Naoaki Yamaguchi
  • Patent number: 5739043
    Abstract: A method for producing a substrate for forming a polysilicon thin film by forming an amorphous silicon film of a thickness not more than 200 .ANG., irradiating excimer laser light onto the amorphous silicon film to crystallize silicon particles contained in the amorphous silicon film; and irradiating the amorphous silicon film with hydrogen radicals to etch the amorphous silicon film.
    Type: Grant
    Filed: February 12, 1996
    Date of Patent: April 14, 1998
    Assignee: Kanegafuchi Chemical Industry Co., Ltd.
    Inventor: Kenji Yamamoto
  • Patent number: 5736464
    Abstract: In order to improve a process and an apparatus for producing a functional structure of a semiconductor component, which comprises layers arranged on a base substrate and defining the entire functions of the semiconductor component, such that the functional structure of the semiconductor components can be produced as simply as possible and with as little susceptibility as possible with respect to the quality of the semiconductor components it is suggested that all the layers be produced without lithography and applied to the base substrate one after the other exclusively with physical layer application processes.
    Type: Grant
    Filed: May 25, 1995
    Date of Patent: April 7, 1998
    Assignee: Deutsche Forschungsanstalt fuer Luft-und Raumfahrt e.V.
    Inventor: Hans Opower
  • Patent number: 5712191
    Abstract: In producing a thin film transistor, after an amorphous silicon film is formed on a substrate, a nickel silicide layer is formed by spin coating with a solution (nickel acetate solution) containing nickel as the metal element which accelerates (promotes) the crystallization of silicon and by heat treating. The nickel silicide layer is selectively patterned to form island-like nickel silicide layer. The amorphous silicon film is patterned. A laser light is irradiated while moving the laser, so that crystal growth occurs from the region in which the nickel silicide layer is formed and a region equivalent to a single crystal (a monodomain region) is obtained.
    Type: Grant
    Filed: September 8, 1995
    Date of Patent: January 27, 1998
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Setsuo Nakajima, Shunpei Yamazaki, Naoto Kusumoto, Satoshi Teramoto
  • Patent number: 5593918
    Abstract: Various techniques for forming superconductive lines are described whereby superconductive lines can be formed by stamping, etching, polishing, or by rendering selected areas of a superconductive film (layer) non-superconductive. The superconductive material can be "perfected" (or optimized) after it is formed into lines (traces). In one embodiment, trenches are etched in a substrate, the trenches are filled with superconductive material, and any excess superconductive material overfilling the trenches is removed, such as by polishing. In another embodiment, superconductive lines are formed by rendering selected areas of a superconductive layer (i.e., areas other than the desired superconductive lines) non-superconductive by "damaging" the superconductive material by laser beam heating, or by ion implantation. Superconductive lines formed according to the invention can be used to protect semiconductor devices (e.g.
    Type: Grant
    Filed: April 22, 1994
    Date of Patent: January 14, 1997
    Assignee: LSI Logic Corporation
    Inventors: Michael D. Rostoker, Mark Schneider, Nicholas F. Pasch, Abraham Yee, William C. Schneider
  • Patent number: 5591668
    Abstract: A laser annealing method for a semiconductor thin film for irradiating the semiconductor thin film with a laser beam having a section whose outline includes a straight-line portion, so as to change the crystallinity of the semiconductor thin film is provided, wherein the semiconductor thin film is overlap-irradiated with the laser beam while the laser beam is shifted in a direction different from a direction along the straight-line portion. A thin film semiconductor device fabricated by use of the laser annealing method is also provided.
    Type: Grant
    Filed: March 13, 1995
    Date of Patent: January 7, 1997
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Shigeki Maegawa, Tetsuya Kawamura, Mamoru Furuta, Yutaka Miyata
  • Patent number: 5529951
    Abstract: A method of forming a polycrystalline silicon thin film improved in crystallinity and a channel of a transistor superior in electrical characteristics by the use of such a polycrystalline silicon thin film. An amorphous silicon layer of a thickness preferably of 30 nm to 50 nm is formed on a substrate. Next, substrate heating is performed to set the amorphous silicon layer to preferably 350.degree. C. to 500.degree. C., more preferably 350.degree. C. to 450.degree. C. Then, at least the amorphous silicon layer is irradiated with laser light of an excimer laser energy density of 100 mJ/cm.sup.2 to 500 mJ/cm.sup.2, preferably 280 mJ/cm.sup.2 to 330 mJ/cm.sup.2, and a pulse width of 80 ns to 200 ns, preferably 140 ns to 200 ns, so as to directly anneal the amorphous silicon layer and form a polycrystalline silicon thin film. The total energy of the laser used for the irradiation of excimer laser light is at least 5 J, preferably at least 10 J.
    Type: Grant
    Filed: November 1, 1994
    Date of Patent: June 25, 1996
    Assignee: Sony Corporation
    Inventors: Takashi Noguchi, Tohru Ogawa, Yuji Ikeda
  • Patent number: 5496768
    Abstract: In the first laser beam radiation, a laser beam having a predetermined energy density is scanned on each of predetermined unit irradiated regions at a scanning pitch smaller than the beam size, and in the second laser beam radiation, a laser beam having an energy density lower than that of the laser beam of the first radiation is scanned at a scanning pitch smaller than the beam size on each of unit irradiated regions different from those of the first laser beam radiation.
    Type: Grant
    Filed: November 23, 1994
    Date of Patent: March 5, 1996
    Assignee: Casio Computer Co., Ltd.
    Inventor: Toshio Kudo
  • Patent number: 5492861
    Abstract: In order to provide a process for applying structured layers of a functional structure of a semiconductor component, with which structured layers of a functional structure of a semiconductor component can be produced as simply as possible and with as little susceptibility as possible with respect to the quality of the semiconductor components, it is suggested that a material film be arranged above a surface region of a process substrate to be provided with the structured layer, that the material film be acted upon on its side remote from the process substrate by a focus of a laser beam located in a defined position corresponding to the structured layer to be produced and that with the laser beam in the region of the focus the material from the material film migrate to the surface region.
    Type: Grant
    Filed: August 26, 1993
    Date of Patent: February 20, 1996
    Assignee: Deutsche Forschungsanstalt fuer Luft-und Raumfahrt e.V.
    Inventor: Hans Opower
  • Patent number: 5455203
    Abstract: A method of adjusting a semiconductor pressure switch of the type having a silicon substrate having a pressure receiving diaphragm includes mounting and pressurizing the semiconductor pressure switch in a pressure chamber and measuring the pressure of the switch to determine if the pressure is above or below the predetermined pressure detection value. If the measured pressure is above the predetermined pressure detection value, the thickness of the diaphragm is adjusted by thinning the diaphragm to adjust the measured pressure to the predetermined pressure detection value. If the measured pressure is below the predetermined pressure detection value, the thickness of the diaphragm is adjusted by thickenning the diaphragm to adjust the measured pressure to the predetermined pressure detection value.
    Type: Grant
    Filed: February 11, 1993
    Date of Patent: October 3, 1995
    Assignee: Seiko Instruments Inc.
    Inventors: Osamu Koseki, Yoshifumi Yoshida
  • Patent number: 5387546
    Abstract: The present invention relates to a method for manufacturing a semiconductor device including a method for reforming an insulating film formed by a low temperature CVD method. It is an object of the present Invention to provide a method for manufacturing a semiconductor device capable of improving a film quality of an insulating film formed by a CVD method which is able to form a film at a low temperature and also capable of maintaining mass productivity, in which processing by irradiation with ultraviolet rays of the insulating film while heating the film after forming an insulating film (4) on a body to be formed by a chemical vapor deposition method is included.
    Type: Grant
    Filed: June 22, 1992
    Date of Patent: February 7, 1995
    Assignees: Canon Sales Co., Inc., Alcan-Tech Co., Ltd., Semiconductor Process Laboratory Co., Ltd.
    Inventors: Kazuo Maeda, Noboru Tokumasu, Yuko Nishimoto
  • Patent number: 5366926
    Abstract: A low temperature process for dehydrogenating amorphous silicon using lasers. Dehydrogenation occurs by irradiating one or more areas of a hydrogenated amorphous silicon layer with laser beam pulses at a relatively low energy density. After the multiple laser pulse irradiation at a relatively low energy density, the laser energy density is increased and multiple irradiation at a higher energy density is performed. If after the multiple irradiation at the higher energy density the amorphous silicon hydrogen content is still too high, dehydrogenation proceeds by multiple irradiations at a yet higher energy density. The irradiation at the various energy densities can result in the formation of polysilicon due to melting of the amorphous silicon layer. As irradiation may be selectively applied to the amorphous silicon, an integral amorphous silicon-polysilicon structure may be formed.
    Type: Grant
    Filed: June 7, 1993
    Date of Patent: November 22, 1994
    Assignee: Xerox Corporation
    Inventors: Ping Mei, James B. Boyce, Richard I. Johnson, Michael G. Hack, Rene A. Lujan
  • Patent number: 5333161
    Abstract: This invention relates to a method to selectively mitigate intergranular stress corrosion cracking (IGSCC) by rapid quench melting through the use of a pulsed laser. Such methods of the type, generally, mitigate reactor pipe cracking by rapidly melting the sensitized material to redissolve chromium carbide and then rapidly cooling the sensitized material such that corrosion cracking can be avoided.
    Type: Grant
    Filed: March 19, 1993
    Date of Patent: July 26, 1994
    Assignee: General Electric Company
    Inventors: Robert A. Thompson, Marshall G. Jones
  • Patent number: 5326709
    Abstract: A wafer testing process of a semiconductor device provided with a redundancy circuit. The process comprises a step of removing a passivation film above a pad and link portion, pre-laser testing, laser-repairing, and final quality marking using an off-line inking method. Therefore, fabrication-test processes are simplified to one step by adopting the off-line inking method, thereby achieving productivity improvement, quality enhancement, and reduction of throughput time.
    Type: Grant
    Filed: December 18, 1992
    Date of Patent: July 5, 1994
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hong-bae Moon, Bon-youl Ku, Gi-seung Song, Tae-wook Seo
  • Patent number: 5310446
    Abstract: A method for producing a semiconductor film comprising steps of: preparing a first substrate and a second substrate; superposing the first substrate on the second substrate to form an assembly of combined substrates; applying energy to the assembly of combined substrates to melt a portion within the assembly to form a molten portion therein; cooling the molten portion to crystallize the portion to form a single crystal structure therein; and separating the first substrate from the second substrate. The method makes it possible to control the crystal axis orientation of the recrystallized single crystal structure.
    Type: Grant
    Filed: July 13, 1992
    Date of Patent: May 10, 1994
    Assignee: Ricoh Company, Ltd.
    Inventors: Junichi Konishi, Kouichi Maari, Toshihiko Taneda, Akiko Kishimoto
  • Patent number: 5296405
    Abstract: An improved semiconductor processing is disclosed. In the manufacturing process, a semiconductor layer is formed and then undergoes photo annealing. A neutralizer is then introduced to the photoannealed semiconductor. The semiconductor thus formed demonstrates the SEL effect instead of the Staebler-Wronski effect.
    Type: Grant
    Filed: August 24, 1992
    Date of Patent: March 22, 1994
    Assignee: Semiconductor Energy Laboratory Co.., Ltd.
    Inventors: Shunpei Yamazaki, Kunio Suzuki, Susumu Nagayama, Takashi Inujima, Masayoshi Abe, Takeshi Fukada, Mikio Kinka, Ippei Kobayashi, Katsuhiko Shibata, Masato Susukida, Kaoru Koyanagi
  • Patent number: 5294567
    Abstract: The invention is directed to a method for rapidly forming a dense pattern of via holes in multilayer electronic circuits in which via holes in the dielectric layers are formed by drilling with an excimer laser under controlled operating conditions.
    Type: Grant
    Filed: October 8, 1993
    Date of Patent: March 15, 1994
    Assignee: E. I. Du Pont de Nemours and Company
    Inventors: Jay R. Dorfman, Richard R. Draudt, Thomas D. Lantzer, Arthur H. Mones, David L. Sutton
  • Patent number: 5281553
    Abstract: The state of conduction of an MOS transistor 11 is definitively controlled by a laser beam 21, by forming an electrical connection 22 between the gate 16 and the subjacent portion d of the source region 14 or drain region 15. The invention is applicable in particular to the correction (reconfiguration, redundancy) of integrated circuits and to the programming of integrated PROMs.
    Type: Grant
    Filed: February 22, 1991
    Date of Patent: January 25, 1994
    Assignee: Bull, S.A.
    Inventors: Alain Boudou, Marie-Francois Bonnal, Martine Rouillon-Martin
  • Patent number: 5254137
    Abstract: Disclosed is a method of producing a chip-type solid-electrolyte capacitor, in which the surface of a sheathing resin layer formed on an anode body is roughened by forming an irregularity thereon, and plated metal layers are formed on the surface thus roughened for an anode and cathode use. The metal layers are strongly adhered on the roughened surface. The surface-irregularity of the sheathing resin layer is produced by blasting hard particle material made of, for example, alumina or glass using a sandblast machine, or by irradiating a laser beam such as the YAG laser beam or the like.
    Type: Grant
    Filed: October 29, 1991
    Date of Patent: October 19, 1993
    Assignee: NEC Corporation
    Inventor: Toshiyuki Mitani
  • Patent number: 5231050
    Abstract: The conductor 15 to be connected to the doped region 12 of the substrate 11 has an edge 15a at which the laser beam 20 is aimed, regulated such as to definitively create a zone of low electrical resistance 19 in the dielectric layer 13 that separates the conductor from the doped region. The invention is particularly applicable to programming by laser of read only memories and defective integrated circuits with a view to correcting them.
    Type: Grant
    Filed: April 10, 1990
    Date of Patent: July 27, 1993
    Assignee: Bull, S.A.
    Inventors: Alain Boudou, Marie-Francoise Bonnal, Marine Rouillon-Martin
  • Patent number: 5171710
    Abstract: An improved semiconductor processing is disclosed. In the manufacturing process, a semiconductor layer is formed and then undergoes photo annealing. A neutralizer is then introduced to the photoannealed semiconductor. The semiconductor thus formed demonstrates the SEL effect instead of the Staebler-Wronski effect.
    Type: Grant
    Filed: May 9, 1990
    Date of Patent: December 15, 1992
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kunio Suzuki, Susumu Nagayama, Takashi Inujima, Masayoshi Abe, Takeshi Fukada, Mikio Kinka, Ippei Kobayashi, Katsuhiko Shibata, Masato Susukida, Kaoru Koyanagi
  • Patent number: 5147819
    Abstract: A method of applying an alloy layer of predetermined thickness on a semiconductor wafer to fill contact openings having a defined diameter, the method comprising the following steps:chemical vapor depositing (CVD) a layer of elemental metal atop the wafer to a thickness of from 5% to 35% of the defined contact diameter;sputtering a layer of an alloy atop the chemical vapor deposited layer of elemental metal to a thickness which results in the combination of the chemical vapor deposited and sputtered layers having substantially the predetermined overall layer thickness; andcombining and intermixing the sputtered alloy layer with the chemical vapor deposited elemental metal layer to form an overall homogenous alloy layer by applying energy to the sputtered alloy layer, the application of energy also filling contact openings and planarizing the homogenous layer.Preferably, the CVD layer has a thickness of from 10% to 20%, and the energy is applied by a scanning pulsed laser.
    Type: Grant
    Filed: February 21, 1991
    Date of Patent: September 15, 1992
    Assignee: Micron Technology, Inc.
    Inventors: Chang Yu, Trung T. Doan, Gurtej S. Sandhu
  • Patent number: 5145808
    Abstract: A method of crystallizing a semiconductor thin film moves a laser beam emitted by a pulse laser in a first direction to irradiate the semiconductor tin film with the laser beam for scanning. The laser beam is split into a plurality of secondary laser beams of a width smaller than the pitch of step feed, respectively having different energy densities forming a stepped energy density distribution decreasing from the middle toward the opposite ends thereof with respect to the direction of step feed. The energy density of the first secondary laser beam corresponding to the middle of the energy distribution is higher than a threshold energy density, i.e., the minimum energy density that will melt the semiconductor thin film to make the same amorphous, and lower than a roughening energy density, i.e.
    Type: Grant
    Filed: August 20, 1991
    Date of Patent: September 8, 1992
    Assignee: Sony Corporation
    Inventors: Toshiyuki Sameshima, Masaki Hara, Naoki Sano, Setsuo Usui
  • Patent number: 5137844
    Abstract: The electromagnetic radiation output from a solid-state radiation emitter is adjusted by covering at least part of the emission surface with an absorber material which absorbs the radiation emitted from the emitter, and directing a beam of radiation from outside the radiation emitter on to the absorber material so as to ablate at least part of the absorber material from the emission surface, or render at least part of the absorber material transmissive of the electromagnetic radiation from the emitter. The process is especially useful for equalizing the outputs from an array of emitters, such as a bar of light emitting diodes.
    Type: Grant
    Filed: April 5, 1991
    Date of Patent: August 11, 1992
    Assignee: Polaroid Corporation
    Inventor: Carl A. Chiulli
  • Patent number: 5127364
    Abstract: An apparatus for producing a tape superconductor of a compound superconductor type wherein the apparatus includes a first wire constructed of the superconducting compound material which is melted to form a bead. The bead is then wiped on a tape substrate to form a layer as the substrate is fed by the bead. Finally, the layer is cooled and a tape superconductor is formed.
    Type: Grant
    Filed: December 13, 1990
    Date of Patent: July 7, 1992
    Assignee: General Electric Company
    Inventors: Sudhir D. Savkar, Carl M. Penney
  • Patent number: 5102830
    Abstract: A process for preventing overprocessing of an (IC) wafer or the like in an area of laser overlap. The invention in general comprises a process in which the surface of an (IC) wafer is coated with a composition which forms a light reflective surface upon the application of laser energy. Laser energy is thus reflected away from the wafer in areas of multiple laser exposure. In a preferred embodiment of the invention an (IC) wafer is coated with a nitrogen deficient titanium nitride film, which reacts with oxygen in the laser process chamber, to form a highly reflective titanium oxide film.
    Type: Grant
    Filed: July 24, 1990
    Date of Patent: April 7, 1992
    Assignee: Micron Technology, Inc.
    Inventor: Gurtej S. Sandhu
  • Patent number: 5100834
    Abstract: A planarization method includes the steps of forming a second layer on a first layer which has an alignment mark having a heat sink structure, where the second layer is made of a metal, and irradiating a pulse energy beam on the entire exposed surface of the second layer to planarize the second layer. The heat generated in the second layer on the alignment mark is released via the first layer so that substantially no melting of the second layer occurs on the alignment mark.
    Type: Grant
    Filed: March 19, 1991
    Date of Patent: March 31, 1992
    Assignee: Fujitsu Limited
    Inventor: Ryoichi Mukai
  • Patent number: 5096850
    Abstract: A method including covering the area to be laser trimmed with a first insulative layer having a thickness sufficiently thin that a layer can trim the area through the first insulative layer. An etch stop is formed on the first insulative layer over the area to be trimmed and covered with a second insulative layer. A portion of the second insulative layer is etched to expose the etch stop and a portion of the etch stop is then removed to expose a portion of the first insulative layer and laser trimming is conducted through the exposed first insulative layer. The etch stop is part of a first level of interconnects made of the same material and simultaneously with the etch stop. The area to be trimmed is part of a second level of contacts that interconnect another second material.
    Type: Grant
    Filed: April 23, 1991
    Date of Patent: March 17, 1992
    Assignee: Harris Corporation
    Inventor: Maxwell W. Lippitt, III
  • Patent number: 5094977
    Abstract: A method of processing a semiconductor wafer comprises, a) chemical vapor depositing (CVD) a metal layer atop a semiconductor substrate; and b) impinging laser energy upon the CVD metal layer at an optical fluence of from 0.05 Joules/cm.sup.2 to 0.30 Joules/cm.sup.2 for a period of time sufficient to relieve mechanical stress associated with the CVD metal layer yet insufficient to melt the CVD metal layer. In accordance with another aspect of the invention, such treatment method could also be used to form a desired silicide layer in the same step.
    Type: Grant
    Filed: January 25, 1991
    Date of Patent: March 10, 1992
    Assignee: Micron Technology, Inc.
    Inventors: Chang Yu, Trung T. Doan, Gurtej S. Sandhu
  • Patent number: 5093279
    Abstract: A laser ablation damascene process for the planarizing of metal/polymer structures. More specifically, the process is especially adapted for the fabrication of both interlevel via metallization and circuitization layers in integrated circuit (IC) interconnects. Subsequent to the forming or etching of holes or depressions in a polymer insulating layer, a metal layer or film is deposited thereon for the purpose of fabricating vias or trenches for metallization and circulation layers in IC connects. Thereafter, the surface of the metal layer which has been deposited or superimposed on the polymer substrate through any suitable method known in the art is irradiated with at least one laser pulse which will cause the metal layer to melt and reflow and resultingly fill the vias and trenches etched in the polymer substrate while simultaneously ablating and removing the metal from the planarized surface of the substrate in the regions about the vias and trenches.
    Type: Grant
    Filed: February 1, 1991
    Date of Patent: March 3, 1992
    Assignee: International Business Machines Corporation
    Inventors: Joseph C. Andreshak, Robert J. Baseman
  • Patent number: 5082791
    Abstract: A solar cell fabrication procedure is described in which an excimer laser is used to cut a trench in a flat solar cell substrate so as to electrically isolate front and back regions of the substrate. The trench is cut around the perimeter of the cell. The advantage of using an excimer laser is that it will ablate a trench without diffusing conductive material deeper into the cell.
    Type: Grant
    Filed: August 18, 1989
    Date of Patent: January 21, 1992
    Assignee: Mobil Solar Energy Corporation
    Inventors: Ronald H. Micheels, Percy Valdivia, Jack I. Hanoka
  • Patent number: 5061655
    Abstract: A method of producing so-called SOI structures according to this invention includes the step of forming an opening for seeding after an insulating layer of predetermined thickness has been formed on a first monocrystal silicon layer. Further, a non-monocrystal layer, e.g., a polycrystal silicon layer is formed on the surface of the insulating layer. The surface of the polycrystal silicon layer is smoothed as by grinding. A reflection-preventive film is formed on the smoothed surface of the polycrystal silicon layer. The reflection-preventive film has a thin film region whose reflectance is substantially zero and a thick film region having a predetermined reflectance. During laser annealing, the reflection-preventive film produces a predetermined temperature distribution in the polycrystal silicon layer.
    Type: Grant
    Filed: February 11, 1991
    Date of Patent: October 29, 1991
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Takashi Ipposhi, Kozuyuki Sugahara
  • Patent number: 5057452
    Abstract: The invention relates to a method of manufacturing a semiconductor device in which a polycrystalline or amorphous silicon oxide layer 3, which is provided on a silicon oxide layer 2 on a monocrystalline silicon substrate 1 and which is in contact with the silicon substrate 1 via an opening 4 in the silicon layer 2, is recrystallized by means of a heat treatment in the presence of means for concentrating the heat at the opening 4. In a simple and inexpensive manner, these means consist of a second silicon oxide layer 5 and a second polycrystalline silicon layer 6, the second silicon oxide layer 5 having a thickness at the openings 4 which is smaller than that of the rest of the layer 5.
    Type: Grant
    Filed: February 5, 1991
    Date of Patent: October 15, 1991
    Assignee: U.S. Philips Corporation
    Inventors: Matthias J. J. Theunissen, Johanna M. L. Mulder, Jan Haisma, Wilhelmus P. M. Rutten
  • Patent number: 5045501
    Abstract: An integrated circuit structure and method of forming the same is described in which a plurality of common signal planes are provided for an integrated circuit formed on a layer of semiconductive material (30). The common planes consist of a single crystal semiconductive substrate (2) and at least one conductive layer (26, 66) between the substrate (2) and the semiconductive circuit layer (30), with insulative layers (24, 28, 68) separating the conductive layers (26, 66) from each other and from the substrate (2) and semiconductive layer (30). When one conductive layer (26) is used, a power supply signal (V+) is preferably applied to the substrate (2) and a ground reference to the conductive layer (26). Contacts are made between the integrated circuit and the desired common planes by metallized contacts (56, 60) formed in openings (54, 58) through the underlying material. Various circuit signals can also be introduced through additional conductive layers.
    Type: Grant
    Filed: August 15, 1988
    Date of Patent: September 3, 1991
    Assignee: Hughes Aircraft Company
    Inventor: Jan Grinberg
  • Patent number: 5026664
    Abstract: A semiconductor IC device having a substrate, a patterned conductor layer for interconnection of regions in the substrate and a passivation layer covering the device is provided with an additional conduction path of a pattern and/or part of the patterned conductor layer is removed for disconnection for the purpose of evaluation of the characteristics of the device. The additional conduction path is formed by forming a hole in the passivation layer to expose a part of the conductor layer, directing, in an atmosphere containing a metal compound gas, an ion beam onto the hole and onto a predetermined portion of the passivation layer on which the additional conduction path of a pattern is to be formed to thereby form a patterned film of the metal decomposed from the metal compound gas and forming an additional conductor on the patterned film.
    Type: Grant
    Filed: April 6, 1989
    Date of Patent: June 25, 1991
    Assignee: Hitachi, Ltd.
    Inventors: Mikio Hongo, Katsuro Mizukoshi, Shuzo Sano, Takashi Kamimura, Fumikazu Itoh, Akira Shimase, Satoshi Haraichi, Takahiko Takahashi
  • Patent number: 5024968
    Abstract: A method and apparatus for removing surface contaminants from the surface of a substrate by high-energy irradiation is provided. The invention enables removal of surface contaminants without altering of the substrate's underlying molecular structure. The source of high-energy irradiation may comprise a pulsed laser.
    Type: Grant
    Filed: July 8, 1988
    Date of Patent: June 18, 1991
    Inventor: Audrey C. Engelsberg
  • Patent number: 4968643
    Abstract: A conducting link is disposed in an insulating layer of a semiconductor device in combination with a plurality of wirings of the device which are electrically separated from each other. The conducting link is selectively activated to provide the wirings with a conducting path, and is activatable by melting metal contained in the wirings by irradiating a portion of the wirings in the vicinity of the link with a shot of a pulse of laser beam. The link comprises a through hole or a trench disposed in the insulating layer depending on the structural configuration of the device. The method of fabricating and activating the conductive link is provided.
    Type: Grant
    Filed: April 26, 1989
    Date of Patent: November 6, 1990
    Assignee: Fujitsu Limited
    Inventor: Ryoichi Mukai
  • Patent number: 4931353
    Abstract: In a multi-chip module, a structure for selectively connecting two conductors. A switchable connector (36) is disposed between a first and second portion (30,32) of a copper conductor (28). The switchable connector comprises an amorphous silicon layer (58), which extends between two spacer pads (56) that are electrically connected to the first and second portions of the copper conductor. A barrier layer (60) is formed atop the amorphous silicon, physically separating it from a reactive metal layer (62). The reactive metal layer is coated with an antireflective coating (64). Interaction of the reactive metal layer with the amorphous silicon layer is prevented by the barrier layer until the barrier layer is heated above 500.degree. C. A laser beam (66) is focused on opposite edges of the switchable connector, causing the barrier layer and reactive metal layer to diffuse into the amorphous silicon, forming electrically conductive silicides.
    Type: Grant
    Filed: November 22, 1989
    Date of Patent: June 5, 1990
    Assignee: The Boeing Company
    Inventor: Minas H. Tanielian
  • Patent number: 4924062
    Abstract: A method and apparatus for hardening discrete identical elements, connected to a supporting structure and regularly spaced, by which a laser beam is focused upon the elements as they travel along a path through a hollow sphere containing a mirror on its inside surface. The light reflected by the elements is reflected by the mirror to strike the opposite side of the elements. This process optimizes the radiant energy directed to the elements and produces quick, uniform, well-delineated hardening substantially without a hardness gradient.
    Type: Grant
    Filed: January 30, 1989
    Date of Patent: May 8, 1990
    Assignee: Graf & Cie AG
    Inventor: Erwin Zurcher
  • Patent number: 4895812
    Abstract: A layer of chemically compatible conductive material is applied to ferroelectric semiconductor material having a permanent polarization below its Curie temperature. The materials are heated to a temperature above the Curie temperature of the ferroelectric semiconductor material and allowed to cool. The result is a low resistance contact. The ferroelectric semiconductive material may be a layer on a non ferroelectric semiconductor material with a matching work function or matching dopant levels.
    Type: Grant
    Filed: December 14, 1988
    Date of Patent: January 23, 1990
    Assignee: GTE Laboratories Incorporated
    Inventors: Da Y. Wang, Daniel T. Kennedy, Burton W. MacAllister, Jr.
  • Patent number: 4847138
    Abstract: There is disclosed a method of producing a transition metal pattern on a glass or glass-ceramic substrate by selective exudation of a transition metal from a glass substrate containing the metal as an oxide. The selective exudation is effected by applying an intense, well-focused source of energy to a glass in a pattern corresponding to the desired metal pattern. This develops localized heating, and thereby causes corresponding localized metal exudation from the glass. The metal pattern may be rendered electroconductive, and may constitute a pattern of interconnecting lines for microcircuitry.
    Type: Grant
    Filed: October 7, 1987
    Date of Patent: July 11, 1989
    Assignee: Corning Glass Works
    Inventors: Elizabeth A. Boylan, Gerald D. Fong
  • Patent number: 4840922
    Abstract: A masking layer is formed on the light-emitting mirror surface of a semiconductor laser body. The masking layer is capable of blocking or cutting off light emitted from the semiconductor laser body and of being made optically transparent by exposure to the light emitted from the semiconductor laser body dependent on the amount of energy of the emitted light. When the light is emitted from the semiconductor laser body on which the masking layer is deposited, a small light-emitting hole is defined in the masking layer, the light-emitting hole having a desired diameter commensurate with the amount of energy of the emitted light which is applied to the masking layer.
    Type: Grant
    Filed: October 13, 1987
    Date of Patent: June 20, 1989
    Assignees: Ricoh Company, Ltd., Hiroshi Kobayashi, Haruhiko Machida
    Inventors: Hiroshi Kobayashi, Haruhiko Machida, Hideaki Ema, Jun Akedo, Makoto Harigaya, Yasushi Ide
  • Patent number: 4835704
    Abstract: An adaptive method and system are disclosed for providing high density interconnections of very large scale integrated circuits on a substrate. The procedure is performed in four basic steps: first an artwork representation for the interconnections of the integrated circuits is generated. This artwork representation is stored in a computer data base and assumes the integrated circuits to be at predetermined ideal locations and positions on the substrate. Second, using imaging, the actual positions of each integrated circuit on the substrate are determined. The actual positions of the integrated circuits are compared with their ideal positions to compute an offset and rotation for each integrated circuit on the substrate. Third, the computed offsets and rotations are then used to modify the artwork representation stored in the data base to account for the actual locations and positions of the integrated circuits on the substrate.
    Type: Grant
    Filed: December 29, 1986
    Date of Patent: May 30, 1989
    Assignee: General Electric Company
    Inventors: Charles W. Eichelberger, Robert J. Wojnarowski, Kenneth B. Welles, II
  • Patent number: 4826785
    Abstract: A metallic interconnect includes a fuse portion that is readily vaporized upon exposure to the radiant energy of a laser. A layer of optically absorptive material is formed on top of an aluminum based metallic interconnect and together they are formed by a photolithographic and etch technique into a fuse portion. A low energy laser having a Gaussian energy distribution focused on the absorptive layer produces heat in the absorptive layer. The heat is transferred to the underlying aluminum based interconnect. The concentration of energy made possible by the absorptive layer allows the low energy laser to blow the fuse thereby producing an electrical open in the interconnect without damaging surrounding silicon substrate and/or polysilicon structures below or nearby the metal fuse.
    Type: Grant
    Filed: January 27, 1987
    Date of Patent: May 2, 1989
    Assignee: INMOS Corporation
    Inventors: Paul J. McClure, Robert E. Jones, Jr.
  • Patent number: 4822751
    Abstract: A thin film semiconductor device is formed by preparing a substrate, forming a pattern of metal thin film on the substrate, forming an insulating layer on the metal thin film, and forming a pattern of a semiconductor thin film active layer, which is self-aligned to the pattern of the metal thin film, by laser CVD.
    Type: Grant
    Filed: March 31, 1987
    Date of Patent: April 18, 1989
    Assignee: Mitsubishi Denki Kabushi Kaisha
    Inventors: Akira Ishizu, Tadashi Nishimura, Yasuo Inoue
  • Patent number: 4822752
    Abstract: Disclosed herein is a process for producing a single crystal layer of a semiconductor device, which comprises the steps of providing an oxide insulator layer separated by an opening part for seeding, on a major surface of a single crystal semiconductor substrate of the cubic system, providing a polycrystalline or amorphous semiconductor layer on the entire surface of the insulator layer inclusive of the opening part, then providing a protective layer comprising at least a reflective or anti-reflection film comprising strips of a predetermined width, in a predetermined direction relative to the opening part and at a predetermined interval, the protective layer capable of controlling the temperature distributions in the semiconductor layer at the parts corresponding to the stripes or the parts not corresponding to the stripes, thereby completing a base for producing a semiconductor device, thereafter the surface of the base is irradiated with an energy beam through the striped reflective or anti-reflection film
    Type: Grant
    Filed: March 6, 1987
    Date of Patent: April 18, 1989
    Assignee: Agency of Industrial Science and Technology
    Inventors: Kazuyuki Sugahara, Tadashi Nishimura, Shigeru Kusunoki, Yasuo Inoue