Check Back Patents (Class 178/69L)
  • High bandwidth self-timed data clocking scheme for memory bus implementation
    Patent number: 5550533
    Abstract: A clocking scheme for transferring data between electronic devices. The clocking scheme includes sending a data request signal from a first device to a second device during a first system clocking period. The second device then sends the requested data and a corresponding data validation signal to the first device. The data validation signal latches the data into the second device. The data is latched by the validation signal in a time period that is typically shorter than the clocking period of the system clock.
    Type: Grant
    Filed: November 14, 1994
    Date of Patent: August 27, 1996
    Assignee: Intel Corporation
    Inventor: Stephen S. Pawlowski