Abstract: Systems, devices, and methods for micro-electro-mechanical system (MEMS) tunable capacitors can include a fixed actuation electrode attached to a substrate, a fixed capacitive electrode attached to the substrate, and a movable component positioned above the substrate and movable with respect to the fixed actuation electrode and the fixed capacitive electrode. The movable component can include a movable actuation electrode positioned above the fixed actuation electrode and a movable capacitive electrode positioned above the fixed capacitive electrode. At least a portion of the movable capacitive electrode can be spaced apart from the fixed capacitive electrode by a first gap, and the movable actuation electrode can be spaced apart from the fixed actuation electrode by a second gap that is larger than the first gap.

Abstract: A method for making a capacitive touch sensitive housing, comprises: forming a non-patterned active metal layer on a housing wall; patterning the non-patterned active metal layer on the housing wall by laser ablation such that the non-patterned active metal layer is formed into a patterned active metal layer including a plurality of plating portions separated from each other, and a plurality of non-plating portions separated from the plating portions; and forming a metal layer on the patterned active metal layer such that the metal layer has first portions formed on the plating portions of the patterned active metal layer, and second portions formed on the non-plating portions of the patterned active metal layer.

Abstract: An electrode structure is provided. The electrode structure comprises a plurality of first conductive cells and second conductive cells separated from each other and disposed on a substrate; a plurality of first conductive lines connecting adjacent said first conductive cells and a plurality of second conductive lines connecting adjacent said second conductive cells; wherein each said second conductive line comprises a conducting element and a pair of second conductive branches disposed at two sides of said conducting elements and connecting said conducting element to adjacent said second conductive cells; said first conductive lines and said second conductive lines are insulated and intersected. The method of forming an electrode structure is also provided.

Abstract: A microporous carbon matrix material composition for use in supercapacitor electrodes may be produced by depositing carbon on a sacrificial zeolite template via one of several methods (e.g., hydrothermal or solvo-thermal deposition, sub-atmospheric vapor phase deposition, or high-pressure infiltration of hydrocarbon vapors). The deposition produces a carbon-coated zeolite intermediary. A surface layer of carbon formed on the carbon-coated zeolite intermediary may then be refined and the refined carbon-coated zeolite intermediary may be etched to produce a microporous carbon matrix having a substantially uniform structure and substantially aligned pores. In some embodiments, the carbon-coated zeolite intermediary may be annealed after deposition.

Abstract: A capacitor forming method includes forming an electrically conductive support material over a substrate, forming an opening through at least the support material to the substrate, and, after forming the opening, forming a capacitor structure contacting the substrate and the support material in the opening. The support material contains at least 25 at % carbon. Another capacitor forming method includes forming a support material over a substrate, forming an opening through at least the support material to the substrate, and, after forming the opening, forming a capacitor structure contacting the substrate and the support material in the opening. The support material contains at least 20 at % carbon. The support material has a thickness and the opening has an aspect ratio 20:1 or greater within the thickness of the support material.

Abstract: The present invention relates to a thin film sensor, capacitive touch panel having the sensor and preparation method thereof and terminal product. The thin film sensor of the present invention has only one optically conductive substrate. Specifically, only one optically transparent substrate is used, a sensing electrode layer and a driving electrode layer are coated on the upper and lower surfaces of the substrate, respectively, which helps to reduce the thickness of the thin film sensor on one hand, thus contributes to the development of light and thin of a touch panel and touch electronics; on the other hand, the material selection and the preparation process are simple, the selection of two substrates is not necessary to prepare two optically conductive thin film.

Abstract: The disclosure concerns a method for etching a PVD deposited barium strontium titanate layer, wherein a non-ionic surfactant at a concentration between 0.1 and 1 percent is added to an acid etching solution.

Abstract: In one embodiment of the invention, a method of forming an energy storage device is described in which a porous structure of an electrically conductive substrate is measured in-situ while being electrochemically etched in an electrochemical etching bath until a predetermined value is obtained, at which point the electrically conductive substrate may be removed from the electrochemical etching bath. In another embodiment, a method of forming an energy storage device is described in which an electrically conductive porous structure is measured to determine the energy storage capacity of the electrically conductive porous structure. The energy storage capacity of the electrically conductive porous structure is then reduced until a predetermined energy storage capacity value is obtained.

Abstract: Nano-carbon material is described that combines the common and unique properties of spherical fullerenes, carbon nanotubes and graphene carbon allotropes to create an architecture that has unique mechanical and electrical properties. The combined tensile strength of graphene with the compressive strength of fullerenes attached to nanotubes creates a high strength material. By attaching fullerenes to nanotubes, the surface area of the material is greatly enhanced beyond the high surface area normally associated with vertically aligned nanotube arrays. Fabrication can be performed via several complementary methods including catalyst deposition, hydrocarbon chemical vapor deposition, and surface functionalization. The fabrication of the NTC is based on its sub-composites: graphene-nanotubes and nanotubes-fullerenes and their respective fabrication processes.

Abstract: In general, in one aspect, a graphene film is used as a protective layer for current collectors in electrochemical energy conversion and storage devices. The graphene film inhibits passivation or corrosion of the underlying metals of the current collectors without adding additional weight or volume to the devices. The graphene film is highly conductive so the coated current collectors maintain conductivity as high as that of underlying metals. The protective nature of the graphene film enables less corrosion resistant, less costly and/or lighter weight metals to be utilized as current collectors. The graphene film may be formed directly on Cu or Ni current collectors using chemical vapor deposition (CVD) or may be transferred to other types of current collectors after formation. The graphene film coated current collectors may be utilized in batteries, super capacitors, dye-sensitized solar cells, and fuel and electrolytic cells.

Abstract: The invention relates to a method for manufacturing a high performance multi layer ceramic capacitor, comprising the steps of: a) providing a substrate having a first edge and a second edge arranged opposite to the first edge, b) depositing a bottom electrode layer onto the substrate using a thick-film and/or thin-film deposition method such that the electrode layer extends all the way from the first edge towards the second edge of the substrate such that a trench free of the bottom electrode layer is provided adjacent in between the deposited bottom electrode layer and the second edge of the substrate, d) depositing a high-k dielectric ceramic layer onto the electrode layer using a thick-film and/or thin-film deposition method such that the high-k dielectric ceramic layer extends all the way to the first edge and to the second edge of the substrate, f) depositing a low-k dielectric layer comprising silicon nitride, silicon dioxide and/or aluminum oxide onto the high-k dielectric ceramic layer using a thin-fi

Abstract: A method of forming a capacitor structure, which comprises: applying a silicon etching liquid which contains an alkali compound and a hydroxylamine compound in combination, with the pH adjusted to 11 or more, to a polycrystalline silicon film or an amorphous silicon film, removing a part or all of the polycrystalline silicon film or amorphous silicon film, and forming concave and convex shapes that constitute a capacitor.

Abstract: An electronic device having a variable capacitance element, includes a support substrate providing physical support, a pair of anchors formed on the support substrate, and having support portions in a direction perpendicular to a surface of the substrate, a movable electrode supported by the support portions of the pair of anchors, having opposing first and second side surfaces constituting electrode surfaces, and at least partially capable of elastic deformation, a first fixed electrode supported above the support substrate, and having a first electrode surface opposing to the first side surface of the movable electrode, and a second fixed electrode supported above the support substrate, and having a second electrode surface opposing to the second side surface of the movable electrode.

Abstract: An integrated MIMO antenna system is described wherein multiple antennas are fabricated on a single substrate. Antenna spacing and alignment is enhanced and controlled to a finer degree than with conventional discrete antenna fabrication techniques. Rotation of one or multiple antennas in relation to the other antennas in the system can be performed to within the accuracy of current photo-etching techniques. Metalized traces can be designed and etched on the single substrate and positioned between antenna elements to enhance inter-element isolation. The integrated MIMO antenna system can be fabricated on flexible printed circuit (FPC) material, or can be fabricated on rigid metallized substrate such as common FR4 materials. Portions of one or multiple antenna elements can be photo-etched on opposite sides of the substrate to provide an additional degree of freedom in terms of antenna placement, spacing, and rotation angle.

Abstract: A thin-film device system includes a substrate and a plurality of pillars. The plurality of pillars project from a surface of the substrate. Each of the plurality of pillars have a perimeter that includes at least four protrusions that define at least four recessed regions between the at least four protrusions. Each of the at least four recessed regions of each of the plurality of pillars receives one protrusion from an adjacent one of the plurality of pillars. A thin-film device is fabricated over the plurality of pillars.

Abstract: A method of manufacturing a pattern structure, the method includes sequentially forming a mold layer and a mask layer on a substrate, patterning the mask layer to form a mask having a plurality of first and second holes located at vertices of hexagons that form a honeycomb structure, forming filling layer patterns in the first and second holes, removing the mask, forming a spacer on sidewalls of the filling layer patterns and the spacer has a plurality of third holes at centers of the hexagons, removing the filling layer patterns to form an etching mask including the spacer, and etching the mold layer using the etching mask to form the pattern structure having a plurality of openings located at the vertices and the centers of the hexagons.

Abstract: A high K dielectric such as PZT, PLZT, and/or BST on a metal-containing conductive layer such as iridium is patterned using a fluorine-free, chlorine-based etchant. Despite the lower etch rate of chlorine-based etchants, the undercut at the dielectric-metal interface associated with fluorine-based etching of the high K dielectric material is avoided, and the likelihood of delamination by the dielectric is reduced. For an integrated circuit capacitive structure, an overlying metal layer is patterned with the high K dielectric using a single etch step.

Abstract: A capacitor forming method includes forming an electrically conductive support material over a substrate, forming an opening through at least the support material to the substrate, and, after forming the opening, forming a capacitor structure contacting the substrate and the support material in the opening. The support material contains at least 25 at % carbon. Another capacitor forming method includes forming a support material over a substrate, forming an opening through at least the support material to the substrate, and, after forming the opening, forming a capacitor structure contacting the substrate and the support material in the opening. The support material contains at least 20 at % carbon. The support material has a thickness and the opening has an aspect ratio 20:1 or greater within the thickness of the support material.

Abstract: A thin film capacitor includes a metal foil, dielectric layers and internal electrode layers alternately disposed on the metal foil, and a top electrode layer on the topmost layer among the two or more dielectric layers. These layers have peripheries that define an outer profile flaring toward the metal foil as viewed from the stacking direction of the thin film capacitor, and at least one dielectric layer of two or more dielectric layers satisfies a relationship B>A>0 wherein A is a gap of the periphery of the internal electrode layer directly below the dielectric layer protruding from the periphery of the dielectric layer, and B is a gap of the periphery of the dielectric layer protruding from the periphery of the internal electrode layer or the top electrode layer directly above the dielectric layer. The thin film capacitor has a structure free from short-circuiting and reducing debris of broken dielectric material.

Abstract: A method for producing a thin film laminated capacitor that makes it possible to reduce the number of operations for etching its electrode layers and its dielectric layers. On a substrate, a capacitor part is formed wherein n electrode layers and (n?1) dielectric layers are alternately laminated onto each other, wherein n is 4 or more. The capacitor part is etched from the same side k times. In any ith etching operation, through holes are formed in an amount corresponding to respective ai layers of the electrode layers and the dielectric layers. At least one of ai's is set to 2 or more, and k is made smaller than n?1, thereby making it possible to make the 2nd to nth layers of the electrode layers from the etching starting side exposed at the bottom surfaces of the through holes.

Abstract: The present invention relates to a capacitive touch panel and a method for manufacturing the same, in which the material having lower resistance than that of ITO is filled in the intaglio formed on the resin layer, which is patterned to form the embedded sensing electrode and the sensing electrodes and the wiring electrodes are formed at the same time by using the same resistance material; in which the capacitive touch panel includes a first sensing layer formed with a plurality of first direction sensing electrodes, which are patterned and a plurality of first wiring electrodes; and a second sensing layer formed with a plurality of second direction sensing electrodes, which are patterned and a plurality of second wiring electrodes; in which the first sensing layer and the second sensing layer are bonded in the mutual vertical direction.

Abstract: A method for producing a ceramic material is disclosed. A ceramic raw material mixture is produced by comminuting and mixing starting materials containing Pb, Zr, Ti, Nd and oxygen. Nickel or an nickel compound is introduced. The raw material mixture is calcined and a ceramic is sintered.

Abstract: A Coriolis-based bulk acoustic wave gyroscope includes a center-supported resonating element with capacitively-coupled drive, sense, and control electrodes. The resonating element has a first substantially solid or perforated region which is connected to the center-support by a second region characterized by a plurality of spokes or beams. When operating in a resonance state, the first region undergoes a bulk acoustic mode of vibration while the second region undergoes a flexural mode of vibration. Energy losses associated with the flexural mode of vibration reduce the overall quality factor (Q) at high resonance frequencies creating a large bandwidth and a fast response time without needing vacuum.

Abstract: A process for forming a laminate with capacitance and the laminate formed thereby. The process includes the steps of providing a substrate and laminating a conductive foil on the substrate wherein the foil has a dielectric. A conductive layer is formed on the dielectric. The conductive foil is treated to electrically isolate a region of conductive foil containing the conductive layer from additional conductive foil. A cathodic conductive couple is made between the conductive layer and a cathode trace and an anodic conductive couple is made between the conductive foil and an anode trace.

Abstract: A method of etching a foil for use in an electrolytic capacitor utilizes a nanoimprinted optic to control the etch pattern. The optic is formed by creating a self-assembled monolayer (SAM) of hemispheres onto the surface of an optical quartz substrate. A laser is directed onto the optic while the foil underlies the optic, and the concentrated light source is used to effectively image an array of submicron spots. The resulting spots allow for controlled initiation of etch tunnels during a subsequent electrochemical etch of the foil, with the purpose of ultimately increasing foil capacitance through the increased surface area.

Abstract: A method of manufacturing a capacitor-embedded printed circuit board, the method including providing a substrate on which a first metal layer, a dielectric layer and an adhesive resin layer are stacked on the order thereof; etching a part of the first metal layer to form a first electrode and a first circuit pattern; compressing a surface of the substrate, on which the first electrode is formed, onto a core board by interposing an insulation resin layer; forming a second electrode and a second circuit pattern on the adhesive resin layer; stacking an insulation board on the substrate such that the second electrode and the second circuit pattern are covered; and forming a third circuit pattern on the insulation board.

Abstract: A method for fabricating a capacitor includes: forming a first mold layer having a first through hole on a semiconductor substrate; forming a hole blocking layer filling and blocking an entrance of the first through hole; forming a second mold layer on the hole blocking layer and the first mold layer; forming a second through hole passing through the second mold layer and aligned with the first through hole; selectively removing the hole blocking layer exposed to the second through hole; forming a storage node along a profile of the first and second through holes; and selectively removing a portion of the first and second mold layers.

Abstract: A method of semiconductor fabrication including an etching process is provided. The method includes providing a substrate and forming a target layer on the substrate. An etchant layer is formed on the target layer. The etchant layer reacts with the target layer and etches a portion of the target layer. In an embodiment, an atomic layer of the target layer is etched. The etchant layer is then removed from the substrate. The process may be iterated any number of times to remove a desired amount of the target layer. In an embodiment, the method provides for decreased lateral etching. The etchant layer may provide for improved control in forming patterns in thin target layers such as, capping layers or high-k dielectric layers of a gate structure.

Abstract: A method of forming a capacitor structure and manufacturing a semiconductor device, the method of forming a capacitor structure including sequentially forming a first mold layer, a supporting layer, a second mold layer, an anti-bowing layer, and a third mold layer on a substrate having a conductive region thereon; partially removing the third mold layer, the anti-bowing layer, the second mold layer, the supporting layer, and the first mold layer to form a first opening exposing the conductive region; forming a lower electrode on a sidewall and bottom of the first opening, the lower electrode being electrically connected to the conductive region; further removing the third mold layer, the anti-bowing layer, and the second mold layer; partially removing the supporting layer to form a supporting layer pattern; removing the first mold layer; and sequentially forming a dielectric layer and upper electrode on the lower electrode and the supporting layer pattern.

Abstract: A self-aligned fabrication process for three-dimensional non-volatile memory is disclosed. A double etch process forms conductors at a given level in self-alignment with memory pillars both underlying and overlying the conductors. Forming the conductors in this manner can include etching a first conductor layer using a first repeating pattern in a given direction to form a first portion of the conductors. Etching with the first pattern also defines two opposing sidewalls of an underlying pillar structure, thereby self-aligning the conductors with the pillars. After etching, a second conductor layer is deposited followed by a semiconductor layer stack. Etching with a second pattern that repeats in the same direction as the first pattern is performed, thereby forming a second portion of the conductors that is self-aligned with overlying layer stack lines. These layer stack lines are then etched orthogonally to define a second set of pillars overlying the conductors.

Abstract: A method for fabricating a cylinder type capacitor includes forming connection contacts passing through a lower layer over a semiconductor substrate; forming a mold layer covering the connection contacts; forming a first floated pinning layer with a stress in a first direction over the mold layer; forming a second floated pinning layer for stress relief with a stress in a second direction over the first floated pinning layer, said second direction being opposite to the first direction; forming opening holes passing through the first and second floated pinning layers and the mold layer and exposing the connection contacts; forming storage nodes following a profile of the opening holes; removing portions of the first and second floated pinning layers to form a floated pinning layer pattern, the floated pinning layer pattern exposing a portion of the mold layer and contacting upper tips of the storage nodes; exposing outer walls of the storage nodes by selectively removing the exposed mold layer; and forming a d

Abstract: A thin energy storage device having high capacity is obtained. An energy storage device having high output is obtained. A current collector and an active material layer are formed in the same manufacturing step. The number of manufacturing steps of an energy storage device is reduced. The manufacturing cost of an energy storage device is suppressed. One embodiment of the present invention relates to an electric double layer capacitor which includes a pair of electrodes including a porous metal material, and an electrolyte provided between the pair of electrodes; or a lithium ion capacitor which includes a positive electrode that is a porous metal body functioning as a positive electrode current collector and a positive electrode active material layer, a negative electrode including a negative electrode current collector and a negative electrode active material layer, and an electrolyte provided between the positive electrode and the negative electrode.

Abstract: Disclosed is a porous polyimide membrane of a three-layer structure having two surface layers (a) and (b) and a macrovoid layer interposed between the surface layers (a) and (b), wherein the macrovoid layer has a partition wall joined to the surface layers (a) and (b) and plural macrovoids surrounded by the partition wall and the surface layers (a) and (b), with an average void diameter in a membrane plane direction of from 10 to 500 ?m; each of the partition wall of the macrovoid layer and the surface layers (a) and (b) has a thickness of from 0.1 to 50 ?m and has plural pores having an average pore diameter of from 0.01 to 5 ?m, the pores being communicated with each other and also communicated with the macrovoids; and the membrane has a total membrane thickness of from 5 to 500 ?m and a porosity of from 70 to 95%.

Abstract: A thin-film device system includes a substrate and a plurality of pillars. The plurality of pillars project from a surface of the substrate. Each of the plurality of pillars have a perimeter that includes at least four protrusions that define at least four recessed regions between the at least four protrusions. Each of the at least four recessed regions of each of the plurality of pillars receives one protrusion from an adjacent one of the plurality of pillars. A thin-film device is fabricated over the plurality of pillars.

Abstract: A fluid dispersion obtained by mixing oxide particles and water is sprayed to a raw aluminum foil from a direction opposite to a travelling direction of the raw aluminum foil while the raw aluminum foil is allowed to travel. In this way, a roll-pressed mark of the raw aluminum foil is eliminated, and thus aluminum foil for aluminum electrolytic capacitor electrode is produced. Pyramidal-shaped recesses each having an acute angle tip are present all over a surface of the aluminum foil.

Abstract: A liner removal process is described, wherein an excess portion of a conformal liner formed in a trench is substantially removed while reducing or minimizing damage to a bulk fill material in the trench.

Abstract: A torsional MEMS device is disclosed. The torsional MEMS device includes a support structure, a platform, and at least two hinges, which connects the platform to the support structure. The platform has an active area and a non-active area. A plurality of sacrificial elements is disposed in the non-active area. If the resonant frequency of the torsional MEMS device is less than a predetermined standard resonant frequency of the torsional MEMS device, at least one sacrificial element is removed to reduce the total mass of the torsional MEMS device, and so as to increase the resonant frequency of the torsional MEMS device.

Abstract: A fabrication method of a projective-capacitive touch panel is provided. The method includes steps of: providing a substrate; forming a metal trace layer on the substrate with a first exposing/developing process and a etching/stripping process sequentially; forming a first pattern layer on the metal trace layer with a second exposing/developing process, a first filming process and a first stripping process sequentially; forming a insulation layer on the first pattern layer; and forming a second pattern layer on the insulation layer with a third exposing/developing process, a second filming process and a second stripping process sequentially.

Abstract: A method of etching polysilicon includes exposing a substrate comprising polysilicon to a solution comprising water, HF, and at least one of a conductive metal nitride, Pt, and Au under conditions effective to etch polysilicon from the substrate. In one embodiment, a substrate first region comprising polysilicon and a substrate second region comprising at least one of a conductive metal nitride, Pt, and Au is exposed to a solution comprising water and HF. The solution is devoid of any detectable conductive metal nitride, Pt, and Au prior to the exposing. At least some of the at least one are etched into the solution upon the exposing. Then, polysilicon is etched from the first region at a faster rate than any etch rate of the first region polysilicon prior to the etching of the at least some of the conductive metal nitride, Pt, and Au.

Abstract: Techniques for incorporating nanotechnology into decoupling capacitor designs are provided. In one aspect, a decoupling capacitor is provided. The decoupling capacitor comprises a first electrode; an intermediate layer adjacent to the first electrode having a plurality of nanochannels therein; a conformal dielectric layer formed over the intermediate layer and lining the nanochannels; and a second electrode at least a portion of which is formed from an array of nanopillars that fill the nanochannels in the intermediate layer. Methods for fabricating the decoupling capacitor are also provided, as are semiconductor devices incorporating the decoupling capacitor design.

Abstract: A high density capacitor and low density capacitor simultaneously formed on a single wafer and a method of manufacture is provided. The method includes depositing a bottom plate on a dielectric material; depositing a low-k dielectric on the bottom plate; depositing a high-k dielectric on the low-k dielectric and the bottom plate; depositing a top plate on the high-k dielectric; and etching a portion of the bottom plate and the high-k dielectric to form a first metal-insulator-metal (MIM) capacitor having a dielectric stack with a first thickness and a second MIM capacitor having a dielectric stack with a second thickness different than the first thickness.

Abstract: A low capacitance density, high voltage MIM capacitor and the high density MIM capacitor and a method of manufacture are provided. The method includes depositing a plurality of plates and a plurality of dielectric layers interleaved with one another. The method further includes etching a portion of an uppermost plate of the plurality of plates while protecting other portions of the uppermost plate. The protected other portions of the uppermost plate forms a top plate of a first metal-insulator-metal (MIM) capacitor and the etching exposes a top plate of a second MIM capacitor.

Abstract: In certain embodiments, a MEMS actuator is provided comprising a frame and a movable structure coupled to the frame. A vertical comb drive is provided between the frame and the movable structure to actuate the movable structure.

Abstract: A MEMS device of an aspect of the present invention including a MEMS element includes a first lower electrode provided on a substrate, a first insulator which is provided on the upper surface of the first lower electrode, and has a first thickness, and a movable first upper electrode supported by an anchor in midair above the first lower electrode, and a capacitance element includes a second lower electrode provided on the substrate, a second insulator which is provided on the upper surface of the second lower electrode, and has a second thickness, and a second upper electrode provided on the second insulator, wherein the second thickness is less than the first thickness.

Abstract: A method for fabricating a capacitor includes forming a first storage node (SN) oxide layer over a substrate, forming a second SN oxide layer over the first SN oxide layer, forming a mask pattern over the second SN oxide layer, dry-etching the first and the second SN oxide layers using the mask pattern as an etch barrier to form a capacitor region, and wet-etching a resultant structure including the capacitor region to enlarge a bottom width of the capacitor region, thereby forming a final capacitor region having the enlarged bottom width, wherein the first SN oxide layer comprises one portion of high impurity concentration and the other portion of low impurity concentration, the one portion corresponding to a region where the final capacitor region is to be formed.

Abstract: Methods for fabricating a capacitor are provided. In the methods, a dielectric may be formed on a metal (e.g. nickel) substrate, and a copper electrode is formed thereon, followed by the thinning of the metal substrate from its non-coated face, and subsequently forming a copper electrode on the thinned, non-coated face of the substrate.

Abstract: A method of forming a plurality of capacitors includes forming a plurality of individual capacitor electrodes using two masking steps. An earlier of the two masking steps is used to form an array of first openings over a plurality of storage node contacts. A later of the two masking steps is used to form an array of second openings received partially over and partially offset from the array of first openings. Overlapping portions of the first and second openings are received over the storage node contacts. After both of the two masking steps, conductive material of the individual capacitor electrodes is deposited into the overlapping portions of each of the first and second openings. The individual capacitor electrodes are incorporated into a plurality of capacitors. Other aspects and implementations are contemplated.

Abstract: A thin film capacitor includes a metal foil, dielectric layers and internal electrode layers alternately disposed on the metal foil, and a top electrode layer on the topmost layer among the two or more dielectric layers. These layers have peripheries that define an outer profile flaring toward the metal foil as viewed from the stacking direction of the thin film capacitor, and at least one dielectric layer of two or more dielectric layers satisfies a relationship B>A>0 wherein A is a gap of the periphery of the internal electrode layer directly below the dielectric layer protruding from the periphery of the dielectric layer, and B is a gap of the periphery of the dielectric layer protruding from the periphery of the internal electrode layer or the top electrode layer directly above the dielectric layer. The thin film capacitor has a structure free from short-circuiting and reducing debris of broken dielectric material.

Abstract: A method for manufacturing an LC circuit, including forming a first conductive layer pattern serving as a lower electrode of a capacitor on a first interlayer insulating layer, forming a dielectric layer pattern storing electric charges on the first conductive layer pattern, forming a second conductive layer pattern serving as an upper electrode of the capacitor on the dielectric layer pattern, forming a second interlayer insulating layer on the second conductive layer pattern, forming a contact via exposing one of the first or second conductive layer pattern in the second interlayer insulating layer, and filling the contact via with a contact plug, and forming a third conductive layer pattern on the second interlayer insulating layer having the contact plug, wherein the third conductive layer pattern is electrically connected to the contact plug, and is etched in a metal interconnection type layer and functions as an inductor.

Abstract: A process for producing an aluminum electrode foil for a capacitor, which includes a first step of preparing an emulsion from a mixture including a first phase of a liquid resin or a resin solution obtained by dissolving a resin in a solvent, a second phase of a liquid that is incompatible with the first phase, and an emulsifier; a second step of coating the emulsion on a surface of an aluminum foil; a third step of removing the second phase to form a resin film having a plurality of pores on its surface; a fourth step of etching the aluminum foil having the resin film formed thereon; and a fifth step of removing the resin film after etching. The production process can form high-density etching pits with high accuracy.