Abstract: A tensioning system of traction tracks of a machinery by means of a hydraulic cylinder applying a tensioning force on at least one of the wheels on which the track is wound according to a closed chain configuration in which the hydraulic cylinder is fed with different pressures according to the traction direction, in a first traction direction the feeding pressure of the tensioning hydraulic cylinder being a first pressure approximately corresponding to the pressure which is generated by a pump which is present on a closed circuit feeding the traction devices, in a second traction direction the feeding pressure of the tensioning hydraulic cylinder being a second pressure corresponding to the pressure of the closed circuit up to a predetermined upper limit value.

Abstract: It is an object of the present invention to provide a semiconductor integrated circuit having a chip layout that reduces line length to achieve faster processing. A cache comprises a TAG memory module and a cache data memory module. The cache data memory module is divided into first and second cache data memory modules which are disposed on both sides of the TAG memory module, and input/output circuits of a data TLB are opposed to the input/output circuit of the TAG memory module and the input/output circuits of the first and second cache data memory modules across a bus area to reduce the line length to achieve faster processing.

Abstract: A semiconductor integrated circuit device is comprised a main memory portion constituted with memory cells arranged in a plurality of rows and in a plurality of columns and a sub memory portion constituted with memory cells arranged in a plurality of rows and in a plurality of columns, wherein at least one of address input terminals assigning rows or columns of the main memory portion and at least one of address input terminals assigning rows or columns of the sub memory portion are commonly used and a total number of address input terminals is equal to or smaller than the number of address input terminals assigning rows or columns of the main memory portion. Therefore, the semiconductor integrated circuit device of the present invention has a main memory suitable for being accessed from a plurality of data processors.