Abstract: A plurality of result signals are driven low when abnormal condition is detected and driven high when no abnormal condition is detected. Presence and absence of the abnormal conditions of different types are indicated in a predetermined sequence by high and low signal levels of the result signals. The voltage detecting circuits simultaneously output the result signals on corresponding branching lines connected to a main line of a communication line. An OR gate outputs a result signal on which the result signals output by the voltage detecting circuits are superimposed. When at least one of the result signals of the voltage detecting circuits is at a level indicative of the presence of the abnormal condition, the OR gate outputs on the main line the result signal having the level indicative of the abnormal condition.

Abstract: A method and apparatus for determining an RC (resistive-capacitive) time constant is disclosed. In one embodiment, a method comprises determining a first period of oscillation when an oscillator is operating in a first configuration. The method further comprises determining a second period of oscillation when the oscillator is operating in a second configuration. A measurement circuit is configured to determine a resistive-capacitive (RC) time constant of the oscillator by determining a mean of the first and second periods.

Abstract: A method and apparatus for determining an RC (resistive-capacitive) time constant is disclosed. In one embodiment, a method comprises determining a first period of oscillation when an oscillator is operating in a first configuration. The method further the method further comprises determining a second period of oscillation when the oscillator is operating in a second configuration. A measurement circuit is configured to determine a resistive-capacitive (RC) time constant of the oscillator by determining a mean of the first and second periods.

Abstract: A measuring circuit is provided for a memory integrated within a semiconductor device. The measuring circuit includes initializing means and an oscillating loop. The initializing means loadings two complementary values into at least two locations of the memory. The two locations are addressed by a first address and a second address. The oscillating loop comprises a logic circuit for alternatively generating the first address and the second address from data read from the memory so as to successively read data from the first and second memory locations to produce an oscillating signal that has a frequency that depends on internal parameters of the memory. Also provided is a method for qualifying a memory by initializing the memory by loading two complementary values into two locations, and generating an oscillating signal with a frequency that is dependent on internal parameters of the memory.

Abstract: The motion detector includes at least one element moving at least temporarily, a circuit assembly for sensing the motional condition of the element comprising at least one sensor located adjoining the element and including a timed pulse activated oscillating circuit which is differingly damped depending on the motional condition of the element, a signal processing circuit for forming the signals of the oscillating circuit suitable for analysis in an analyzer receiving and analyzing the signals output by the signal processing circuit. The signal processing circuit of the motion detector includes a comparator, to the input of which at least the positive or negative half waves of the oscillating circuit signals are applied and to the other input of which a reference voltage is applied selected so that when the sensor is activated the output signal of the comparator changes its condition differingly frequently depending on the how the sensor is damped by the element.