Abstract: Provided are a phase detection method and apparatus for a clock signal, and a communication device. A clock signal of a clock to be detected is sampled according to sampling periods set by a sampling clock; a phase angle value corresponding to a sampled clock signal in a current sampling period is obtained according to a mapping relationship between sampled signals and phase angle values; a phase difference corresponding to the current sampling period is subtracted from the phase angle value to obtain an initial phase value of the clock to be detected in the current sampling period, wherein the phase difference is a phase difference between the clock to be detected and the sampling clock in the current sampling period; and after the sampling ends, a final phase value of the clock to be detected is obtained according to initial phase values obtained in respective sampling periods.

Abstract: A pin driver control system for enhancing pulse fidelity can include a first current switch circuit with a current input node and a voltage input node, wherein the first current switch circuit provides a switched output current signal in response to a voltage control signal at the voltage input node. The system can further include a first current source configured to receive a bias control signal and, in response, provide a drive current signal to the current input node of the first current switch. The drive current signal can have a magnitude that exceeds a magnitude of the switched output current signal. The system can further include a bias control circuit configured to receive information about a desired bias current magnitude for use by the first current switch circuit and, in response, provide the bias control signal to the first current source.

Abstract: A frequency estimator for estimating a frequency, including a counter configured to count an integer number of full clock cycles during a measurement time window; a Time-to-Digital Converter (TDC) configured to measure a fraction of a clock cycle during the measurement time window; and a processor configured to determine the estimated frequency based on the counted number of full clock cycles and the measured fraction of the clock cycle.

Abstract: An apparatus is provided which comprises: a frequency locked loop (FLL) comprising an oscillator including a plurality of delay stages, wherein an output of each delay stage is counted to determine a frequency of the FLL; and one or more circuitries coupled to the FLL to adjust a power supply to the FLL according to the determined frequency of the FLL.

Abstract: A method includes the following operations. A reference image of a mask having a plurality of mapping marks is acquired. A lithography exposing process is performed by a scanner with the mask to a photoresist layer which is formed on a substrate. Performing the lithography exposing process includes mapping a real-time image of the mask with the reference image of the mask.

Abstract: An embodiment method for signal path measurement includes providing a first signal at a common node coupled to a plurality of signal paths that each include a respective phase rotation circuit. The method also includes providing a second signal, over a first test path, to a first node coupled to a first signal path of the plurality of signal paths, providing the second signal, over a second test path, to a second node coupled to a second signal path of the plurality of signal paths, selecting a signal path from the plurality of signal paths, transmitting, over the selected signal path, one of the first signal and the second signal, and mixing the first signal with the second signal to obtain a measurement signal of the selected signal path. A difference in phase delay between the second test path and the first test path includes a first known phase delay.

Abstract: A delay circuit includes: a cyclic number control circuit that generates a third signal based on first and second signals generated based on a trigger signal; a loop circuit in which a plurality of delay elements are electrically connected in series, one output of outputs of the plurality of delay elements is fed back to form a loop, and the third signal is input to the delay element at an initial stage; and a latch circuit that latches output values of the plurality of delay elements as latch signals. The second signal is one output among the outputs of the plurality of delay elements. The loop circuit stops the feedback when a cyclic number of loops reaches a prescribed cyclic number.

Abstract: The method and device for analyzing position are disclosed. By analyzing sensing information with at least one zero-crossing, each position can be analyzed. The number of analyzed positions may be different from the number of zero-crossings. When the number of analyzed positions is different from the number of zero-crossing, the number of analyzed positions is more than one.

Abstract: An RF phase offset detection system, which includes a first RF phase detector and a second RF phase detector, and measures a first phase offset between a first RF signal and a second RF signal, is disclosed. Each of the first RF signal and the second RF signal has a common RF frequency. The first RF phase detector detects and filters the first RF signal and the second RF signal to provide a first detection signal. The second RF phase detector receives and phase-shifts the second RF signal to provide a phase-shifted RF signal. The second RF phase detector further detects and filters the first RF signal and the phase-shifted RF signal to provide a second detection signal, such that a combination of the first detection signal and the second detection signal is representative of the first phase offset.

Abstract: Systems and methods that efficiently simulate controlled systems are presented. A simulation management component (SMC) controls simulation of a controlled system by controlling a desired number of nodes, each comprising a controller (e.g., soft controller) and a simulated component or process, which are part of the controlled system. The simulation can be performed in a step-wise manner, wherein the simulation can comprise a desired number of steps of respectively desired lengths of time. For each step, the SMC dynamically selects a desired clock (e.g., currently identified slowest clock) as a master clock for the next step. The SMC predicts a length of time of the next step to facilitate setting a desired length of time for the next step based in part on the predicted length of time. As part of each step, components can synchronously exchange data via intra-node or inter-node connections to facilitate simulation.

Abstract: Systems for measuring optical properties of a specimen are disclosed. The systems are configured to sample signals related to the measurement of the properties of a specimen, and perform software-based coherent detection of the signals to generate resulting measurements are based on the signals acquired at substantially the same time instance. This facilitates the displaying or generating of the desired measurements in real time. In one configuration, the system is configured to direct a modulated light signal at a selected wavelength incident upon a specimen. In another configuration, the system is configured to direct a combined light signal, derived from a plurality of light signals at different wavelengths and modulated with different frequencies, incident upon a specimen. In yet another configuration, the system is configured to direct a plurality of light signals modulated with different frequencies incident upon different regions of a specimen.

Abstract: Described is an apparatus comprising: a delay line including at least four delay stages coupled together in a series; a first multiplexer having a first input coupled to an output of a first delay stage of the at least four delay stages, and a second input coupled to an output of a third delay stage of the at least four delay stages; a second multiplexer having a first input coupled to an output of a second delay stage of the at least four delay stages, and a second input coupled to an output of a fourth delay stage of the at least four delay stages; and a phase interpolator coupled to outputs of the first and second multiplexers, the phase interpolator having an output.

Abstract: Apparatuses and methods for low power counting circuits are described herein. An example apparatus may include a frequency divider configured to receive an input clock signal and adjust a frequency of the clock signal to provide an intermediate clock signal. The apparatus may further include a counter coupled to the frequency divider and configured to receive the intermediate clock signal. The counter may further be configured to provide a plurality of timing signals based on the intermediate clock signal. The apparatus may further include a frequency multiplier including a plurality of logic gates. Each of the plurality of logic gates may be coupled to the counter and configured to receive a respective first timing signal of the plurality of timing signals and at least one of the intermediate clock signal or a respective second timing signal of the plurality of timing signals.

Abstract: A circuit includes a signal generator, a delay pulse generator and a time-to-current converter. The signal generator is configured to generate a first signal including information on a rise delay and a second signal including information on a fall delay. A delay difference exists between the rise delay and the fall delay. The delay pulse generator is configured to provide an additional delay to one of the first and second signals. The time-to-current converter is configured to extract the delay difference.

Abstract: The present disclosure describes techniques and apparatuses for clone-resistant logic. In some aspects, this clone-resistant logic enables computing-device manufacturers to better protect their devices against use of inauthentic accessories.

Abstract: Disclosed is a monitoring device for a rotary encoder electronically connectable to the monitoring device. A pulse generating unit generates a comparison pulse signal by extracting a portion corresponding to a specific phase range from a first pulse included in a first pulse signal output from the rotary encoder. The rotary encoder detects rotation of a rotating body and outputs the first pulse signal and a second pulse signal, the first pulse signal and the second pulse signal having a phase difference from each other. A determining unit determines an abnormality of the rotary encoder, based on a state of a pulse of the comparison pulse signal at a specific timing of a second pulse included in the second pulse signal.

Abstract: Representative implementations of devices and techniques provide bipolar time-to-digital conversion. For example, either a positive time duration or a negative time duration may be converted to a digital representation by a linear time-to-digital converter (TDC). A set of logic functions may be applied to the input of the TDC to provide start and/or stop signals for the TDC. Further, a correction component may be applied to an input or an output of the TDC to compensate for a delay offset of the TDC.

Abstract: A signal generation device and a signal generation method may measure leakage currents, such as an input current value I and phase-shifted current values I cos ? and I sin ? in a short period of time and automatically output the detected values without calculating a vector of a phase difference. The signal generation device generates logical signals from a voltage waveform and a current waveform of a measured power line through first and second comparators, sets parameters, full-wave rectifies the current waveform, and performs quantization transform on the full-wave rectified current waveform using a successive ??ADC.

Abstract: A measurement device that performs a predetermined measurement task together with a plurality of other measurement devices is provided. This measurement device is provided with a sampling phase generator for generating a sampling phase for instructing a timing of sampling, and a communication unit for communicating with at least one of the plurality of other measurement devices. The communication unit transmits the sampling phase generated by the sampling phase generator to at least one of the plurality of other measurement devices. The sampling phase generator is configured to generate a third sampling phase, using an operation that is based on a generated first sampling phase and a second sampling phase received by the communication unit from at least one of the plurality of other measurement devices.

Abstract: A phase locked loop (PLL) lock detector may be configured to observe the phase error signal from a phase comparator of a PLL circuit. The PLL lock detector may accumulate a sum of phase errors and compare the sum of phase errors to determine whether the PLL circuit is locked in phase with the reference signal. Various modifications to the phase error signal and sum of phase errors may be used to improve the efficiency of the PLL lock detector. Configurable settings for the accumulator and a comparator may be used to adjust the operation of the PLL lock detector.

Abstract: This load connection state detection circuit includes a PNP type transistor whose emitter is connected to a power source terminal, a NPN type transistor where the emitter thereof is connected to the power source terminal, the collector thereof is connected to the base of the PNP type transistor, and the base thereof is connected to the collector of the PNP type transistor, and a diode inserted between the collector of the PNP type transistor and an external antenna load, wherein the diode is configured to perform temperature compensation for the base voltage of the NPN type transistor and prevent currents from flowing from the external antenna load to the PNP type transistor and the NPN type transistor.

Abstract: An alternating current phase detecting system includes a first arithmetic circuit, a second arithmetic circuit, and an inverted output module connected to the second arithmetic circuit. The first arithmetic circuit receives any first alternating current signal and the second arithmetic circuit receives a second alternating current signal. The first alternating current signal is converted to a first output signal and is output to the second arithmetic circuit. The second arithmetic circuit outputs a second output signal to the inverted output module which is fed by the second alternating current signal and the first output signal. The inverted output module obtains a phase value difference between the first alternating current signal and the second alternating current signal to establish 120 degree sequentiality between the two, or otherwise, to enable correct electrical connections to be made to a powered device.

Abstract: In a particular embodiment, a digital circuit includes a frequency detection circuit operative to compare information related to transitions between sequential samples of a received signal. The frequency detection circuit is further operative to generate a control signal to reduce a sampling rate of the received signal in response to a predetermined number of the sequential samples having a same value. The digital circuit also includes a digital phase detector operative to provide the information related to the transitions between sequential samples to the frequency detection circuit.

Abstract: An all-digital delay measurement circuit (DMC) constructed on an integrated circuit (IC) die characterizes clocking circuits such as full phase rotation interpolators, also constructed on the IC die. The on-die all-digital DMC produces a digital output value proportional to the relative delay between two clocks, normalized to the clock period of the two clocks.

Abstract: Systems provide for a test system for capacitors in a digitally controllable oscillator (DCO). The system includes: capacitor toggling logic configured to switch on and off a selected one of the capacitors at a modulation frequency; a tone generator configured to generate a tone; a mixer configured to receive the tone and an output carrier signal from the DCO while the capacitor toggling logic is switching the selected one of the capacitors on and off and to output an intermediate frequency signal having FM sidebands based on the modulation frequency and relative capacitor size; and an evaluation circuit configured to evaluate a frequency deviation associated with the selected one of the capacitors based on at least one of the FM sidebands.

Abstract: A method and a system are provided for clock phase detection. A set of delayed versions of a first clock signal is generated. The set of delayed versions of the first clock is used to sample a second clock signal, producing a sequence of samples in a domain corresponding to the first clock signal. At least one edge indication is located within the sequence of samples.

Abstract: A circuit configuration detects zero-crossings and/or a brownout condition. The circuit configuration contains a zero-crossing detection circuit, a brownout detection circuit, an isolation and digitization circuit connected to the zero-crossing detection circuit and the brownout detection circuit, and a filtering circuit connected to the isolation and digitization circuit. The single circuit configuration can be used for detecting zero-crossings of single-phase and multi-phase systems as well as ascertaining a brownout condition of either the single-phase or the multi-phase systems.

Abstract: In one embodiment, a timing relationship between two signals on an integrated circuit is measured using a ring oscillator on the die of the integrated circuit. The measured time difference is outputted in a digital form. A delay line coupled to the ring oscillator may be used to reduce uncertainty in measurement which may result from the effects of latch circuit metastability. Other embodiments are described and claimed.

Abstract: An integrated circuit (IC), comprises a receiver on an IC substrate. The receiver is configured to receive a stressed input signal. A built in self test (BIST) circuit is provided on the IC substrate for testing the receiver. The BIST circuit comprises an encoder configured for receiving an input signal and identifying whether a first condition is present, in which two or more consecutive input data bits have the same polarity as each other. An output driver circuit provides the stressed input signal corresponding to the two or more consecutive input data bits. The stressed input signal has an amplitude that is larger when the encoder identifies that the first condition is present and smaller when the encoder identifies that two or more consecutive input data bits have different polarity from each other.

Abstract: A method for digital triggering of a digital recording of a digitized measurement signal having a superimposed noise signal. The method includes generating from the digitized measurement signal a digital triggering signal for the digital triggering of the digital recording of the measurement signal, and performing band-limitation of the noise signal superimposed on the digitized measurement signal via a low-pass filtering before the digital triggering signal is generated. The bandwidth of the low-pass filtering is adjusted dependent upon edge steepness of the measurement signal, in order to reduce variance ?t2 in jitter of the digital triggering signal.

Abstract: A phase detection apparatus for an alternator is disclosed according to an embodiment of the present invention. The phase detection apparatus comprises a waveform detector, a threshold voltage generator, and a comparator. The waveform detector is used for detecting a wave peak of a phase signal, and generating a waveform detection signal accordingly. The threshold voltage generator is used for generating a reference signal according to the waveform detection signal. The comparator is used for comparing the phase signal with the reference signal, and generating a comparison signal accordingly. Therefore, the phase detection apparatus for the alternator may reduce the leakage current of a battery in a vehicle.

Abstract: A system for measuring a voltage drop between two nodes in an electrical circuit, comprising a switched capacitor integrator (SCI), a comparator and a counter. The SCI alternately (a) captures charge onto a set of sampling capacitors and (b) selectively accumulates/transfers the charge onto a pair of integration capacitors, where the charge includes a first portion that is based on the voltage drop and a second portion that depends on a digital indicator signal. The comparator generates the digital indicator signal based on whether an analog output of the SCI is positive or negative. The counter counts a number of ones occurring in the digital indicator signal during a measurement interval. At the end of the measurement interval, the count value represents a measure of the voltage drop. Knowing the resistance between the two nodes, the voltage drop may be converted into a current measurement.

Abstract: The service phase of the electrical connection to a customer endpoint device located within a power distribution system is determined by various techniques. At the feeder level, the system may be programmed to induce momentary power interruptions, thereby causing missed zero crossings at the customer endpoint devices. The pattern of these interruptions is a controlled one, designed specifically to avoid causing noticeable disruption even to sensitive devices, but to be unusual enough that it is statistically unlikely to be naturally occurring. The monitoring of the zero crossing information is used to determine the phase of the service line to the customer endpoint devices.

Abstract: In a particular embodiment, a digital circuit includes a frequency detection circuit operative to compare information related to transitions between sequential samples of a received signal. The frequency detection circuit is further operative to generate a control signal to reduce a sampling rate of the received signal in response to a predetermined number of the sequential samples having a same value. The digital circuit also includes a digital phase detector operative to provide the information related to the transitions between sequential samples to the frequency detection circuit.

Abstract: A timing adjusting circuit including a time amplifier and a phase adjusting module is provided. The time amplifier is used for increasing the active pulse-width of a phase control signal, so as to generate an adjusted control signal. Based on the adjusted control signal, the phase adjusting module adjusts the phase of an output signal. The phase of the output signal is associated with the active pulse-width of the phase control signal.

Abstract: A method for digital phase detection, comprises the steps of: providing a reference clock; receiving a feedback clock; determining a timing difference between the reference clock and the feedback clock; determining a polarity that indicates the leading or lagging relationship between the reference clock and the feedback clock; adaptively selecting one of at least two operating modes for generating a quantized level indicative of the timing difference, wherein in a first operating mode the quantized level is a constant maximum value and wherein in a second operating mode the quantized level is proportional to the timing difference; and generating a digital phase detection output as a combination of the polarity and the quantized level.

Abstract: In one embodiment, the present invention includes a system having an electromagnetic coupler probe to electromagnetically sample signals from a device under test or a link under test and a receiver, e.g., configured as an integrated circuit that is to receive the sampled electromagnetic signals from the probe and output digital signals corresponding thereto. Other embodiments are described and claimed.

Abstract: Provided is a test apparatus for testing a device under test that outputs, as an output signal, an amplitude-phase modulated signal having a level and a transition point phase selected from among a plurality of levels and a plurality of phases according to transmission data, the test apparatus comprising a comparing section that compares the output signal to a first comparison level, which is less than the expected level, before the expected phase, and compares the output signal to a second comparison level, which is greater than the expected level, and to a third comparison level, which is less than the expected level, after the expected phase; and a judging section that judges that the output signal matches the expected values on a condition that (i) the output signal is less than or equal to the first comparison level before the expected phase and (ii) the output signal is less than or equal to the second comparison level and greater than or equal to the third comparison level after the expected phase.

Abstract: A phase locked loop device includes a phase detector that measures a difference in phase between a reference clock signal and an output clock signal of the phase locked loop. The phase detector provides a pulse having a width indicative of the phase difference. A phase measurement module determines a digital value based on the pulse width. Accordingly, the digital value provides an indication of the phase difference between the reference clock signal and the output clock signal. A series of the digital values can be recorded to indicate how the phase difference varies over time, thereby providing a useful characterization of device behavior.

Abstract: An apparatus including a circuit configured to measure timing between features in a first signal only referring to timing information contained in the signal itself.

Abstract: A phase difference detector for detecting a phase difference between input clocks which both have a same first frequency, including: a pulse width conversion unit for converting the input clocks into a phase difference signal indicating by a pulse width a phase difference between the input clocks; and a counter unit which samples a level of the phase difference signal using a reference clock having a second frequency which is slower than the first frequency, and counts the number of levels of the phase difference signal using a first weighting according to the sampled level of the phase difference signal. When the count value of the counter unit transits in a predetermined range, the phase difference between the input clocks is detected according to the first weighting.

Abstract: An on-chip jitter measurement circuit and corresponding method are provided for receiving a reference clock and a signal of interest, the circuit including a latch for latching and comparing the arrival time of the signal of interest to the reference clock, a clock counter in signal communication with the latch for counting the number of reference clock cycles received and latched, a delay chain in signal communication with the reference clock for varying the arrival time of the reference clock, the delay chain having a first stage, middle stages, and a last stage, and a voltage controller in signal communication with at least one of the middle stages of the delay chain for controlling the delay of the arrival time of the reference clock, wherein the voltage controller controls the first and last stages of the delay chain to retain a full voltage swing independent of the delay.

Abstract: A system for measuring the time interval of a signal. The second signal has a frequency higher than a frequency of the first signal. According to one embodiment, the system includes an electronic circuit for determining an approximation of the time based on a period of the second signal and for determining an adjustment to the approximation based on the second signal and a third signal corresponding to the second signal and aligned with the first signal. The length of the adjustment is less than the period of the second signal.

Abstract: In one embodiment, a timing relationship between two signals on an integrated circuit is measured using a ring oscillator on the die of the integrated circuit. The measured time difference is outputted in a digital form. A delay line coupled to the ring oscillator may be used to reduce uncertainty in measurement which may result from the effects of latch circuit metastability. Other embodiments are described and claimed.

Abstract: The traveling wave excitation system phase shifter chassis method and device of the invention is compact, inexpensive, and versatile when compared to customary methods for generating traveling wave excitation signals that would require using an equivalent number of commercial function generators. The method and device of the invention produces up to 56 simultaneous sine waves that are phase shifted with respect to one another.

Abstract: A digital filter device capable of removing the effect of noise such as chattering from a zero crossing signal is provided. A digital filter device 4 filtering a binary digital signal DIN and outputting a binary digital signal DOUT is provided with a toggle flip-flop 12 which switches a signal level of the digital signal DOUT each time a trigger signal is input; an XOR circuit 13 which outputs a first enable signal EN1 while a signal level of the digital signal DIN does not match with the signal level of the output digital signal DOUT; and a charge counter 14 which counts in synchronization with a clock signal CLK while the first enable signal EN1 is input and resets the count to an initial value and outputs a carry on signal ON_RCO as the trigger signal to the toggle flip-flop 12 when the count has reached an upper limit value.

Abstract: A phase difference detector for detecting a phase difference between input clocks which both have a same first frequency, including: a pulse width conversion unit for converting the input clocks into a phase difference signal indicating by a pulse width a phase difference between the input clocks; and a counter unit which samples a level of the phase difference signal using a reference clock having a second frequency which is slower than the first frequency, and counts the number of levels of the phase difference signal using a first weighting according to the sampled level of the phase difference signal. When the count value of the counter unit transits in a predetermined range, the phase difference between the input clocks is detected according to the first weighting.

Abstract: Methods and systems are provided for an improved phase detector utilizing analog-to-digital converter (ADC) components. In an embodiment, the method includes from an ADC having a sampling clock signal that determines sampling instants, obtaining a first comparison value between an analog signal and a first threshold voltage at a first sampling instant, and obtaining a second comparison value between the analog signal and a second threshold voltage at a second sampling instant. The method further includes, from a supplemental circuit, obtaining a third comparison value between the analog signal and a third threshold voltage at a third sampling instant between the first and second sampling instants. The method further includes processing the first, second, and third comparison values to determine a phase relationship between the analog signal and the sampling clock.

Abstract: A power generation system including a RF power generator which provides a RF output power. The power distribution system includes a phase-magnitude detector module having a dual logarithmic amplifier phase-magnitude detector. The dual logarithmic amplifier phase-magnitude detector receives current and voltage signals. The dual logarithmic amplifier phase-magnitude detector generates a phase signal that varies in accordance with the phase between the voltage signal and the current signal and a magnitude signal that varies in accordance with the magnitude between the voltage and current signals. A controller receives the phase and magnitude signal and communicates control signals to the matching network.

Abstract: A failure detection apparatus for a semiconductor apparatus includes a clock line to transmit a clock signal, a shield line to shield the clock line, an inverted signal setting unit to supply signals inverted to each other to the clock and shield lines in a failure detection mode, and a failure detection evaluator to detect a failure by comparing static current consumption in each of the failure detection mode and a normal operation mode.