Negative Resistance Device Patents (Class 326/135)
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Patent number: 8669785Abstract: Logic circuits using neuristors is described. In an example, a circuit includes a plurality of neuristors each producing an output voltage spike in response to a super-threshold input voltage. A plurality of impedances couple the plurality of neuristors to form at least one input and an output, the output selectively providing an output voltage spike based on a logical operation of at least one input voltage at the at least one input.Type: GrantFiled: July 31, 2012Date of Patent: March 11, 2014Assignee: Hewlett-Packard Development Company, L.P.Inventor: Matthew D. Pickett
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Patent number: 8593180Abstract: A circuit includes a negative differential resistance (NDR) device which includes a gate and a graphene channel, and a gate voltage source which modulates a gate voltage on the gate such that an electric current through the graphene channel exhibits negative differential resistance.Type: GrantFiled: March 12, 2012Date of Patent: November 26, 2013Assignee: International Business Machines CorporationInventors: Shu-Jen Han, Yu-Ming Lin, Yanqing Wu
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Patent number: 8525553Abstract: In one example, an oxide-based negative differential resistance comparator circuit includes a composite NDR device that includes a first electrode, a first thin film oxide-based negative differential resistance (NDR) layer in contact with the first electrode and a central conductive portion. The composite NDR device also includes a second thin film oxide-based NDR layer disposed adjacent to the first NDR layer and a second electrode. A resistor may be placed in series with the composite NDR device and an electrical energy source can apply applying a voltage across the first electrode and second electrode. The composite NDR device produces a threshold based comparator functionality in the comparator circuit.Type: GrantFiled: April 30, 2012Date of Patent: September 3, 2013Assignee: Hewlett-Packard Development Company, L.P.Inventors: Wei Yi, Jianhua Yang, Matthew D. Pickett, Minxian Max Zhang
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Patent number: 7684427Abstract: A switching matrix has a first number of inputs and a second number of outputs as well as a conductor arrangement and controllable switching elements by means of which the inputs can be connected with the outputs. The controllable switching elements are fashioned such that at least two independent control signals are required to trigger a switching event.Type: GrantFiled: November 18, 2005Date of Patent: March 23, 2010Assignee: Siemens AktiengesellschaftInventor: Horst Kröckel
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Patent number: 7573310Abstract: The present invention relates to a SET/RESET latch circuit a Schmitt trigger circuit, and a MOBILE based D-type flip flop circuit and frequency divider circuit using the SET/RESET latch circuit and Schmitt trigger circuit. The SET/RESET latch circuit is configured with CML-type transistors and negative differential resistance diodes. The SET/RESET latch circuit can be applied to very high speed digital circuits.Type: GrantFiled: May 5, 2006Date of Patent: August 11, 2009Assignee: Korea Advanced Institute of Science and TechnologyInventors: Kyoung-Hoon Yang, Tae-Ho Kim, Yongsik Jeong
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Patent number: 7548094Abstract: Systems and methods for on-chip signaling are disclosed. In some embodiments, an integrated circuit having on-chip signaling between a first component and a second component includes, a differential interconnect capable of coupling the first component to the second component, a driver capable of being coupled to the first component that sends data on the differential interconnect, a receiver capable of being coupled to the second component that receives the data, and a plurality of negative impedance converters capable of being coupled to the differential interconnect that provide loss compensation.Type: GrantFiled: January 17, 2007Date of Patent: June 16, 2009Assignee: The Trustees of Columbia University in the City of New YorkInventors: Kenneth L. Shepard, Anup P. Jose
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Patent number: 7403032Abstract: The present invention relates to CML(Current Mode Logic)-type input driving method and tunneling diode logic using MOBILE(Monostable Nistable transition Logic Element) configuration, as kinds of very high-speed digital logic circuits. The objectives of the present invention are to improve the disadvantage of MOBILE circuit configuration that is an existing tunneling diode logic, and at the same time provide new MOBILE based logic functions. Wherein, the difficulty for input voltage adjustment is resolved by replacing the input part with a CML input driving gate, and speed problem due to transistor is resolved. Moreover, a plurality of logic functions such as inverted return-to-zero D flip-flop, non-inverted return-to-zero D flip-flop, return-to-zero OR gate, return-to-zero D flip-flop generating differential output, and optical flip-flop are implemented.Type: GrantFiled: June 15, 2005Date of Patent: July 22, 2008Assignee: Korea Advanced Institute of Scientififc and TechnologyInventors: Kyoung Hoon Yang, Sun Kyu Choi
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Patent number: 7372306Abstract: A method and state stabilizer for enhancing computing functionality by using fast excitations are described. The state stabilizer includes a voltage source for producing fast excitations having an associated excitation amplitude. An electronic device having an associated negative differential resistance region is also included. The excitation amplitude is greater than a width of the negative differential resistance region.Type: GrantFiled: February 14, 2006Date of Patent: May 13, 2008Assignee: The Regents of the University of CaliforniaInventors: Alexander Khitun, Kang L. Wang
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Patent number: 7304509Abstract: There is disclosed an impedance circuit which realizes negative impedance with ease, and a power supply device having negative output impedance. An impedance circuit 1 connected to an external circuit comprises: a current inverter circuit 11 having an input terminal connected to outside; a passive circuit 10 having an input terminal connected to an output terminal of the current inverter circuit 11; and a current inverter circuit 12 having an input terminal connected to an output terminal of the passive circuit 10 and an output terminal connected to outside. The current inverter circuits 11 and 12 work in cooperation with each other, to make magnitude of impedance of the impedance circuit 1 proportional to impedance of the passive circuit 10, and to invert the polarity of the impedance of the impedance circuit 1.Type: GrantFiled: January 30, 2006Date of Patent: December 4, 2007Assignee: Fujitsu LimitedInventor: Yutaka Fukui
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Patent number: 6864816Abstract: An apparatus includes a quantizer circuit having a resonant tunneling device with an operational characteristic that includes a first region of unstable operation, and second and third regions of stable operation. An input terminal and an output terminal are each coupled to one end of the resonant tunneling device. A bias section is coupled to the resonant tunneling device, and responds to a clock signal by alternately operating in a first mode where the resonant tunneling device is forced to operate within the first region, and a second mode where the resonant tunneling device is permitted to operate in either of the second and third regions.Type: GrantFiled: January 21, 2004Date of Patent: March 8, 2005Assignee: Raytheon CompanyInventor: Gary A. Frazier
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Patent number: 6784689Abstract: A negative impedance device that accelerates signal transitions on a signal is provided. The negative impedance device is highly responsive to high to low and low to high transitions on the signal, and when one of these types of transitions begins to occur on the signal, the negative impedance device senses the transition and quickly drives the signal to the intended value before a point in time when the signal would have reached the intended value had the negative impedance device not been used. Further, a signal transition accelerator design that reduces signal rise and fall times is provided. Further, a method for accelerating a signal transition is provided.Type: GrantFiled: February 6, 2002Date of Patent: August 31, 2004Assignee: Sun Microsystems, Inc.Inventors: Sudhakar Bobba, Pradeep Trivedi
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Patent number: 6724655Abstract: A memory cell using both negative differential resistance (NDR) and conventional FETs is disclosed. A pair of NDR FETs are coupled in a latch configuration so that a data value passed by a transfer FET can be stored at a storage node. By exploiting an NDR characteristic, the memory cell can be implemented with fewer active devices. Moreover, an NDR FET can be manufactured using conventional MOS processing steps so that process integration issues are minimized as compared to conventional NDR techniques.Type: GrantFiled: December 21, 2001Date of Patent: April 20, 2004Assignee: Progressant Technologies, Inc.Inventor: Tsu-Jae King
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Patent number: 6486707Abstract: CMOS semiconductor pass-transistor logic circuitry (200) is disclosed, comprising pass transistor circuitry (204, 212, 218), and tunneling structure circuitry (228) coupled to the pass transistor circuitry; where the tunneling structure circuitry is adapted to hold a node (222) voltage stable by compensating a leakage current (302) originating from said pass transistor circuitry.Type: GrantFiled: July 17, 2000Date of Patent: November 26, 2002Assignee: Texas Instruments IncorporatedInventor: Xiaowei Deng
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Patent number: 6323709Abstract: A high-speed, compact, edge-triggered flip-flop circuit is provided which includes an input circuit section, a latch circuit section and an output circuit section. The input circuit section includes at least one transistor such as a field-effect transistor (FET) which determines the logic function of the flip-flop such as D, S-R, or T, and provides a first stage of latching. The input circuit section receives the logic control signals such as D, S-R, or T, and a clock signal. In one embodiment of the invention, the latch circuit section includes two series-connected negative differential resistance (NDR) diodes. In this embodiment, a common terminal of the two NDR diodes is connected to the data output of the input circuit section and to the data input of the output circuit section.Type: GrantFiled: May 18, 2000Date of Patent: November 27, 2001Assignee: The Regents of the University of MichiganInventors: Shriram Kulkarni, Mayukh Bhattacharya, Pinaki Mazumder
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Patent number: 6323708Abstract: The present invention includes: a series circuit which has a negative differential resistance element and another negative differential resistance element that has a control terminal capable of controlling a value of an element current; a transfer gate; a latch circuit which has negative differential resistance elements connected in series; and an inverter circuit which has an FET as a drive element and a negative differential resistance element as a load element. With this, such a flip-flop can be obtained that when a clock signal is applied to a power supply terminal of the series circuit and a control terminal of the transfer gate and an input signal is supplied to the control terminal of the negative differential resistance element, an output is placed at a terminal.Type: GrantFiled: April 26, 2000Date of Patent: November 27, 2001Assignee: NEC CorporationInventor: Tetsuya Uemura
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Patent number: 6316965Abstract: A circuit includes at least one negative differential resistance (NDR) device and at least one magnetic device having reversibly variable resistance, wherein the negative differential resistance device and the magnetic device are operatively connected so that changing the resistance of the magnetic device changes the current-voltage response characteristics of the circuit. NDR devices and magnetic devices can be arranged to form multiple value logic (MVL) cells and monostable-bistable transition logic elements (MOBILE), and these logic cells can form the components of a field programmable gate array.Type: GrantFiled: June 15, 2000Date of Patent: November 13, 2001Assignee: The United States of America as represented by the Secretary of the NavyInventors: Berend T. Jonker, Richard Magno
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Patent number: 6097036Abstract: A semiconductor logic element is provided which is capable of a plurality of logic operations. The semiconductor logic element includes a semiconductor substrate on which is disposed at least three control electrodes and an output electrode for outputting signals in response to inputs to said control electrodes, making it possible to significantly reduce the number of elements constituting a logic circuit and to provide high speed processors and electronic computers. Logic circuitry and apparatus using the semiconductor logic elements are also provided.Type: GrantFiled: September 8, 1997Date of Patent: August 1, 2000Assignee: Hitachi, LLPInventors: Tatsuya Teshima, Hiroshi Mizuta, Ken Yamaguchi
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Patent number: 5789940Abstract: Multiple resonant tunneling devices offer significant advantages for realizing ultra-dense, ultra-high performance multivalued logic arithmetic integrated circuits. A multivalued logic adder is disclosed, wherein two numbers represented by positive digit base-M range-N words are added by two-input summation circuits 40 which sum corresponding digits, then the digit sums are decomposed into a binary representation by range-7 multivalued to binary converter circuits 42, then three-input summation circuits 44 sum appropriate bits of the binary representations to calculate the digits of a positive digit base-2 range-4 word whose value is the sum of the two numbers. Preferably, the decomposition to binary representation is performed by multi-valued folding circuits 56 which are connected by voltage divider circuitry. Preferably, the multi-valued folding circuits contain multiple-peak resonant tunneling transistors 54. Ripple carries are eliminated and the speed of the adder is independent of input word width.Type: GrantFiled: April 3, 1997Date of Patent: August 4, 1998Assignee: Texas Instruments IncorporatedInventor: Albert H. Taddiken
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Patent number: 5773996Abstract: A multiple-valued logic circuit includes a first device, a second device, a signal source, and a signal output terminal. The second device is connected in series with the first device. The signal source supplies an oscillating voltage across a series circuit consisting of the first device and the second device. The first device is constituted by at least one unit device having first and second main terminals and exhibiting voltage-current characteristics including negative differential resistance characteristics for obtaining a peak current between the first and second main terminals. The second device is constituted by at least two series-connected unit devices each having first and second main terminals and exhibiting voltage-current characteristics including variable negative differential resistance characteristics for obtaining a peak current changing between the first and second main terminals.Type: GrantFiled: May 22, 1996Date of Patent: June 30, 1998Assignee: Nippon Telegraph and Telephone CorporationInventor: Waho Takao
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Patent number: 5537076Abstract: A new negative resistance circuit comprises a first N-channel enhancement FET (E-FET), an N-channel depletion FET as a load element connected to the first N-channel E-FET to form a series branch connected between negative resistance ports, and a second N-channel E-FET having source-drain path parallel to the series branch. The gate of the second N-channel E-FET is connected to the connection node between the load element and the first E-FET, while the gate electrode of the first E-FET is connected to a control port for controlling current-voltage characteristic between the negative resistance ports. The negative resistance circuit can be used in an inverter to enable the inverter to have a hysteretic function or a multivalued logic function.Type: GrantFiled: May 2, 1994Date of Patent: July 16, 1996Assignee: NEC CorporationInventor: Masahiro Fujii
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Patent number: 5469163Abstract: Multiple resonant tunneling devices offer significant advantages for realizing circuits which efficiently convert values represented by multivalued number systems to conventional binary representation. In one form of the invention, a number represented by a range-4 base-2 word is converted into a conventional binary word (range-2 base-2) having the same value. The conversion is accomplished by a series of decomposition stages 53, each decomposition stage 53 producing an interim range-4 base-2 word and a binary digit, which becomes one of the digits of the binary output word. Preferably, the decomposition at each stage is accomplished by a set of range-4 base-2 to binary converters 50, each of which operates on a single digit of the interim word. Preferably, summation circuits 52 sum outputs of adjoining range-4 base-2 converters 50 to form the new interim word. The least significant digit of the output of the decomposition stage becomes a digit of the output binary word.Type: GrantFiled: May 24, 1993Date of Patent: November 21, 1995Assignee: Texas Instruments IncorporatedInventor: Albert H. Taddiken