Abstract: A technique relates to a circuit for a sum frequency generator. A first resonator is connected to a Josephson ring modulator (JRM), and the first resonator is configured to receive a first photon at a first frequency. A second resonator is connected to the JRM, and the second resonator is configured to have a first harmonic and no second harmonic. The second resonator is configured to receive a second photon at a second frequency, and the first resonator is configured to output an up-converted photon. The up-converted photon has an up-converted frequency that is a sum of the first frequency and the second frequency.

Abstract: One embodiment of the invention includes a quantum processor system. The quantum processor system includes a first resonator having a first characteristic frequency and a second resonator having a second characteristic frequency greater than the first characteristic frequency. A qubit cell is coupled to each of the first resonator and the second resonator. The qubit cell has a frequency tunable over a range of frequencies including the first characteristic frequency and the second characteristic frequency. A classical control mechanism is configured to tune the frequency of the qubit cell as to transfer quantum information between the first resonator and the second resonator.

Abstract: The present disclosure relates to methods and systems for data tag control for quantum dot cellular automata (QCA). An example method includes receiving data, associating a data tag with the data, communicating the data tag along a first wire-like element to a local tag decoder, reading instructions from the data tag using the local tag decoder, communicating the instructions to a processing element, communicating the data along a second wire-like element to the processing element, and processing the data with the processing element according to the instructions. A length of the first wire-like elements and a length of the second wire-like element are approximately the same such that communication of the instructions and the data to the processing element are synchronized.

Abstract: Systems and methods are provided for performing a quantum gate operation. A first classical control parameter is associated with a first qubit and coupled to a resonator. The first classical control parameter is transitioned from a first control value to a second control value. The first classical control parameter is returned from the second control value to the first control value via an adiabatic sweep operation, as to permit a transfer of energy between the first qubit and the resonator that causes a change in the quantum state of the qubit and resonator.

Abstract: A programmable phase shifter is constructed of Rapid Single Flux Quantum (RSFQ) logic elements. The logic elements may include an RSFQ inverter and an RSFQ T flip-flop. A digital word comprising N bits is used to control the amount of phase shift and the phase shifter selectively imparts a respective phase shift for any of 2N states that can be represented by the digital word. The RSFQ logic elements utilize Josephson junctions which operate in the superconducting temperature domain.

Abstract: Systems and methods for copying the classical state of a source qubit to a target qubit are provided. These techniques may be used to read out the states of an array of qubits.

Abstract: A programmable phase shifter is constructed of Rapid Single Flux Quantum (RSFQ) logic elements. The logic elements may include an RSFQ inverter and an RSFQ T flip-flop. A digital word comprising N bits is used to control the amount of phase shift and the phase shifter selectively imparts a respective phase shift for any of 2N states that can be represented by the digital word. The RSFQ logic elements utilize Josephson junctions which operate in the superconducting temperature domain.

Abstract: A superconductor crossbar switch for connecting a plurality of inputs with a plurality of outputs, including a switching cell having an input, an output and a circuit for connecting the input with the output for bidirectionally transmitting data therebetween. The connection of the retaining and releasing circuitry of a plurality of cells enables the switch to simultaneously retain a selected cell or cells of a group of cells and disable the remaining cells of that group, whereby a subsequent query on a disabled cell is inoperative until the selected cell or cells is released. The crossbar switch is characterized by latency on the order of nanoseconds, a data rate per channel on the order of gigabits per second, essentially zero crosstalk, and detection of contention in nanoseconds or less and resolution of contention in nanoseconds or less.

Abstract: A superconducting circuit includes a first transformer to produce a first alternating-current output at a secondary-side inductor, a second transformer to produce a second alternating-current output at a secondary-side inductor, a first pulse generating circuit to produce a single flux quantum pulse responsive to the first alternating-current output, a second pulse generating circuit to produce a single flux quantum pulse responsive to the second alternating-current output, and a confluence buffer circuit to merge the single flux quantum pulses from the pulse generating circuits, wherein each of the pulse generating circuits includes a superconducting loop including the secondary-side inductor, a first Josephson junction situated in the superconducting loop to generate the single flux quantum pulse, and a second Josephson junction situated in the superconducting loop, a threshold value of the second Josephson junction for an electric current flowing through the secondary-side inductor being different from tha

Abstract: A circuit includes a latch circuit including a Josephson junction and configured to perform a latch operation based on a hysteresis characteristic in response to a single flux quantum, a load circuit including load inductance and load resistance and coupled to an output of the latch circuit, and a reset circuit provided between the output of the latch circuit and the load circuit and configured to reset the latch circuit a predetermined time after the latch operation by the latch circuit, wherein the Josephson junction is driven by a direct current.

Abstract: A superconductor crossbar switch for connecting a plurality of inputs with a plurality of outputs, including a switching cell having an input, an output and a circuit for connecting the input with the output for bidirectionally transmitting data therebetween. The connection of the retaining and releasing circuitry of a plurality of cells enables the switch to simultaneously retain a selected cell or cells of a group of cells and disable the remaining cells of that group, whereby a subsequent query on a disabled cell is inoperative until the selected cell or cells is released. The crossbar switch is characterized by latency on the order of nanoseconds, a data rate per channel on the order of gigabits per second, essentially zero crosstalk, and detection of contention in nanoseconds or less and resolution of contention in nanoseconds or less.

Abstract: A superconductor memory array (10) has a high associated throughput with low power dissipation and a simple architecture. The superconductor memory array (10) includes memory cells (12a-12d) arranged in a row-column format and each including a storage loop (14a-14d) with a Josephson junction (16a-16d) for storing a binary value. Row address lines (24a, 24b) each are magnetically coupled in series to a row of the memory cells (12a-12d), and column address lines (26a, 26b) each are connected in series to a column of the memory cells (12a-12d). A sense amplifier (38a, 38b) is located on each of the column address lines (26a, 26b) for sensing state changes in the memory cells (12a-12d) located in the columns during a READ operation initiated by row address line READ signals.

Abstract: CMOS semiconductor latch and register (500) circuitry is disclosed, comprising a first tunneling structure latch circuit (502); data input circuitry (506), coupled and adapted to pass data to (504) said first tunneling structure latch circuit (502), a second tunneling structure latch circuit (514), data transmission circuitry (516), coupled between said first and second tunneling structure latch circuits, and adapted to transfer data from said first tunneling structure latch circuit to said second tunneling structure latch circuit, and data output circuitry (518), coupled to (512) said second tunneling structure latch circuit (514).

Abstract: A very fine-grained gate array cell is provided that includes a two-input logic device and a cascade NAND gate with buffered output. The NAND gate accepts a cascade input from another cell, and the cascade output of the NAND gate is provided as a cascade input to the other cell to facilitate the efficient implementation of cross-coupled devices. Each cell contains integral routing paths that facilitate a “sea of cells” layout approach. To ease the routing task, the output of each gate array cell is pre-wired so as to facilitate a programmed interconnection to each logic input of adjacent cells, near-adjacent cells, and far cells, and the aforementioned cascade interconnection with adjacent upper and lower cells. This configuration allows adjacent and near-adjacent cells to be easily interconnected to form macro cells that conform to higher level functional blocks.

Abstract: A novel magnetic tunnel device capable of displaying a magnetic tunnelling effect in stability and with high sensitivity even to an external magnetic field of a weak intensity. The magnetic tunnel device 1 has a layered structure including a first magnetic layer 2, a granular layer 3 layered on the first magnetic layer 2 and a second magnetic layer 4 layered on the surface of the granular layer 3 opposite to its surface carrying the first magnetic layer 2. The granular layer 3 has a granular structure which is made up of a magnetic metal phase 7 and an insulating phase 8. The first magnetic layer 2 and/or the second magnetic layer 4 of the magnetic tunnel device is formed of a ferromagnetic material having soft magnetic properties. The current is supplied in the layering direction of the layered structure.