Abstract: A poller including an output (S), as well as a first (E1), a second (E2), and a third (E3) input, receiving respectively a first (E.sub.s 1), a second (E.sub.s 2), and a third (E.sub.s 3) signal, which are identical during normal operation. The poller further includes a two-channel diverter (AIG1) provided with an active input (A), a quiescent input (R), a control input (EC) and a common output (SC). The quiescent input (R) and the active input (A) of the diverter (AIG1) are respectively connected to the first (E1) and second (E2) inputs of the poller, whereas the common output (S) of the diverter (AIG1) is connected to the output (S) of the poller. A first monitor (M1) with two inputs (X, Y), branched between the second and third inputs (E2, E3) of the poller, is used to measure the deviation between the second (E.sub.s 2) and third (E.sub.s 3) signals and to control the diverter (AIG1).

Abstract: An apparatus and method for transmitting information between dual redundant components comprises two information sources each of which is coupled to two transmitters, the outputs of which are coupled to four signal paths for transmission to two independent voters. Each of the voters compares predetermined pairs of the signals on the four signal paths and provides a preferred one of the signals to a corresponding receiver based on the results of the pair comparisons.

Abstract: A controller for a first in first out (FIFO) memory comprises detector logic for detecting any difference between the number of addresses in the memory into which data is written and the number of addresses in the memory from which data is read. Comparator logic connected to the detector logic generates a request data transfer signal in response to said difference becoming greater than or equal to a threshold. Threshold select logic connected to the comparator logic is responsive to data having first and second portions being written to the memory. The threshold select logic sets the threshold to a first value when the first portion is being written and sets the threshold to a second value, greater than the first value, when the second portion is being written.

Abstract: A fault-tolerant clock having at least four channels, each providing its own clock output, and yet all clock output signals of all functioning channels being coherent with one another. One clock functions as a master with the other clocks of the remaining channels slaving themselves to that one clock. In view of a failure of the master, another clock reigns as the master clock to slave the remaining clocks. If the next master clock fails, then still another clock becomes a master to slave the remaining clock or clocks. The clocks are independently powered such that complete failure of one clock, including its power, does not necessarily prevent the other clocks from providing coherent outputs.

Abstract: A process is stated with which ADALINE-type neural networks whose inputs are Boolean variables can be realized using Boolean functions. In addition, a purely digital circuit arrangement for realizing ADALINE-type neural networks is stated. The digital circuit arrangement can be constructed with the aid of a digital base circuit. The digital base circuit generates the set of Boolean functions which replaces a neuron for any value of its input weighting factors. A process for training the circuit arrangement is stated. It is thus possible to realize and to train ADALINE-type neural networks entirely with the aid of purely digital circuit arrangements.