Abstract: A signal receiver includes a first input terminal, a second input terminal, a first transistor, a second transistor and a variable load. The first and the second transistors each include a gate electrode, a first electrode and a second electrode. The gate electrode of the first transistor is coupled to the first input signal terminal, the gate electrode of the second transistor is coupled to the second input signal terminal, and the variable load is coupled to the first electrode of the first transistor, where a resistance of the first variable load is adjusted to make a DC level at an output node of the signal receiver keep a constant value.

Abstract: A novel implementation of a majority gate and a 2-1 MUX by using both gates of FinFET transistors as inputs is presented. A general methodology of using both gates of FinFET as inputs to implement any digital logic circuit is also presented. Circuits implemented using this methodology have significant advantages over CMOS logic counterpart and pass transistor logic counterpart in terms of power consumption and cell area.

Abstract: A system and method for detecting soft-failures in integrated circuits is provided. A circuit includes a combinatorial logic block having a first signal input and a second signal input, and a latch coupled to an output of the combinatorial logic block. The combinatorial logic block produces a pulse when only one of either a first signal provided by the first signal input or a second signal provided by the second signal input is a logical high value, and the latch captures the pulse if the pulse has a pulse width greater than a second threshold. The pulse has a pulse width that is based on a timing difference between a first signal transition on the first signal and a second signal transition on the second signal, the combinatorial logic block produces the pulse if the timing difference is greater than a first threshold, and the combinatorial logic block operates with balanced inputs.

Abstract: Systems and methods of balanced adaptive body bias control. In accordance with a first embodiment of the present invention, a method of balanced adaptive body bias control comprises determining a desirable dynamic condition for circuitry of an integrated circuit. A first dynamic indicator corresponding to the desirable dynamic condition is accessed. Second and third dynamic indicators of the integrated circuit are accessed. A first body biasing voltage is adjusted by an increment so as to change the first dynamic indicator in the direction of the desirable dynamic condition. A second body biasing voltage is adjusted based on a relationship between the second dynamic indicator and the third dynamic indicator.

Abstract: CMOS circuitry having mixed threshold voltages is disclosed. Circuits may be implemented using PMOS transistors, NMOS transistors, or both. For at least one given type of transistor (PMOS or NMOS), a circuit includes at least one transistor configured to switch at a first nominal threshold voltage and at least one transistor configured to switch at a second nominal threshold voltage. The different threshold voltages among a given transistor type are realized by varying the thickness of the transistor gate oxides and/or the channel dopant density, for example.

Abstract: Embodiments of a threshold logic element are provided. Preferably, embodiments of the threshold logic element discussed herein have low leakage power and high performance characteristics. In the preferred embodiment, the threshold logic element is a threshold logic latch (TLL). The TLL is a dynamically operated current-mode threshold logic cell that provides fast and efficient implementation of digital logic functions. The TLL can be operated synchronously or asynchronously and is fully compatible with standard Complementary Metal-Oxide-Semiconductor (CMOS) technology.

Abstract: A novel implementation of a majority gate and a 2-1 MUX by using both gates of FinFET transistors as inputs is presented. A general methodology of using both gates of FinFET as inputs to implement any digital logic circuit is also presented. Circuits implemented using this methodology have significant advantages over CMOS logic counterpart and pass transistor logic counterpart in terms of power consumption and cell area.

Abstract: A method and an apparatus for obtaining an equivalent circuit model of a multi-layer circuit are disclosed. The method includes simulating the multi-layer circuit using an electromagnetic field analysis to provide a coupling network; and simplifying the coupling network using a circuit model order reduction method to generate the equivalent circuit model. The method is very simple to implement and the equivalent circuit model obtained has an apparent physical meaning.

Abstract: A majority voter circuit is configured to generate a selecting signal based on first input data and inverted first input data. The first input data and the inverted first input data each include an odd-number of bits, and the odd-number of bits include bits of a first type and bits of a second type. The generated selecting signal is indicative of which of the first type and the second type of bits in the first input data are in the majority.

Abstract: A majority voter circuit is configured to generate a selecting signal based on first input data and inverted first input data. The first input data and the inverted first input data each include an odd-number of bits, and the odd-number of bits include bits of a first type and bits of a second type. The generated selecting signal is indicative of which of the first type and the second type of bits in the first input data are in the majority.

Abstract: A low voltage, low power, wideband quadrature divide-by-three frequency divider using a wideband low voltage, low power differential Muller C element with multiple inputs operates on quadrature input and quadrature output signals. This frequency divider can be used in frequency synthesisers and as quadrature local oscillator generator.

Abstract: A majority voter circuit is configured to generate a selecting signal based on first input data and inverted first input data. The first input data and the inverted first input data each include an odd-number of bits, and the odd-number of bits include bits of a first type and bits of a second type. The generated selecting signal is indicative of which of the first type and the second type of bits in the first input data are in the majority.

Abstract: A method and apparatus for performing majority voting is presented. The method selects pairs of inputs, performs AND and NOR operations on each pair of inputs to determine that each pair of inputs is both high or both low, yielding a quantity of “both high” pairs and a quantity of “both low” pairs, and compares the quantity of “both high” pairs against the quantity of “both low” pairs to determine the majority. The apparatus includes AND gates configured to receive pairs of values and NOR gates configured to receive the same pairs of values, with a connections between all AND gates and connections between all NOR gates. A summation element sums all AND gate outputs and all NOR gate outputs to determine the majority.

Abstract: Apparatus and systems, as well as methods and articles, may operate to provide a majority voter indication using a sense amplifier coupled to a first plurality of bit inputs and to a second plurality of bit inputs.

Abstract: A process variation detector includes a pulse-signal generating unit that generates a pulse signal having a pulse width corresponding to a characteristic of a process variation in an integrated circuit based on a clock signal; and an output unit that generates a predetermined value, when the pulse signal indicates a specific process variation, by using a transistor of which a channel width and a gate length are set to an unbalanced state, and outputs the predetermined value.

Abstract: This invention provides a storage medium on which there is stored a cell library to design a semiconductor integrated circuit to satisfy low power consumption and high speed operation and a design method using the cell library. The cell library is registered with at least two kinds of cells which are different in delay and power consumption while having the same function and the same shape. To satisfy the specification of the semiconductor integrated circuit, one cell is selected from at least two kinds of cells of the cell library.

Abstract: A bi-directional high speed video data transmission system. A transmitter transmits an encoded video data stream across a data pair to a receiver by switching a DC current, via a pair of transistors, across the two data lines comprising the data pair. As the current varies on the data lines, so too does the voltage. The receiver decodes the serial video data stream back into its component parts so that the video data may be displayed by an appropriate display device. A pair of summing resistors adds the AC currents seen across the data lines to reconstruct the original DC current as a DC return current. The DC return current may be used to drive a return transmitter located on the original receiving side in order to send video data to the original transmitting side of the bi-directional video data transmission system.

Abstract: An input buffer circuit includes front stage circuits and a succeeding stage circuit. Each of the front stage circuits has a logic threshold voltage different from each other. The succeeding stage circuit has a P type MOS transistor and an N type MOS transistor connected in series. The succeeding circuit includes inputs connected to the front stage circuit. A logic threshold voltage of the succeeding stage circuit is set to be between the respective logic threshold voltages of the front stage circuits.

Abstract: In a standard cell, rise time when an output transitions from a low-level voltage to a high-level voltage and fall time when an output transitions from the high-level voltage to the low-level voltage differ from each other. A flip-flop outputs a first input signal, which is input in a cycle immediately before a clock in synchronization with one of rise and fall of the clock, to the standard cell and then fixes an output the signal at one of a high-level voltage and a low-level voltage. Before a second input signal, which is output from the flip-flop after the first input signal, reaches the standard cell, an output of the standard cell is set at one of a high-level voltage and a low-level voltage, which corresponds to a signal whose transition speed is slow, by one of the high-level voltage and the low-level voltage that is output from the flip-flop.

Abstract: A method for multi-threshold voltage CMOS process optimization. The method includes the steps of: providing a semiconductor substrate with a plurality of devices of different threshold voltages; establishing a plurality of types of timing models for a timing calculation; obtaining a static timing analysis report through the timing calculation; defining a large and a small setup time margin as a Tl and a Ts; changing the devices whose setup time margins are less than Ts to low threshold devices; changing the devices whose setup time margins are greater than Tl to high threshold devices; checking a setup time of each device; changing the devices whose setup time margin does not meet the enhanced static timing analysis report; performing a first pocket implant process for the normal threshold devices; performing a second pocket implant process for the low threshold devices and performing a third pocket implant process for the high threshold devices.

Abstract: An information processing structure is disclosed that is formed of single electron circuits each operating rapidly and stably by way of a single electron operation. The information processing structure includes a MOSFET (11), and a plurality of quantum dots (13) disposed immediately above a gate electrode (12) of the MOSFET and each of which is made of a microconductor or microsemiconductor of a nanometer scale in size. Between each of the quantum dots and the gate electrode is there formed an energy barrier that an electron is capable of directly tunneling. The total number of such electrons moved between the quantum dots and the gate electrode is used to represent information. In the structure, a power source electrode (14) is disposed in contact with the quantum dots and a pair of information electrodes (15) is disposed across a quantum dot in contact therewith for having electric potentials applied thereto, representing data of information.

Abstract: A semiconductor integrated circuit that is well-balanced between increased operating speed and decreased power consumption caused by a leakage current. The gate cells of the circuit comprised of low threshold voltage MOSs are used for logic gates provided with three or more inputs, and gate cells comprised of high threshold voltage MOSs are generally used for logic gates provided with one or two inputs, sometimes on a case-by-case basis.

Abstract: A semiconductor integrated circuit of the present invention includes MOSFETs of at least one of N channel- and P channel-types where at least two MOSFETs included in a plurality of MOSFETs, which are provided in a channel between a high potential power line and a low potential power line, includes two serially-connected MOSFETs of the same channel-type in which their respective gates are connected to each other.

Abstract: An input buffer circuit includes front stage circuits and a succeeding stage circuit. Each of the front stage circuits has a logic threshold voltage different from each other. The succeeding stage circuit has a P type MOS transistor and an N type MOS transistor connected in series. The succeeding circuit includes inputs connected to the front stage circuit. A logic threshold voltage of the succeeding stage circuit is set to be between the respective logic threshold voltages of the front stage circuits.

Abstract: A neuron circuit that can be served as a building block for a neural network implemented in an integrated circuit is disclosed. The neuron circuit includes a synapse circuit block and a neuron body circuit block. The synapse circuit block has three transistors, and the body of one of the three transistors is controlled by a weighted input. The neuron body circuit block includes a current mirror circuit, a summing circuit, and an invertor circuit. The neuron body circuit is coupled to the synapse circuit block to generate an output pulse.

Abstract: An adaptive threshold logic circuit is provided in which the switching threshold levels of the logic circuit are automatically changed to accommodate variations in the level of applied data signals to the switching circuit. A detector stage detects the voltage level of the incoming data signals and selectively adjusts the threshold level of a threshold adaptor stage in accordance with the output of the detector stage. The threshold adaptor stage is essentially an adaptive CMOS inverter having various switching paths turned on or off in accordance with the output of the detector stage.

Abstract: A one-hot Muller C-element, wherein an event received on each of a plurality of inputs results in an event being output, can be implemented with complementary inputs and a true transistor pair comprising one transistor having a gate coupled to a first true input and another transistor having a gate coupled to a second true input; a true arm comprising the true transistor pair, coupled in series between a complement output and ground, and a true pull-up transistor, coupled between the complement output and a source; a true arm pull-up logic gate, coupled at its inputs to complement input wires of the one-hot Muller C-element and coupled at its output to a gate of the true pull-up transistor; a complement transistor pair comprising one transistor having a gate coupled to a first complement input and another transistor having a gate coupled to a second complement input; a complement arm comprising the complement transistor pair, coupled in series between a true output and ground, and a complement pull-up transis

Abstract: A neuron circuit that can be served as a building block for a neural network implemented in an integrated circuit is disclosed. The neuron circuit includes a synapse circuit block and a neuron body circuit block. The synapse circuit block has three transistors, and the body of one of the three transistors is controlled by a weighted input. The neuron body circuit block includes a current mirror circuit, a summing circuit, and an invertor circuit. The neuron body circuit is coupled to the synapse circuit block to generate an output pulse.

Abstract: In a semiconductor integral circuit having a transistor or an inverter, a leak current of the transistor or a through current of the inverter, respectively, or the like is reduced. The semiconductor integral circuit has an analog circuit which changes linearly the voltage of an input signal and causes the amount of a current flowing through the analog circuit to change in accordance with the change in the voltage of the input signal. The semiconductor integral circuit also has a logic circuit to which an input signal having a first or second voltage is input. This logic circuit outputs an output signal having the first or second voltage in response to the first or second voltage of the input signal. The absolute value of the threshold value of the MOS transistor of the analog circuit is set smaller than the absolute value of the threshold value of the MOS transistor of the logic circuit.

Abstract: A logic circuit implementing a logic function and method of manufacture thereof. The logic circuit includes a series connection of two or more CMOS devices, at least one CMOS device having a threshold voltage at an input lower than a threshold voltage at an input of another of the CMOS devices. The CMOS logic circuit exhibits enhanced switching speed for logic operations and reduced leakage current when operating in an off-state. A logic family is built around the series connection of two or more devices having mixed voltage threshold inputs for enhanced switching speed and reduced off-current leakage.

Abstract: A semiconductor driver circuit includes a first inverter circuit that inverts an input voltage and supplies a first inverted voltage, and a second inverter circuit that inverts the first inverted voltage and outputs a second inverted voltage. The second inverter circuit includes a first conduction type transistor, such as a PMOS transistor, and a second conduction type transistor, different from the first conduction type transistor, such as an NMOS transistor. The driver circuit further includes a substrate voltage supply circuit that supplies voltages to the substrate of the first conduction type transistor and the substrate of the second conduction type transistor, respectively, according to the second inverted voltage, and a substrate voltage control circuit that adjusts the substrate voltages applied to either or both of the first and second conduction type transistors, according to the second inverted voltage, in order to lessen the power consumption of the driver circuit.

Abstract: A method and apparatus provides an efficient ratioed digital logic structure. The digital logic structure includes ratioed pull-up transistors and pull-down transistors such that the circuit noise margin does not substantially affect gain performance of the ratio stage. In one particular embodiment, a ratioed logic structure includes PMOS transistors and NMOS transistors that receive input voltage signals wherein a current path is induced in the NMOS transistors when a voltage input of zero or less is applied. Another feature of the present invention allows modification of gain performance of the ratio stage by arranging different ratios of the PMOS-to-NMOS transistor channel widths.

Abstract: A majority circuit comprises CMOS circuits is adapted to prevent operation errors due to disagreement of conductance among the transistors of the circuits. Such a majority circuit can realize a large fan in.

Abstract: A logical circuit device has a MOS transistor having a source region, a drain region, a channel region defined between the source region and the drain region, and a gate electrode formed above the channel region, respectively formed on a semiconductor substrate. The amplitude of a voltage applied to the gate electrode necessary for making the channel region conductive is not level throughout the channel region in the width direction. Using such a logical circuit device, flip-flop circuits and storage circuits of a multivalued logic type can be realized.

Abstract: A threshold element enabling a logical operation with fewer transistors and easy design and setting of an element weight and a threshold value is provided. In a threshold element of the present invention, MIS (Metal Insulator Semiconductor) transistors each passing a drain current upon excitation corresponding to weight &ohgr;i of input Xi obtained from a logical expression Y=Sign(&Sgr;&ohgr;iXi−1) derived from Y=F(Xi) thereof are connected in parallel. A terminal for transmitting an input signal Xi corresponding to each of the transistors is connected to the gate electrode thereof. By this input signal, excitation of each of the transistors is controlled. An output voltage based on a sum of the drain currents from the transistors is compared with a threshold value by a comparing inverter, and a comparison result is output.

Abstract: A diode device with a low or negligible threshold voltage includes at least one field effect transistor, the gate of the field effect transistor being connected to the drain of the field effect transistor. The threshold voltage of the diode device is approximately of the same magnitude as the potential of the gate of the field effect transistor forming part of the diode device.

Abstract: The threshold value logic has a non-inverting circuit path (S) that and an inverting circuit path (S') are connected to at least one comparative weighting subcircuit (BC, BS). The non-inverting circuit path and the inverting circuit path preferably are of identical construction and each contain at least one neuron transistor (NT1, NT1'). The corresponding neuron transistor gates in the non-inverting circuit path and in the inverting circuit path are driven inversely with respect to one another.

Abstract: The present invention relates to a buffer for logic signals including a MOS output transistor of a first conductivity type connected by its source to a first supply potential, the drain of this transistor forming an output terminal of the buffer; a control transistor for controlling the output transistor connected between the gate of the output transistor and a second supply potential; a third transistor of the first conductivity type connected between the gate of the output transistor and the first supply potential and controlled to maintain the gate-source voltage of the buffer close to a threshold voltage so that the output transistor operates as a current generator; and a fourth transistor connected to render floating the gate of the third transistor when the potential on the output terminal is close to the first supply potential.

Abstract: According to the present invention, various logic circuits, AD converters, DA converters and counter circuits can be constituted with a small number of transistors by employing a capacitive coupling circuit.

Abstract: An asynchronous register with embedded acknowledge collection is disclosed. The asynchronous register includes a data threshold circuit for generating data or NULL values at an output signal line based upon an evaluation of at least one data input value and an acknowledgment collection circuit, embedded in the data threshold circuit, for collecting a plurality of acknowledge signals and resolving the acknowledge signals for controlling, in combination with the at least one data input value, the passing of the data or NULL values to the output signal line. The acknowledgment collection circuit includes an M of N acknowledge collection circuit, wherein N is an integer representing the number of acknowledge signals being resolved and M representing a threshold, wherein M.ltoreq.N.

Abstract: A threshold logic circuit with a low space requirement includes a first and at least one second circuit portion, each of which has an evaluator circuit and at least two branches to be evaluated. A partial sum signal formed in the first circuit portion is jointly used for the at least one second circuit portion and is not formed separately in each case. The main advantage is a low chip area consumption.

Abstract: A programmable gate array is disclosed for implementing asynchronous logic. In one embodiment, the array includes a set of cells, at least one of which includes a threshold gate having a plurality of inputs, an output, and a threshold value. Signals may assume an ASSERTED state having a logic meaning and a NULL state that has no logic meaning. The gate output switches to NULL when all inputs are NULL, and switches to the ASSERTED state when the number of ASSERTED inputs exceeds the threshold value. In the preferred embodiment, the gate exhibits hysteresis such that the output remains ASSERTED while the number of ASSERTED inputs remains greater than zero, and less than the threshold value. In an alternate embodiment, an array of simplified threshold elements is used to form more complex threshold gates.

Abstract: A defined zero point voltage (V.sub.0), dependent on a settable zero point voltage target value (V.sub.0,soll), is enabled in amplifier stages (1 . . . k) with neuron MOS transistors (T10,1 . . . T10,k). This is generally required because, for example, due to a process-caused charging of the floating gates of the neuron MOS transistors, and due to a capacitively coupled-in voltage from the channel region, an undefined zero point displacement of the transmission characteristic curve results. The devices can be used together with the amplifier stages, e.g. in video and audio technology, in sensor technology, in analog computers, in fuzzy circuits and in neural networks.

Abstract: An integrated circuit includes a plurality of MOSFETs on a substrate. The plurality of MOSFETs preferably includes at least one MOSFET having a first conductivity type and at least one MOSFET having a second conductivity type. Each MOSFET has an initial threshold voltage. The integrated circuit also preferably includes first and second biasing circuits which selectively bias only a selected well a corresponding conductivity type of the plurality of MOSFETs to produce an absolute value of an effective threshold voltage of only the selected MOSFET which is lower than an absolute value of the initial threshold voltage thereof and thereby inhibit a high standby current for the integrated circuit. Method aspects of the invention are also disclosed.

Abstract: The present invention provides a novel circuitry comprising a series connection of a plurality of invertor gates, each of which has field effect transistors, wherein at least one of the field effect transistors has a back bias control terminal; and a various bias voltage generator being capable of generating at least one bias voltage and also capable of varying the at least one bias voltage individually, the various bias voltage generator being also electrically connected to the back bias control terminal of the at least one of the field effect transistors for applying the at least one bias voltage to the back bias control terminal so that the various bias voltage generator is operated to individually vary the at least one bias voltage thereby to individually vary a threshold voltage of the at least one of the field effect transistors.

Abstract: To judge whether or not the number of high-level bits among N (N.ltoreq.2) bits of an input signal is greater than a predetermined number M (1.ltoreq.M<N), a judging circuit has a differential amplifier, N primary MISFETs, M secondary MISFETs, and primary and secondary resistors having the same resistance. Sources of the primary MISFETs are connected to the ground in common. Drains of the primary MISFETs are connected to one end of the primary resistor in common. The other end of the primary resistor is supplied with a power-supply voltage. Gates of the primary MISFETs are supplied with the N bits, respectively. The primary MISFETs have on-currents, respectively, which are equal to one another. An inverted input terminal of the amplifier is connected to the above-mentioned one end of the primary resistor. Sources of the secondary MISFETs are connected to the ground in common. Drains of the secondary MISFETs are connected to one end of the-secondary resistor in common.

Abstract: A NULL convention logic bus includes: a plurality of bus transmission lines; a plurality of NULL convention transmitter ports; and a plurality of NULL convention receiver ports. Each NULL convention transmitter port propagates alternating wavefronts of data an NULL across the bus transmission lines to a NULL convention receiver port. A pipeline bus includes NULL convention storage registers at the transmitter ports. A FIFO pipeline bus includes NULL convention storage registers at the receiver ports.

Abstract: A NULL convention threshold gate receives a plurality of inputs, each having an asserted state and a NULL state. The threshold gate switches its output to an asserted state when the number of asserted inputs exceeds a threshold number. The threshold gate switches its output to the NULL state only after all inputs have returned to NULL. Signal states may be implemented as distinct current levels.

Abstract: An integrated circuit having a plurality of interdependent differential pairs of CMOS transistors emulates the functional characteristics of a biological neuron. The gate voltage of a first one of each pair of transistors is settable to a threshold value corresponding to an activation threshold of an ion channel in the biological neuron and the gate of a second one of each pair of transistors is representative of an incoming membrane potential, ligand concentration or ion concentration of the biological neuron. Each differential pair of CMOS transistors provides a sigmoidal output representative of an ionic conductance across a neuron membrane when the gate voltage of the second transistor exceeds the threshold value set by the gate voltage of the first transistor.

Abstract: A NULL convention threshold gate receives a plurality of inputs, each having an asserted state and a NULL state. The threshold gate switches its output to an asserted state when the number of asserted inputs exceeds a threshold number. The threshold gate switches its output to the NULL state only after all inputs have returned to NULL. Signal states may be implemented as distinct current levels.