Abstract: The logic circuit includes an input terminal, an output terminal, a main logic circuit portion that is electrically connected to the input terminal and the output terminal, and a switching element electrically connected to the input terminal and the main logic circuit portion. Further, a first terminal of the switching element is electrically connected to the input terminal, a second terminal of the switching element is electrically connected to a gate of at least one transistor included in the main logic circuit portion, and the switching element is a transistor in which a leakage current in an off state per micrometer of channel width is lower than or equal to 1×10?17 A.

Abstract: An input/output circuit implemented in an integrated circuit is described. The input/output circuit comprises an input/output pad and a voltage control circuit coupled to the input/output pad. The voltage control circuit sets a voltage at the input/output pad at a first voltage when the input/output pad is implemented as an input pad and at a second voltage when the input/output pad is implemented as an output pad. Methods of implementing input/output circuits in an integrated circuit are also described.

Abstract: Method and apparatus for programmable heterogeneous integration of stacked semiconductor die are described. In some examples, a semiconductor device includes a first integrated circuit (IC) die including through-die vias (TDVs); a second IC die vertically stacked with the first IC die, the second IC die including inter-die contacts electrically coupled to the TDVs; the first IC die including heterogeneous power supplies and a mask-programmable interconnect, the mask-programmable interconnect mask-programmed to electrically couple a plurality of the heterogeneous power supplies to the TDVs; and the second IC die including active circuitry, coupled to the inter-die contacts, configured to operate using the plurality of heterogeneous power supplies provided by the TDVs.

Abstract: A semiconductor integrated circuit device includes cells A-1, B-1, and C-1 that have the same logic. Cell B-1 has cell width W2 larger than a cell width of cell A-1, but gate length L1 of a MOS transistor is equal to that of cell A-1. Cell C-1 has cell width W2 equal to a cell width of cell B-1, but has a MOS transistor having large gate length L2. A circuit delay of cell C-1 becomes large as compared with that of cells A-1 and B-1, but leak current becomes small. Therefore, by replacing cell A-1 adjacent to a space area with cell B-1, and by replacing cell B-1 in a path having room in timing with cell C-1, for example, leak current can be suppressed without increasing a chip area.

Abstract: A convertible logic circuit includes a plurality of carbon nanotube transistors. Each carbon nanotube transistors are configurable as p-type or an n-type transistors according to a voltage of a power source voltage. Each carbon nanotube transistor includes a source electrode, a drain electrode, a channel formed of a carbon nanotube between the source electrode and the drain electrode, a gate insulating layer formed on the carbon nanotubes, and a gate electrode formed on the gate insulating layer.

Abstract: A method and apparatus of providing a programmable system using non-volatile programmable transistors are disclosed. A programmable logic circuit, in one embodiment, includes a first programmable transistor and a second programmable transistor. The first programmable transistor includes a first gate terminal, a first source terminal, a first drain terminal, and a first programming terminal. The second programmable transistor includes a second gate terminal, a second source terminal, and a second drain terminal, and a second programmable terminal. The first and second programmable transistors include non-volatile memory elements. The first and the second gate terminals are coupled to an input terminal, and the first drain terminal and the second source terminal are coupled to an output terminal to perform a logic function.

Abstract: A programmable logic device architecture having logic elements with dedicated hardware to configure the look up tables of the logic element to either perform logic functions or to operate as a register for pipelining or other purposes. The programmable logic device includes a general interconnect and a plurality of logic array blocks interconnected by the general interconnect. Each of the plurality of logic blocks further includes one or more logic elements. The logic elements each include a first look up table, a second look up table, and dedicated hardware within the logic element to configure the first look table and the second look up table as a register without having to use the general interconnect. In one embodiment, the dedicated hardware includes a plurality of dedicated interconnects within the logic element to configure the two look up tables as a pair of cross coupled muxes or latches when configured as a register.

Abstract: A packaged PLD solution includes a first die having a masked-Read Only Memory (ROM) that is programmed during its fabrication to store configuration data, and includes a second die having a PLD including a number of configurable resources collectively configured to implement a circuit design embodied by the configuration data. The first die is electrically connected to the second die, and both the first die and second die are stacked and encapsulated together to form the packaged PLD solution. The configuration data is programmed into the masked-ROM by a manufacturer of both the masked-ROM and the PLD.

Abstract: An output driver for use in a semiconductor memory device includes a pull-up metal oxide semiconductor (MOS) transistor for pulling-up a voltage loaded on an output node in response to a pull-up control signal; a pull-up linear element connected between the pull-up MOS transistor and the output node for increasing a linearity of an output current; a pull-down MOS transistor for pulling-down the voltage loaded on the output node in response to a pull-down control signal; and a pull-down linear element connected between the pull-down MOS transistor and the output node for increasing the linearity of the output current, wherein the pull-up MOS transistor and the pull-up linear element are different typed MOS transistors and the pull-down MOS transistor and the pull-down linear element are different typed MOS transistors.

Abstract: A dynamic circuit latch, having the functionality of a domino circuit and a transparent latch, without the delay associated with the inclusion of a separate series latch element. Embodiments include a fast scannable footed Domino dyanmic latch. Also described is a fast scannable delay reset Domino dynamic latch. A fast scannable compound Domino dynamic latch is also described.

Abstract: A convertible logic circuit includes a plurality of carbon nanotube transistors. Each carbon nanotube transistors are configurable as p-type or an n-type transistors according to a voltage of a power source voltage. Each carbon nanotube transistor includes a source electrode, a drain electrode, a channel formed of a carbon nanotube between the source electrode and the drain electrode, a gate insulating layer formed on the carbon nanotubes, and a gate electrode formed on the gate insulating layer.

Abstract: Methods and circuitry for reducing ground bounce and VCC sag effects in integrated circuit (“IC”) devices is provided. In particular, a via-programmable design for I/O circuitry in IC devices is provided. The via-programmable I/O circuitry is used to disconnect I/O pin driver circuitry from and create a substantially direct connection between unused I/O pins and the ground and/or VCC signals of an IC device to reduce ground bounce and VCC sag, respectively.

Abstract: Line load compensation and reflection reduction in a signal transmitting circuit is provided using feedback capacitors. The feedback capacitor serially coupled with a resistance generates an RC rise/fall time that is independent of the line load. Additionally, by selecting a capacitor that yields a rise/fall time of approximately ? of the maximum bit transmission time, signal reflection on the signal line can be reduced. Accordingly, by incorporating the feedback capacitor with a differential drive circuit, such as the IB 485 driver, variations in line load can be compensated for while also reducing signal reflection due to un-terminated or improperly terminated signal lines, thus allowing a free topology implementation.

Abstract: A universal logic module that may have a reduced off-leak current in universal logic cells (100) not used as logic circuits has been disclosed. A universal logic module may include universal logic cells (100) that may be formed with a second wiring for connecting universal logic cells (100) from a base configuration formed with a first wiring. Unused universal logic cell (100) may include transistors in basic cells (A to E) that are non-connected to a power supply (VDD) and/or a ground potential (VSS). Furthermore, unused universal logic cell (100) may include transistors in basic cells (A to E) that may provide a capacitor between a power supply (VDD) and a ground potential (VSS). In this way, off-leak current may be reduced and noise on a power line and/or a ground line may be reduced.

Abstract: A method and system for reducing power consumption in digital circuits using charge redistribution, comprising a plurality of signal lines, an intermediate floating virtual source/sink, and a charge redistribution circuit connected to each said signal line that isolates said line from its source and connects it to the intermediate floating virtual source/sink during an idle period prior to a change of state.

Abstract: A programmable input/output buffer has a first plurality of pull-down transistors connected between a supply voltage and an electrical system conductor on the integrated circuit and a second plurality of pull-down transistors connected between the electrical conductor and the system reference voltage. Reference circuits generate signals to turn on a first number of said first plurality of pull-up transistors and/or a second number of said second plurality of pull-down transistors to provide an input/output buffer impedance matching the impedance of the external transmission line either sending a signal to the programmable input/output buffer or receiving a signal from the programmable input/output buffer.

Abstract: A Variable Grain Architecture is disclosed wherein Variable Grain Blocks (VGB's) are wedged together in mirror opposition to one another to define super-VGB structures. The super-VGB structures are arranged as a matrix within an FPGA device. Each VGB includes progressive function synthesizing layers for forming more complex function signals by folding together less complex function signals of preceding layers. A function spawning layer containing a set of function spawning lookup tables (LUT's) is provided near the periphery of the corresponding super-VGB structure. In one case, the function spawning layer is L-shaped and includes a symmetrical distribution of Configurable Building Blocks. A signal-acquiring layer interfaces with adjacent interconnect lines to acquire input terms for the LUT's and controls. A decoding layer is interposed between the signal-acquiring layer and the function spawning layer for providing strapping and intercept functions.

Abstract: A universal logic module that may have a reduced off-leak current in universal logic cells (100) not used as logic circuits has been disclosed. A universal logic module may include universal logic cells (100) that may be formed with a second wiring for connecting universal logic cells (100) from a base configuration formed with a first wiring. Unused universal logic cell (100) may include transistors in basic cells (A to E) that are non-connected to a power supply (VDD) and/or a ground potential (VSS). Furthermore, unused universal logic cell (100) may include transistors in basic cells (A to E) that may provide a capacitor between a power supply (VDD) and a ground potential (VSS). In this way, off-leak current may be reduced and noise on a power line and/or a ground line may be reduced.

Abstract: An amplifier includes differential input transistors, first switches arranged between each gates and source of the differential input transistors, a second switch arranged to turn on/off a current source that gives the bias of the differential input transistors, and a drive circuit arranged to turn off the second switch and turns on the first switches when the current of the current source is not supplied to the differential input transistors.

Abstract: Logic array circuits are formed on SOI substrates. The pull-down network (130) of the logic array circuit comprises NMOS transistors (125) and PMOS transistors (120) configured in series.

Abstract: Described are systems for producing differential logic signals and circuits for biasing the voltages of the differential logic signals. These systems can be adapted for use with different loads by programming one or more programmable elements. One embodiment includes a series of driver stages, the outputs of which are connected to one another. The driver stages turn on successively to provide increasingly powerful differential amplification. This progressive increase in amplification produces a corresponding progressive decrease in output resistance, which reduces the noise associated with signal reflection. The systems can be incorporated into programmable IOBs to enable PLDs to provide differential output signals.

Abstract: An arrangement for improving the ESD protection in a CMOS buffer includes a plurality of PMOS transistors (31 to 37) and a plurality of NMOS transistors (41-47) which are connected in series with the PMOS transistors and have a finger width WN which is larger than the finger width WP of the PMOS transistors in order to be capable of withstanding an increased current load in the case of an electrostatic discharge.

Abstract: Zero-power logic cells are implemented in CMOS technology for forming part of programmable logic devices with minimized static power dissipation. The zero-power logic cells are implemented with stacked P-channel and N-channel field effect transistors. The respective gate of each of such P-channel and N-channel transistors are coupled to one of a first input signal, a second input signal, an output of a first memory cell, or an output of a second memory cell. The output node of the logic cell is one of a logic cell input signal, a complement of the logic cell input signal, the logical high state, or the logical low state depending on the outputs of the memory cells in a functional mode. In addition, such zero-power logic cells may be used to verify the respective output of each of the first and second memory cells in a verify mode.

Abstract: A digital electronic circuit having first and second sections. The first section is adapted to transmit one of N input signals. The second section is adapted to receive the signal transmitted by the first section and one or more control signals. The second section is configured to output either an inverse of the signal transmitted by the first section or a logical 0, or to output either an inverse of the signal transmitted by the first section or a logical 1. The second section also may be selectively configurable.

Abstract: A configuration for voltage buffering in dynamic memories based on CMOS technology uses the capacitance of a well structure for buffering the amplified word line voltage or the negative word line reverse voltage.

Abstract: Antenna size of conductive members is calculated with respect to an area of a gate oxide film of a transistor using an expression which approximates an actual relationship of changes therein, not using a simple proportional relationship. As a result, in design of a structure having conductive members connected to a gate oxide film of a transistor, it is possible to properly calculate an antenna size such as wire length of the conductive members with respect to an area of the gate oxide film.

Abstract: A programmable input/output circuit for a programmable logic device input/output pin can be configured in a standard I/O mode, or in a reference voltage mode. The circuit includes a tristatable, but otherwise standard I/O buffer as well as a reference voltage clamp circuit. In reference voltage mode, the I/O circuit is tristated, and the reference voltage clamp circuit passes a reference voltage from the I/O pin to a reference voltage bus. In standard I/O mode, the I/O buffer is operational. The reference voltage clamp circuit isolates the I/O pin from the reference voltage bus and may include undervoltage and overvoltage protection to prevent disturbance of the reference voltage bus by an out-of-range I/O signal.

Abstract: A digital electronic circuit having first and second sections. The first section is adapted to transmit one of N input signals. The second section is adapted to receive the signal transmitted by the first section and one or more control signals. The second section is configured to output either an inverse of the signal transmitted by the first section or a logical 0, or to output either an inverse of the signal transmitted by the first section or a logical 1. The second section also may be selectively configurable.

Abstract: Reduction of standby leakage current in an internal circuit block using a transistor stack effect. For one embodiment, an apparatus includes a standby leakage reduction circuit to be coupled to the circuit block including a plurality of logic gates. The standby leakage reduction circuit causes a stack effect at each of the plurality of logic gates during a standby mode of the circuit block by turning off two or more series-coupled transistors of a same type (either n-type or p-type) at each of the plurality of logic gates.

Abstract: A programmable circuit is provided. The programmable circuit includes a programmable inverter circuit (PIC) that is configured to receive an input signal and to generate an output signal. The programmable circuit also includes a teaching circuit that is coupled to the PIC. The teaching circuit is configured to compare the output signal of the PIC to a desired output signal. Responsive to this comparison, the teaching circuit is configured to generate a control signal to the PIC. In response to the control signal the PIC is configured to generate the desired output signal.

Abstract: The present invention provides an input receiver in a differential amplifier or modified differential amplifier configuration which adjusts the input high and low voltage signals compatible with multiple input/output (I/O) interfaces, including transistor-transistor logic (TTL), Low Voltage TTL (LVTTL), and Stub Series Terminated Logic (SSTL) interfaces. Transistors in a differential amplifier or modified differential amplifier configuration that receive a reference.sub.-- voltage signal and receiver.sub.-- enable signal are adjusted in accordance to the input high signal and input low signal requirements for a selected type of interface, while other transistors remain at a relatively constant voltage. Once a particular type of interface has been selected, the gate voltages for the transistors that receive the reference.sub.-- voltage and receiver.sub.-- enable signals remain relatively constant.

Abstract: A dynamic-floating-gate arrangement is used to improve the ESD robustness of driving-current-programmable CMOS output buffers in cell libraries, by suitably dynamically floating the gates of the NMOS/PMOS buffers using a small-dimension CMOS device having its drain connected to the gate of an unused CMOS buffer, its source connected to one of two voltage sources, and its gate connected between a resistance, that is connected between the two voltage sources, and a capacitance connected between the resistance and the same one of the two voltage sources as the source of the small-dimension CMOS device.

Abstract: A programmable input/output (I/O) circuit for transmitting output signals on or receiving input signals from an I/O terminal, the I/O circuit including a pull-up transistor, a gate bias control circuit and a well bias control circuit, all being connected between Vcc and the I/O terminal. The gate bias control circuit connects the gate of the pull-up transistor to the I/O terminal and the well bias control circuit connects the bulk terminal of the pull-up transistor to the I/O terminal when the I/O circuit is in a 5V tolerant input mode. The gate bias control circuit connects the gate of the pull-up transistor to the system voltage source and the well bias control circuit connects the bulk terminal of the pull-up transistor to Vcc when the I/O circuit is in a PCI compliant input mode. In an output mode, the gate bias control circuit and well bias control circuit allow the pull-up transistor to pull up the I/O terminal to Vcc in response to a pull-up data signal.

Abstract: Disclosed herein is a differential CMOS cell that achieves faster switching speeds than conventional CMOS logic by 1) biasing a differential pair of output nodes to a relatively high logic low voltage threshold, and 2) pulling up the differential pair of output nodes to a logic high voltage level. The differential CMOS cell is designed such that the difference between logic low and logic high voltage thresholds is much less than in traditional CMOS circuits (i.e., approximately 0.8 V-1.0 V as compared to 2.6 V). A lower voltage swing allows for fast switching of a differential output signal. In a preferred embodiment, the differential CMOS cell receives a primary differential input signal, and respective first and second secondary differential input signals.

Abstract: A programmable buffer circuit includes a first stage circuit which receives an input signal IN indicative of a first or second value, and a second stage circuit, responsive to an output of the first stage circuit, for outputting one of a value designated depending on the value of the input signal and a value designated regardless of the value of the input signal. The second stage circuit includes a plurality of MOS transistors whose conduction properties change depending on whether ion implantation is applied thereto. By applying the ion implantation selectively to the MOS transistors, the second stage circuit is operated as a transfer logical function circuit or an inverter logical function circuit.

Abstract: A zero power AND or NOR (AND/NOR) gate includes circuitry configured for use in a field programmable gate array (FPGA). The AND/NOR gate includes multiple driver circuits each receiving a single input of the AND/NOR gate, each driver circuit being connected by a NORCNTL line and a NOROUT line to a current switch circuit. The NOROUT line provides the output of the AND/NOR gate, while the NORCNTL line enables zero power operation. The driver circuits can be included in input/output buffers (IOBs), configurable logic blocks (CLBs), or other components throughout an FPGA to receive more inputs than typically provided to a single CLB. Each of the driver circuits includes a pull down transistor having a gate receiving an input signal (IN.sub.1 -IN.sub.N) of the AND/NOR gate, and having a source to drain path connecting the NOROUT line to Vss.

Abstract: Ferroelectric transistors are combined with MOSFETs to perform logic functions. The logic functions include a non-volatile ferroelectric latch (30), a clocked non-volatile ferroelectric latch (50), a programmable switch (60), an edge-triggered complementary flip-flop (78), a tri-state logic circuit (80), a ferroelectric logic NAND-gate (100), a clocked ferroelectric logic NAND-gate (140), and a programmable logic function (150). The programmable logic function (150) includes a programming terminal (156) to select between a NOR-gate function and a NAND-gate function.

Abstract: The present invention provides a logic circuit that is programmable to implement a first logic function or a second logic function using as few as four transistors. In one embodiment, the logic circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a first signal line for receiving a first input signal, a second signal line for receiving a second input signal, a control signal line for receiving a control signal, and an output signal line for receiving an output signal. The first transistor and the second transistor are connected in series between the control signal line and the output signal line. The third transistor is connected in series between the first input signal line and the output signal line. The fourth transistor is connected in series between the second input signal line and the output signal line.

Abstract: In a semiconductor device, wherein capacitors are connected with multi-input terminals Q1 to Qn and one end of each capacitor is commonly connected to a sense amplifier, the semiconductor device comprises either the reset element for resetting the commonly connected capacitor terminals or the reset element which is connected between a capacitor and a switch, which is provided between a capacitor and an input terminal, and a structure in which inverted-phase-signals of the drive signals of the reset elements are input is connected with the same terminals as those of the reset elements, scaling down the circuit, improving the processing, and reducing the power consumption.

Abstract: Two NAND gates are provided corresponding to each of a plurality of pads. By connecting a mode switching pad to power supply potential or ground potential, one of the two NAND gates provided corresponding to each pad is activated, and the other NAND gate is non-activated. As a result, different mode select signals are provided from the output of each NAND gate.

Abstract: Problems associated with excessive crowbar current due to input signal transitions at a buffered programmable interconnect point are solved by inserting a transistor switch between power and ground. The inserted switch is in series with the input buffer and is controlled by a memory cell which also controls the pass/no-pass state of the interconnect. An OFF inserted switch blocks current that flows during switching when the memory cell output causes a no-pass state of the interconnect.

Abstract: A temperature monitor which determines the operating temperature of an integrated circuit chip. The temperature monitor includes a delay line made up of serially connected delay cells. The propagation time of a signal through the delay cells is determined and this value is correlated to a signal representative of chip temperature. Chip temperature values are stored in a memory to produce an operating history of chip temperatures.

Abstract: A fuse-programmable circuit controllably enables or disables an electrical signal (S). The circuit includes a transmission gate (118) connected between the circuit's input and output terminals. The transmission gate is controlled by complimentary outputs OUTH, OUTL of a fuse-programmable latch (130). A PMOS transistor (Q41) and a fuse (F41) are connected in series between the output terminal and a power supply voltage (VCC). An NMOS transistor (Q42) and a fuse (F42) are connected in series between the output terminal and a reference voltage (ground). The gate of the PMOS transistor is connected to the latch output OUTH. The gate of the NMOS transistor is connected to the latch output OUTL. When OUTH is high and OUTL is low, the transmission gate couples the signal (S) from the input terminal to the output terminal. When OUTH is low and OUTL is high, the transmission gate is closed.

Abstract: An input circuit to a semiconductor device may selectively accept different voltage logic levels (e.g., TTL or CMOS) as selected by a preset selection signal. The selection signal activates an N-type or P-type transistor in the input circuit which alters the threshold switching voltage of the input circuit logic. By altering the input threshold voltage, both TTL and CMOS input signals may be correctly triggered. An additional circuitry may be provided to allow a low voltage circuit (e.g., 3.3 Volts) to be tolerant of higher voltage inputs (e.g., 5 Volts). An isolation transistor isolates the input of the circuit from the high voltage signal, while a pulldown transistor pulls a high logic, high voltage signal down to supply voltage level.

Abstract: The invention comprises an FPGA having a plurality of input reference voltages and/or output voltage supplies. In one embodiment, two or more differential amplifiers in the same configurable input buffer use different input reference voltages. According to a second aspect of the invention, the I/O pad line is configurably connected to the input reference voltage line, so that any configurable Input/Output Block (IOB) can be used to supply the input reference voltage. According to a third aspect of the invention, the reference input of an I/O is configurably connected to any of two or more input reference voltage lines.

Abstract: A method for varying the type of function selected on a chip (for example, after completion of manufacturing) may include the steps of providing predetermined fuse arrangements which individually or in combination correspond to each type of function on the chip and providing disable control lines having fuses to each of the predetermined fuse arrangements. When one of the types of circuits is selected, the predetermined fuse arrangement individually or in combination corresponding to that selected type of function is blown. The blowing of fuses may change the functionality of the chip directly or may perform a complex procedure such as controlling a portion of a decoding scheme which may radically change the function of the chip. To prevent further blowing of predetermined fuse arrangements, the fuses in disable control lines to each of the predetermined fuse arrangements may be blown, eliminating further selection of types of function.

Abstract: A gate array architecture adapted for serial multiplexer-based circuits. In one embodiment, the gate array contains base cells having functional but isolated serial multiplexer circuits therein. In another embodiment, a base cell contains a single serial multiplexer circuit divisible into varying-sized (size corresponding to the number of inputs) derivative serial multiplexer circuits. In either embodiment, the serial multiplexer circuits within the base cell may be formed from P- and N-channel transistors of varying size. The transistor sizes are chosen to optimize the efficiency of serial multiplexer-based circuits.

Abstract: A method and circuit are disclosed for changing the output impedance of an impedance controlled buffer from an initial impedance to a final impedance, while minimizing data transmission errors. The buffer has a plurality of impedance control inputs, with each of the plurality of impedance control inputs receiving a corresponding one of a plurality of bits of a binary coded impedance control signal. The output impedance of the buffer is controlled as a function of a value of the impedance control signal. First, the value of the impedance control signal is changed from an initial value corresponding to the initial output impedance to an intermediate value corresponding to an intermediate output impedance which is less than the initial output impedance. Next, the intermediate value of the impedance control signal is changed to a final value corresponding to the final output impedance.

Abstract: In a programmable logic device having a plurality of external pins each of which may be driven by an output drive structure controlled by a programmable logic block, a logic device such as an OR gate or a programmable pull-up or pull-down switch is inserted between the input terminal of the output drive structure and the programmable logic block or other internal logic block which controls the output driver. This inserted structure allows the macrocell to be used for internal logic while the output drive structure is used to stabilize power or ground voltage.

Abstract: A user configurable circuit contains clock logic, a switching element and a data path circuit. Input data is received in the switching element, and the switching element and the data path circuit constitute the entire data path for the circuit. A plurality of user configurable inputs are received to configure the circuit for a particular user application. The clock logic and the switching element implement a logic function that is configurable by the user configurable inputs. The logic function is pre-processed in the clock logic so that minimal delay occurs in the data path. In addition, the propagation delay through the switching element and the register is independent of the user configurable inputs. The user configurable circuit of the present invention has application for use as a macro cell for a programmable logic device permitting the user to configure the circuit as a D-type flip-flop, a T-type flip-flop. In addition, the user selects the polarity for the output circuit.