Abstract: A binary half-adder comprising first and second oscillators, each oscillator being connected to a first input and to a second input, the second oscillator being connected to the first oscillator, wherein the first oscillator is configured to oscillate if the first input is high or the second input is high, the second oscillator is configured to oscillate if the first and the second inputs are high, and wherein the connection between the second oscillator and the first oscillator is configured to suppress oscillation of the first oscillator if the second oscillator is oscillating.

Abstract: A double data rate serial encoder is provided. The serial encoder comprises a mux having a plurality of inputs, a plurality of latches coupled to the inputs of the mux, an enabler to enable the latches to update their data inputs, and a counter to select one of the plurality of inputs of the mux for output. In another aspect, the mux provides a glitch-less output during input transitions. The mux includes an output selection algorithm optimized based on a priori knowledge of an input selection sequence provided by the counter.

Abstract: A binary half-adder comprising first and second oscillators, each oscillator being connected to a first input and to a second input, the second oscillator being connected to the first oscillator, wherein the first oscillator is configured to oscillate if the first input is high or the second input is high, the second oscillator is configured to oscillate if the first and the second inputs are high, and wherein the connection between the second oscillator and the first oscillator is configured to suppress oscillation of the first oscillator if the second oscillator is oscillating.

Abstract: Systems, methods and media for implementing logic in the arithmetic/logic unit of a processor are disclosed. More particularly, hardware is disclosed for computing logical operations with minimal hardware by organizing the execution unit such that the propagate and generate functions required for the adder can be used as a basis to implement the bitwise logical instructions. The result of these functions is computed before execution of the instruction by an execution macro in the arithmetic/logic unit.

Abstract: A fast, flexible carry scheme for use in clustered field programmable gate array architectures is described. Each cluster has a cluster carry input node, a cluster carry output node, a cluster carry output circuit having an output coupled to the cluster carry output node, a first input coupled to the cluster carry input node, and a second input and a plurality of logic modules each comprising a logic function generator circuit coupled to a carry circuit. The logic modules are coupled in a series carry arrangement between the cluster carry input node and the second input of the cluster carry output circuit such that the least significant bit of an arithmetic logic circuit can be programmably placed in any of the logic modules.

Abstract: A logic module for an FPGA includes a LUT formed from an N-level tree of 2:1 multiplexers. Each of the N inputs to the LUT is connected to the select inputs of the multiplexers in one level of the tree. Each of the data inputs at the leaves of the tree is driven by a configuration memory cell that produces either a logic 0 or a logic 1. The output of the single multiplexer at the last level of the tree forms a Y output and is coupled to one input of an XOR gate and to the select input of a two-input carry multiplexer. The 0 input of the carry multiplexer is coupled to a G input. A CI input is coupled to the other input of the XOR gate and to the 1 input of the carry multiplexer.

Abstract: A device for generating k-bit parallel pseudo-random data includes “n” registers, from the first through the n-th registers (“n” is an integer not less than 3), and “k” exclusive-OR gates, from the first through the k-th exclusive-OR gates (“k” is an integer not less than 2). An output of the m-th register is input to the (m+k)th register (“m” is an integer between 1 and (n?k)). Outputs of the first through the (k?1)th exclusive-OR gates are respectively input to the second through the k-th exclusive-OR gates. An output of the first register is input to the first exclusive-OR gate. The outputs of the first through the k-th exclusive-OR gates are respectively input to the k-th through the first registers. Outputs of “k” registers, from the (n?k+1)th through the n-th registers are respectively input to the k-th through the first exclusive-OR gates, and also extracted as the k-bit parallel pseudo-random data.

Abstract: In various embodiments, an adder circuit includes a plurality of transistors, all of the transistors being of a single type selected from the group consisting of NMOS transistors and PMOS transistors, and dissipates no more power than an equivalent CMOS circuit.

Abstract: A fast, flexible carry scheme for use in clustered field programmable gate array architectures is described. Each cluster has a cluster carry input node, a cluster carry output node, a cluster carry output circuit having an output coupled to the cluster carry output node, a first input coupled to the cluster carry input node, and a second input and a plurality of logic modules each comprising a logic function generator circuit coupled to a carry circuit. The logic modules are coupled in a series carry arrangement between the cluster carry input node and the second input of the cluster carry output circuit such that the least significant bit of an arithmetic logic circuit can be programmably placed in any of the logic modules.

Abstract: A method for a mix mode driver to accommodate traces of different lengths includes storing in the mix mode driver a set of one or more control signals and coefficient signals for a trace length. The one or more control signals select a number of the stages to generate a variable amplitude data output signal. Each stage is operable to increase or decrease a data signal, and each of the coefficient signals determines the magnitude of increase or decrease of the data input signal by a stage. A method for operating the mix mode driver includes generating the variable amplitude data output signal with one or more of the stages, and providing the variable amplitude data output signal to a trace.

Abstract: A computational unit is disclosed to increment or decrement n-bits of data. The unit has n/3 logic blocks to process the n-bits of data, each logic block including: first and second multiplexers to propagate a carry chain; and first, second and third exclusive—OR (XOR) circuits coupled to the carry chain of the multiplexers to generate a 3-bit incremented output.

Abstract: A circuit for a parity tree is disclosed. In one embodiment, a circuit for a parity tree includes a pull-up circuit, a pull-down circuit, and a cross-couple circuit. The circuit, an XOR/XNOR circuit, includes both an output node and an inverted output node. For a given set of input signals, a pull-up path exists through the cross-couple circuit for one of the output node and the inverted output node, and wherein a pull-down path exists through the cross-couple circuit for the other one of the output node and the inverted output node.

Abstract: Sum bit generation circuit includes first logic generating first signal as XOR of first and second input signals and second signal as the inverse of XOR of the first and second input signals; second logic receiving the first and second signals generated by first logic and generating an output signal as XOR of first signal and third input signal. Second logic includes at least two pass gates. First gate terminal of the first pass gate receives third input signal. A second gate terminal of the first pass gate receives the inverse of third input signal. First gate terminal of the second pass gate receives the inverse of the third input signal. Second gate terminal of the second pass gate receives the third input signal. Input terminals of the first and second pass gates receive the first signal and the second signal respectively. Pass gate output terminals generate the output signal.

Abstract: Each binary carry logic circuit 20 of half adder circuits other than that for the least significant digit comprises a transfer gate 212 turned on when an input bit A2 is active and receiving a carry-in bit *C2 at its data input, and a transistor 23, turned on when the input bit A2 is inactive, connected between a power supply potential VDD and the data output of the transfer gate 212 a signal on which is a carry-out bit *C3. Transfer gates 212 to 214 of binary carry logic circuits other than that for the least significant digit are connected in chain, and are simultaneously on/off controlled by input bits A2 to A4, letting the carry-in bit *C2 from the least significant digit propagate through the transfer gate chain at a high speed.

Abstract: A logic circuit capable of suppressing occurrence of wraparound of signals, capable of reducing power consumption, and in addition achieving a reduction of a circuit scale and an improvement of an operating speed and a full adder using the same, wherein provision is made of an exclusive-OR generation circuit 12 for receiving a first logic signal A and a second logic signal B taking a logic “1” or “0” and generating the exclusive-OR of the first logic signal A and the second logic signal B, a dual signal generation circuit 11 for receiving the first logic signal A and the second logic signal B and generating the dual signal of the exclusive-OR of the first logic signal A and the second logic signal B, and an interpolation circuit 13 for compulsorily setting the output level of the dual signal at the level of the logic “1” when the output level of the exclusive-OR is the logic “0”, while compulsorily setting the output level of the exclusive-OR at the level of the

Abstract: Methods and circuits for selectively latching the output of an adder are disclosed. One such circuit includes first and second NAND gates, each of which has an input coupled to a clock signal. The outputs of the NAND gates are coupled to a multiplexer. A set dominant latch is coupled to the clock signal and an output of the multiplexer.

Abstract: A method and apparatus for searching a parent code sequence for a target code sequence. In various embodiments, a first circuit arrangement selects and stores subsets of codes of the parent code sequence. A matching circuit determines in parallel matches between the subset of codes and the target code sequence, and provides a programmed binary value for each match. The binary values provided by the matching circuit are summed in a pipelined fashion.

Abstract: In accordance with the present invention, an adder tree structure includes at least two adder stages. In the circuit and method according to the present invention, the first of the two adder stages generates two bits of a common weight and other more significant bits of a weight one bit more significant than the two bits of the common weight. The second of the two adder stages includes an adder that receives the more significant bits generated in the first of the two adder stages. The second adder stage also includes an AND gate which receives and logically AND's the two bits of the common weight to generate a carry-in bit for the adder in the second stage. The above adder tree structure and adding method have an advantage of permitting more input terminals of adders to contain information about the input values to the adder tree structure. Therefore, the adders are used more efficiently and less adders are required to perform a specific function.

Abstract: In the design of an integrated circuit for comparing serial data signals, the number of transistor elements can be reduced by implementing the comparison gate (12) based on the associated truth table rather than by using a general comparison gate component. Using this method, an exclusive OR gate (22) can be implemented using two transistor elements (221, 222), an exclusive NOR gate (52) can be implemented using two transistor elements (521, 522), an AND gate (62) can be implemented using a single transistor element (621), and an OR gate (72) can be implemented using a single transistor element (721). The reduced number of elements used to implement the comparison gates can provide a transistor element saving in the associated circuit.

Abstract: A high speed, low power 3-2 adder (300, 500) with latchable outputs comprises a most significant bit (MSB) adder circuit (100) and a least significant bit (LSB) adder circuit (200). MSB adder circuit (100) includes three differential data inputs (A1, B1, and C1), a latch enable input (LE1), three separate bias points, and an MSB output. In addition the LSB adder circuit includes three differential data inputs (A2, B2, and C2), a latch enable input (LE2), three separate bias points and a LSB output. Internal latch circuits (172, 272) and latch enable circuits (174, 274) are provided in each adder stage. Internal latch enable inputs are connected in parallel in one configuration. Separate latch enable inputs are provide in a second configuration. Separate bias points are also provided in each adder stage.

Abstract: A threshold logic circuit with a low space requirement includes a first and at least one second circuit portion, each of which has an evaluator circuit and at least two branches to be evaluated. A partial sum signal formed in the first circuit portion is jointly used for the at least one second circuit portion and is not formed separately in each case. The main advantage is a low chip area consumption.

Abstract: The present invention relates to multi-bit exclusive-or (XOR) gates (60), including those where N parallel input bits (36, 38) are XORed with one data input bit (52). A modular approach is made using only one basic cell (30) for various implementations with different propagation delays. An N-bit XOR comprises basic cells (30) of adjacent first and second XOR gates (32, 34). Each first XOR gate (32) processes as input two of said N primary input bits (36, 38) and each second XOR gate (34) processes as input bits output bits of first or second XOR gates (32, 34) or the input data bit (52). This structure makes it possible to create an array of identical basic cells which is very suitable for VLSI implementation. There are few lines of connections between the different cells in the cell array which leads to substantial reduction in propagation delay without adding substantial wiring or layout complexity.

Abstract: A carry logic circuit for a programmable logic device which uses a single function generator to create a carry propagate signal (P) and an output signal (S). The function generator includes a plurality of signal generation circuits, each of which is controlled by a first input signal (A) and a second input signal (B). One of the signal generation circuits is programmed to provide a desired carry propagate signal (P) in response to the first and second input signals (A,B). The carry propagate signal (P) is transmitted for use outside of the function generator to perform a carry propagation function for the carry logic circuit. The remaining signal generation circuits are programmed to generate one or more intermediate output signals in response to the first and second input signals (A,B). These intermediate output signals, in combination with carry propagate signal (P), are representative of the desired output signal (S).

Abstract: A logic signal level translation method and apparatus having very low dropout with respect to the powering rails and having a tri-state mode of operation allowing the output terminal to be driven to voltages beyond the highest supply voltage coupled thereto without significant power dissipation within the circuit. The output circuit includes well or body snatching devices which are controlled to assure that the wells of the output devices are able to follow extremes in voltage of the output terminal without biasing to conduction a PN junction of one or more of the output devices. A preferred embodiment is disclosed.

Abstract: A zero-stopping incrementer operates on the recognition that half of all digital values that require incrementing will be even numbers; that is, the least significant bit (LSB) is a binary "0". Incrementing such a number merely requires changing the LSB from a binary "0" to a binary "1". For odd numbers (i.e., those where the LSB is a binary "1"), the zero-stopping incrementer searches for the first binary "0" beginning with the LSB. Once found, that binary "0" is changed to a binary "1" and all the binary "1s" preceding it are changed to binary "0s". No change is required to the higher order bits following the first binary "0". This operation is very fast, the worst case being the case when all the binary bits of the number to be incremented are "1s". Nevertheless, the process is significantly increased, especially for 64-bit numbers which are processed by modern superscalar microprocessors.

Abstract: A logic circuit provides increment functions +1 and +2 and decrement functions -1 and -2.

Abstract: An evaluation tree circuit is disclosed that produces a generate, a propagate, and a zero output for use in carry lookahead adders. Another evaluation tree circuit is disclosed that merges the generate, propagate, and zero signals from several adjacent bits or groups of bits. These evaluation trees may be used in self-resetting CMOS or CVSL circuits. They can be used to reduce the number of levels of logic in a carry lookahead adder. They can also be used to form a magnitude comparator, which is also disclosed.

Abstract: An adder-based base cell (10) is provided for field programmable gate arrays. The base cell (10) includes a first inverter (13) operable to receive a first input signal (A). A first NAND gate (12) is coupled to the first inverter (13) and is operable to receive a second input signal (B). A first 2:1 multiplexer (14) is coupled to the first NAND gate (12) and is operable to receive a third input signal (C). The output of the first 2:1 multiplexer (14) represents a first function (F1). A second inverter (17) is operable to receive a fourth input signal (D). A second NAND gate (16) is coupled to the second inverter (17) and is operable to receive a fifth input signal (E). An XOR gate (18) is coupled to the second NAND gate (16), is operable to receive a sixth input signal (F), and is coupled to the first 2:1 multiplexer (14). The output of the XOR gate represents a partial sum function (PS.sub.-- 1).

Abstract: An arithmetic and logic unit is provided with a first NAND gate (29) which outputs a NAND logic operation result between a first operand (A.sub.i), a second operand (B.sub.i) and a first control signal (S.sub.0), a first EXOR gate (30) which outputs an EXOR logic operation result between the output of the first NAND gate (29) and a second control signal (S.sub.1), an OR gate (31) which outputs an OR logic operation result between the first operand (A.sub.i) and the second operand (B.sub.i), a second NAND gate (32) which outputs a NAND logic operation result between the output of the first EXOR gate (30) and the output of the OR gate (31), a third NAND gate (20) which outputs a NAND logic operation result between a third control signal (S.sub.2) and a carry input (CY.sub.

Abstract: The present invention relates to an implementation of domino logic using a logic cell which is not limited to the use of positive logic functions, and which can be implemented using MOS technology. A significant feature of the present invention relates to use of a single clock cycle to generate separate clock phases for a first function (e.g., carry function of a full-adder logic cell) and a second function (e.g., sum function in the full-adder logic cell). The separate clock phase used to gate the second function corresponds to a delayed version of the clock phase used to gate the first function, wherein the clock delay corresponds to a delay through the first function. In one exemplary embodiment, the delay can be made equal to that of the first function by using circuitry identical to that of the first function to create the delay period.