Abstract: In a method computer storage element operation, first and second rising (or falling) clock edges are applied to first and second power inputs of the computer storage element having a transistor array between the first and second power inputs over time T1 whereupon a logic value applied to an input of the transistor array is stored therein. Thereafter, first and second falling (or rising) clock edges are applied to the first and second power inputs over time T2, whereupon part of an electrical charge or energy associated with the logic value stored in the transistor array is provided to circuitry that generates the first and/or second clock edge(s), wherein the value(s) of time T1 and/or time T2 is/are greater than a product of RC, where R is resistance associated with the computer storage element, and C is a load capacitance associated with the computer storage element.

Abstract: Disclosed is a many-bit, groupable, reconfigurable, multi-valued, electronic operator and its construction method. Each bit of the electronic operator is provided with n column calculators and one potential combiner. A data input line is connected to an input terminal of an A signal selector, and an output terminal of the A signal selector is connected to a work permitter. Another input terminal of the work permitter is connected to a reconfiguration latch, and an output terminal of the work permitter is further connected to an output validator. Another input terminal of the output validator is connected to a power supply Vcc, and an output terminal of the output validator is connected to an output generator. Another input terminal of the output generator is connected to a reconfiguration circuit, and an output terminal of the output generator is connected to the potential combiner.

Abstract: An integrated memory device can include an array of memory cells with decoding and sensing circuitry, a memory controller, read and write circuitry associated to the sensing circuitry, logic circuit portions in the read and write circuitry including at least a logic element receiving a data stream on a data input and a clock signal on a clock input, and a programmable or trimmable delay element or circuit upstream to the data input or the clock input for self trimming the internal timing of said at least a logic element by aligning in time the clock signal and/or the data stream. Operating parameters of the integrated circuit can be set for self trimming an internal timing of the integrated circuit.

Abstract: Provided is a ternary logic synthesis method at least temporarily performed by a computer, the ternary logic synthesis method including generating a switching table with respect to pull-up and pull-down circuits using a truth table corresponding to a ternary function, converting the switching table into a sum of products (SOP) using a Quine-McCluskey algorithm, minimizing the SOP, and mapping a transistor corresponding to the SOP.

Abstract: Semiconductor circuitry comprises a plurality of signal transition detectors and dynamic OR circuitry. The plurality of signal transition detectors are configured to respectively output detection signals, each of the detection signals being based on a transition of at least one of a plurality of signals. The dynamic OR circuitry is configured to output a recovered clock signal based on a logical sum of the detection signals.

Abstract: Apparatus and methods for setting and clamping a node voltage are provided herein. In certain embodiments, a node control circuit includes a setting circuit for setting a voltage of a node based on a set signal. The node control circuit further includes at least one of a p-type follower clamp for clamping the node to an upper voltage limit based on an upper clamping control signal or an n-type follower clamp for clamping the node to a lower voltage limit based on a lower clamping control signal. When including both clamps, the node operates with a voltage level set by the set signal, but saturates at the upper voltage limit established by the upper clamping control signal and at the lower voltage limit established by the lower clamping control signal.

Abstract: A circuit includes an isolator that provides isolated signal communications between a host-side circuit and a converter-side circuit. The isolated signal communications include a conversion start signal generated in the host-side circuit passing through the isolator to become an isolated conversion start signal in the converter-side circuit. The isolated signal communications includes an isolated system clock generated in the converter-side circuit passing through the isolator to become a system clock in the host-side circuit. A sampling clock generator in the host-side circuit generates the conversion start signal based on the system clock. A logic circuit in the converter-side circuit re-clocks the isolated conversion start signal through the logic circuit.

Abstract: Various implementations are presented herein that improve the performance of dynamic quantizers over process, voltage and temperature (“PVT”) and input common mode (Vcm) variations. This can be accomplished by separating and then varying the voltage supply to the reset devices connected to the input devices of the quantizer while leaving the supply to the other parts of the quantizer unchanged. The timing performance of the quantizer can be improved (reduced clock-to-q) by lowering the voltage supply to the reset devices. The input referred RMS noise and offset voltage of the circuit can be improved (reduced) by raising the voltage supply to the reset devices. Similarly, increases in Vcm due to process and voltage scaling can be mitigated by raising the voltage supply to the reset devices. Control systems are also provided herein to control the voltage supply to the reset devices to accomplish these and other objectives.

Abstract: An integrated circuit comprises a circuit module, a first function circuit, and a second function circuit. The first function circuit is configured to be operational in response to a first type logic signal at a first pin and the second function circuit is configured to be operational in response to a second type logic signal at the first pin. The type of logic signal at the first pin is determined by the circuit module. Based on the determined type of logic signal, the circuit module is configured to activate the appropriate function circuit and provide function related signaling for operation at a second pin. The circuit module allows the pins of the integrated circuit to be shared between the first and second function circuits, thus minimizing the number of pins required for multi-functional circuits on the integrated circuit.

Abstract: At least one analog signal compatible complementary metal oxide semiconductor (CMOS) switch circuit is incorporated with digital logic circuits in an integrated circuit. The integrated circuit may further comprise a digital processor and memory, e.g., microcontroller, microprocessor, digital signal processor (DSP), programmable logic array (PLA), application specific integrated circuit (ASIC), etc., for controlling operation of the at least one analog signal compatible CMOS switch for switching analog signals, e.g., audio, video, serial communications, etc. The at least one analog signal compatible CMOS switch may have first and second states, e.g., single throw “on” or “off”, or double throw common to a or b, controlled by a single digital control signal of either a logic “0” or a logic “1”.

Abstract: In an asymmetrically terminated communication system, the power consumed to transmit a particular bit value is adjusted based on whether the bit being output is the second, third, fourth, etc. consecutive bit with the same value after a transition to output the particular bit value. The adjustment of the power consumed to transmit the two or more consecutive bits with the same value may be made by adjusting the driver strength during the second, or subsequent, consecutive bits with the same value. The adjustment of the power consumed is performed on the bit value that consumes the most DC power and the other value is typically not adjusted.

Abstract: A circuit having versatility synthesizes one-bit digital signals to generate a ternary signal. The pulse synthesizing circuit synthesizes one-bit digital signals from two DFFs to generate a ternary signal. The pulse synthesizing circuit has a first NOR gate, a second NOR gate, a third NOR gate, and three switches. The first switch is connected to a first electric potential, the second switch is connected to a second electric potential, and the third switch is connected to a third electric potential. The first to third switches are turned on/off according to logical values of the signals from the two DFFs, and any of the first electric potential, the second electric potential, and the third electric potential is set as an output potential so that a ternary signal is generated.

Abstract: A multi-valued logic (MVL) circuit includes a MVL clock generator that generates a MVL clock signal having three or more ith MVL levels, a single MVL clock signal distribution network connected to the MVL clock generator, and three or more ith MVL selection circuits connected to the single MVL clock signal distribution network where i=0 to N and N>=3. Each ith MVL selection circuit corresponds to a specified ith MVL level. The ith MVL selection circuit outputs an ith binary clock signal having: (a) a first logic level whenever the MVL clock signal is equal to the ith MVL level and the ith data input receives the first logic level, (b) a second logic level whenever the MVL clock signal is equal to the ith MVL level and the ith data input receives the second logic level, and (c) a previous logic level of the ith binary clock signal whenever the MVL clock signal is not equal to the ith MVL level.

Abstract: Disclosed is a voltage level converter that includes: a first conversion unit which receives at least one input signal of a logic 1 signal and a logic 0 signal from a signal input terminal and converts the signal; a second conversion unit and a third conversion unit which alternately output a logic ?1 signal and the logic 1 signal respectively in accordance with the input signal; a fourth conversion unit and a fifth conversion unit which alternately output the logic ?1 signal and the logic 0 signal respectively in accordance with the input signal; and a latch which has a complementary characteristic in which if a first transistor becomes an on-state, then a second transistor becomes an off-state in accordance with the input signal, and performs a positive feedback operation. A drain output of the first transistor is input to the fourth conversion unit. A drain output of the second transistor is input to the fifth conversion unit.

Abstract: Techniques for determining and a computing device configured to determine a quantum Karnaugh map through decomposing a quantum circuit into a multiple number of sub-circuits are provided. Also, techniques for obtaining and a computing device configured to obtain a quantum circuit which includes the minimum number of gates among possible quantum circuits corresponding to a quantum Karnaugh map are also provided.

Abstract: A row driver is configured to activate a row line responsive to a signal having one of multiple possible values. A column driver is configured to activate a column line responsive to a signal having one of multiple possible values. The row and column drivers comprise sets of sense amps and decoders. One of a plurality of lines is operably connected to and input/output line responsive to the active row line and column line. The use of sense amps in the row and column drivers enables this flow control circuit to operate with low power consumption and allows the flow control circuit to act as a register.

Abstract: A multi-valued driver circuit selectively outputs, to a transmission line, one from among multiple voltages according to a selection signal. A memory circuit stores setting data which define the respective levels of the multiple voltages. According to the selection signal, a selector circuit selects one from among the multiple setting data stored in the memory circuit. A Thevenin termination circuit outputs a voltage that corresponds to the upper M bits of the data thus selected by the selector circuit. An R-2R ladder circuit outputs a voltage that corresponds to the lower Nl bits of the data thus selected by the selector circuit.

Abstract: Hardware and processes are provided for efficient interpretation of multi-value signals. The multi-value signals have a first voltage range with is used to indicate multiple numerical or logical values, and a second voltage range that is used to provide control functions. In one example, the multi-value circuitry is arranged as a set of rows and columns, which may be cascaded together. The control function can be implemented to cause portions of rows, columns, or cascaded connections to be powered off, thereby saving power and enabling more efficient operation.

Abstract: A one-of-n storage cell for use in an N-nary dynamic logic (NDL) circuit. The storage cell may accept an input value and provide a complemented output value that corresponds to the input value. However, if an input value that corresponds to a precharge input value is received, the output value remains the previous output value. The storage cell may be implemented to accept either inverted or non-inverted one-of-n NDL signals and to provide as an output either non-inverted or inverted one-of-N NDL signals, respectively, where N is greater than two.

Abstract: Quad-state logic elements and quad-state memory elements are used to reduce the wiring density of integrated circuits. The resulting reduction in wiring interconnects between memories and logic elements results in higher speed, higher density, and lower power integrated circuit designs.

Abstract: Apparatus are disclosed, such as those involving a transmitter circuit that is configured to generate multi-level signals based on a plurality of data digits. One such transmitter circuit includes a signal output and an encoder configured to provide control signals based at least partially on the plurality of data digits. The transmitter circuit also includes a first set of switches configured to receive one or more of the control signals, and to selectively conduct a first or second voltage reference to the signal output. The transmitter circuit further includes first and second voltage drop circuits that provide third and fourth voltage references, respectively. The third and fourth voltage references have voltage levels between those of the first and second voltage references. The transmitter circuit also includes a second set of switches configured to receive one or more of the control signals, and selectively conduct the third or fourth voltage reference to the signal output.

Abstract: A latch circuit switches a differential operation performed by a differential operation circuit including a first logic circuit, a second logic circuit, a third logic circuit, and a fourth logic circuit and a single end operation performed by a single end operation circuit according to a logic level of an inputted selection signal. The latch circuit performs an operation to output an input signal and an inverted input signal without change from a first output terminal and a second output terminal of the latch circuit, respectively, and an operation to set the input signal and the inverted input signal in a hold state in the differential operation and performs an operation to output the input signal from the first output terminal without change and an operation to set the input signal in a hold state in the single end operation, according to a clock signal and an inverted clock signal.

Abstract: A one-of-n storage cell for use in an N-nary dynamic logic (NDL) circuit. The storage cell may accept an input value and provide a complemented output value that corresponds to the input value. However, if an input value that corresponds to a precharge input value is received, the output value remains the previous output value. The storage cell may be implemented to accept either inverted or non-inverted one-of-n NDL signals and to provide as an output either non-inverted or inverted one-of-N NDL signals, respectively, where N is greater than two.

Abstract: Hardware and processes are provided for efficient interpretation of multi-value signals. The multi-value signals have a first voltage range with is used to indicate multiple numerical or logical values, and a second voltage range that is used to provide control functions. In one example, the multi-value circuitry is arranged as a set of rows and columns, which may be cascaded together. The control function can be implemented to cause portions of rows, columns, or cascaded connections to be powered off, thereby saving power and enabling more efficient operation.

Abstract: Hardware and processes are provided for efficient interpretation of multi-value signals. The multi-value signals have a first voltage range with is used to indicate multiple numerical or logical values, and a second voltage range that is used to provide control functions. In one example, the multi-value circuitry is arranged as a set of rows and columns, which may be cascaded together. The control function can be implemented to cause portions of rows, columns, or cascaded connections to be powered off, thereby saving power and enabling more efficient operation.

Abstract: Vertical dithering is performed for vertical droop compensation in image processing using Linear Feedback Shift Registers (LFSRs). Line memories are not used. A compensation circuit includes a signature reload input signal coupled to the input of five LFSRs. Each LFSR includes a signature store. The output of each LFSR provides a sequence output signal that is gated with a corresponding enable signal in a first logic circuit. The output of all of the first logic circuits are combined in a second logic circuit to provide a control signal output.

Abstract: A combinatorial circuit with pre-calculation and having shorter delay is described. The combinatorial circuit uses information available from earlier input signals to pre-calculate intermediate signals, which are used to generate output signals when the last input signal arrives. The combinatorial circuit includes an input calculation block, at least one pre-calculation block, and an output calculation block coupled in series. The input calculation block receives some input signals and generates intermediate signals for the first pre-calculation block. The pre-calculation block(s) receive at least one earlier input signal and generate additional intermediate signals. The output calculation block receives the latest input signal and the intermediate signals from the last pre-calculation block and generates the output signals. The pre-calculation block(s) and the output calculation block may be implemented with simple circuits.

Abstract: Quad-state logic elements and quad-state memory elements are used to reduce the wiring density of integrated circuits. The resulting reduction in wiring interconnects between memories and logic elements results in higher speed, higher density, and lower power integrated circuit designs.

Abstract: Disclosed herein is a logic circuit which responds to three signals to detect whether the number of signals taking one of logic-1 and logic-0 is odd or even, and includes five NAND gates. The first NAND gate is supplied with the first signal, the second signal and the third signal; the second NAND gate is supplied with the inverted first signal, the inverted second signal and the third signal; the third NAND gate is supplied with the first signal, the inverted second signal and the inverted third signal; and the fourth NAND gate is supplied with the inverted first signal, the second signal and the inverted third signal. The fifth NAND gate is supplied with outputs of first, second, third and fourth NAND gates and produces the output signal whose logic level is dependent on whether the number of the input signals taking one of logic-1 and logic-0 is odd or even.

Abstract: Apparatus are disclosed, such as those involving a transmitter circuit that is configured to generate multi-level signals based on a plurality of data digits. One such transmitter circuit includes a signal output and an encoder configured to provide control signals based at least partially on the plurality of data digits. The transmitter circuit also includes a first set of switches configured to receive one or more of the control signals, and to selectively conduct a first or second voltage reference to the signal output. The transmitter circuit further includes first and second voltage drop circuits that provide third and fourth voltage references, respectively. The third and fourth voltage references have voltage levels between those of the first and second voltage references. The transmitter circuit also includes a second set of switches configured to receive one or more of the control signals, and selectively conduct the third or fourth voltage reference to the signal output.

Abstract: A control circuit generates an output based on the first signal and the second signal by encoding the output to be a multi-state signal having at least three states. A magnitude of the multi-state signal generated by the controller varies depending on binary states of the first signal and the second signal. The controller utilizes the output (i.e., the multi-state signal) to control a switching circuit. A driver circuit receives the output generated by the control circuit. In one embodiment, the multi-state signal has more than two different logic states. The driver decodes the multi-state signal for generating signals to control switches in the switching circuit. One signal generated by the driver circuit is a pulse width modulation signal; another signal generated by the driver circuit is an enable/disable signal.

Abstract: Quad-state logic elements and quad-state memory elements are used to reduce the wiring density of integrated circuits. The resulting reduction in wiring interconnects between memories and logic elements results in higher speed, higher density, and lower power integrated circuit designs.

Abstract: A pull-up switching device for controlling connection and non-connection of an input terminal IN and a first supply VDD and a pull-down switching device for controlling connection and non-connection of the input terminal IN and a second supply VSS are provided. The pull-up switching device and the pull-down switching device are operated exclusively on and off in time division to hold and output the state of the input terminal during each operating state from the two output terminals.

Abstract: Quad-state logic elements and quad-state memory elements are used to reduce the wiring density of integrated circuits. The resulting reduction in wiring interconnects between memories and logic elements results in higher speed, higher density, and lower power integrated circuit designs.

Abstract: A buffer apparatus for a communications bus comprises a driver circuit having an output. An amplifier circuit having an input is coupled to the output of the driver circuit. The driver circuit is arranged to generate, when in use, a drive signal having a waveform that comprises a step therein so as to substantially suppress generation by the amplifier circuit of a portion of an oscillation of an output signal.

Abstract: The tolerant buffer circuit and interface are provided in which reverse inflow of current to a power supply voltage from an output terminal does not occur, even if the output terminal is at a higher potential than an output circuit power supply voltage during open-drain operation in an output circuit of a semiconductor integrated circuit, or if the output circuit power supply voltage becomes 0 V.

Abstract: The invention relates to error-correcting coding and correct restart of decoding after errors of sequences that are coded by convolutional coders or LFSR based descramblers. The signals can be binary or multi-valued signals. Methods and apparatus to convolutional encode and decode sequences of binary and n-valued symbols are disclosed. The invention further discloses methods and apparatus to identify symbols in error in sequences coded according to methods of the invention. Methods and apparatus to correct these errors are provided. Methods and apparatus to repair errors in a Trellis of received sequences are also provided. Methods and apparatus for n-valued Recursive Systematic Convolutional coders and decoders are disclosed.

Abstract: High voltage logic circuits that can handle digital input and output signals having a larger voltage range are described. In an exemplary design, a high voltage logic circuit includes an input stage, a second stage, and an output stage. The input stage receives at least one input signal and provides (i) at least one first intermediate signal having a first voltage range and (ii) at least one second intermediate signal having a second voltage range. The second stage receives and processes the first and second intermediate signals based on a logic function and provides (i) a first drive signal having the first voltage range and (ii) a second drive signal having the second voltage range. The output stage receives the first and second drive signals and provides an output signal having a third voltage range, which may be larger than each of the first and second voltage ranges.

Abstract: A combinatorial circuit with pre-calculation and having shorter delay is described. The combinatorial circuit uses information available from earlier input signals to pre-calculate intermediate signals, which are used to generate output signals when the last input signal arrives. The combinatorial circuit includes an input calculation block, at least one pre-calculation block, and an output calculation block coupled in series. The input calculation block receives some input signals and generates intermediate signals for the first pre-calculation block. The pre-calculation block(s) receive at least one earlier input signal and generate additional intermediate signals. The output calculation block receives the latest input signal and the intermediate signals from the last pre-calculation block and generates the output signals. The pre-calculation block(s) and the output calculation block may be implemented with simple circuits.

Abstract: Quad-state logic elements and quad-state memory elements are used to reduce the wiring density of integrated circuits. The resulting reduction in wiring interconnects between memories and logic elements results in higher speed, higher density, and lower power integrated circuit designs.

Abstract: A control circuit generates an output based on the first signal and the second signal by encoding the output to be a multi-state signal having at least three states. A magnitude of the multi-state signal generated by the controller varies depending on binary states of the first signal and the second signal. The controller utilizes the output (i.e., the multi-state signal) to control a switching circuit. A driver circuit receives the output generated by the control circuit. In one embodiment, the multi-state signal has more than two different logic states. The driver decodes the multi-state signal for generating signals to control switches in the switching circuit. One signal generated by the driver circuit is a pulse width modulation signal; another signal generated by the driver circuit is an enable/disable signal.

Abstract: N-valued re-circulating latches using n-valued reversible inverters with n>3 are disclosed. Latches using n-valued self-reversing inverters are provided; latches using n-valued universal inverters are provided; and latches using inverters which are not self-reversing or universal are also provided. A latch may use two individually controlled gates. It may also use one individually controlled gate. N-valued latches are provided wherein a state is represented by a signal being an independent instance of a physical phenomenon. A latch not using absence-of-signal as a state is also provided.

Abstract: Quad-state logic elements and quad-state memory elements are used to reduce the wiring density of integrated circuits. The resulting reduction in wiring interconnects between memories and logic elements results in higher speed, higher density, and lower power integrated circuit designs.

Abstract: There is provided a three-valued logic function circuit capable of remarkably reducing the kinds of basic circuits necessary for realizing all 33^2=19683 kinds of two-variable three-valued logic function circuits, remarkably reducing asymmetry of the switching time, and improving an operation speed and symmetry of waveform of the logic function circuit. In a three-valued logic function circuit, three transfer gates T1, T2, and T3 are turned on or off by one-variable three-valued logic function circuits C1, D1, C3 and D3, according to three logic values ?1, 0, and 1 constituting a first input a, to select outputs of three one-variable three-valued logic function circuits B1, B2, and B3 connected to a second input b. The transfer gate T2 is configured by parallel connection of a switch pair of serial connection of two n-type MOS transistors and a switch pair of serial connection of two p-type MOS transistors.

Abstract: A support identification device comprising a support (BPA), e.g. a rack or backplane of a telecommunication system, and an identity receiver (PCB), e.g. a printed circuit board or card, coupled to an identity transmitter or connector of the support. The identity transmitter has several read pins (id1-id4=R1-R4) each at a logical level (0, 1) to indicate (identify) the type of support. The card (PCB) further has write terminals (W1, W2) coupled to dynamic terminals (D1, D2) of the support (BPA). These dynamic terminals are coupled to one or more of the read pins (id1-id4). The card is also provided with a program that sets the write terminals at a first logical level, reads a first logical level at each read pin (R1-R4), then sets the write terminals at a second logical level, reads a second logical level at each read pin, and determines from the difference between the first and the second read logical levels to which write terminal each read terminal is coupled, or not.

Abstract: Method and apparatus for writing scrambled multi-value data to a physical media and for reading scrambled multi-value data from a physical media, are disclosed. The physical media can be an optical disk. The scrambling can be performed by a multi-valued LFSR scrambler and the descrambling can be performed by a multi-valued LFSR descrambler. Further, the multi-valued data that is scrambled can include synchronization data and/or user data. Error correction coding can be used during the writing process and processing to correct for errors can be used during the reading process. Also, methods and apparatus for synchronizing multi-valued data written to and read from physical media are disclosed. Multi-value correlation methods and apparatus are also disclosed.

Abstract: An n-valued switch with n?2, with an input enabled to receive a signal in one of n states, an output enabled to provide a signal in one of at least 2 states, under control of a control signal having one of at least 2 states is disclosed. Signals are instances of a physical phenomenon, an instance representing a state. N-valued inverters are also disclosed. Different types of signals are disclosed, including optical signals with different wavelengths, electrical signals with different frequencies and signals represented by a presence of a material. A kit including an n-valued switch is also disclosed.

Abstract: N-valued re-circulating latches using n-valued reversible inverters with n>3 are disclosed. Latches using n-valued self-reversing inverters are provided; latches using n-valued universal inverters are provided; and latches using inverters which are not self-reversing or universal are also provided. A latch may use two individually controlled gates. It may also use one individually controlled gate. N-valued latches are provided wherein a state is represented by a signal being an independent instance of a physical phenomenon. A latch not using absence-of-signal as a state is also provided.

Abstract: A transmission system and method may be provided. The transmission system may transmit 2-bit data for each transmission line set and each transmission line set may include first, second and/or third transmission lines arranged in order. The first, second and/or third transmission lines may respectively transmit first, second and/or third signals each having one of first, second and/or third values such that a combination of a first electric field between the first and second transmission lines and a second electric field between the second and third transmission lines may be made depending on a logic state of the 2-bit data. The transmission system may transmit differential signals using a smaller number of transmission lines and the transmission system may transmit a larger number of signals in the same circuit area.

Abstract: N-valued re-circulating latches using n-valued reversible inverters with n>3 are disclosed. Latches using n-valued self-reversing inverters are provided; latches using n-valued universal inverters are provided; and latches using inverters which are not self-reversing or universal are also provided. A latch may use two individually controlled gates. It may also use one individually controlled gate. N-valued latches are provided wherein a state is represented by a signal being an independent instance of a physical phenomenon. A latch not using absence-of-signal as a state is also provided.