Function Of And, Or, Nand, Nor, Or Not Patents (Class 326/7)
  • Patent number: 11689223
    Abstract: Model-free error correction in quantum processors is provided, allowing tailoring to individual devices. In various embodiments, a quantum circuit is configured according to a plurality of configuration parameters. The quantum circuit comprises an encoding circuit and a decoding circuit. Each of a plurality of training states is input to the quantum circuit. The encoding circuit is applied to each of the plurality of training states and to a plurality of input syndrome qubits to produce encoded training states. The decoding circuit is applied to each of the encoded training states to determine a plurality of outputs. A fidelity of the quantum circuit is measured for the plurality of training states based on the plurality of outputs. The fidelity is provided to a computing node. The computing node determines a plurality of optimized configuration parameters. The optimized configuration parameters maximize the accuracy of the quantum circuit for the plurality of training states.
    Type: Grant
    Filed: September 14, 2018
    Date of Patent: June 27, 2023
    Assignee: President and Fellows of Harvard College
    Inventors: Alan Aspuru-Guzik, Jonathan P. Olson, Jhonathan Romero Fontalvo, Peter D. Johnson, Yudong Cao, Pierre-Luc Dallaire-Demers
  • Patent number: 11329638
    Abstract: Systems and techniques that facilitate multi-resonant couplers for preserving ZX interaction while reducing ZZ interaction are provided. In various embodiments, a first qubit can have a first operational frequency and a second qubit can have a second operational frequency, and a multi-resonant architecture can couple the first qubit to the second qubit. In various embodiments, the multi-resonant architecture can comprise a first resonator and a second resonator. In various cases, the first resonator can capacitively couple the first qubit to the second qubit, and a second resonator can capacitively couple the first qubit to the second qubit. In various aspects, the first resonator and the second resonator can be in parallel.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: May 10, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David C. Mckay, Abhinav Kandala, Srikanth Srinivasan
  • Patent number: 11200947
    Abstract: Apparatus and methods relating to programmable superconducting cells are described. A programmable superconducting cell can be formed from a superconducting current loop having at least two terminals connected to the loop. The current loop and terminals can be formed from a single layer of superconducting material. The programmable superconducting cell can be incorporated into a crossbar architecture to form a high-speed vector-matrix multiplying processor for deep neural network computations.
    Type: Grant
    Filed: February 4, 2019
    Date of Patent: December 14, 2021
    Assignee: Massachusetts Institute of Technology
    Inventors: Karl K. Berggren, Oguzhan Murat Onen, Brenden Butters, Emily Toomey
  • Patent number: 11165429
    Abstract: The invention is notably directed to a method of operating a superconducting channel. The method relies on a device including: a potentially superconducting material; a gate electrode; and an electrically insulating medium. A channel is defined by the potentially superconducting material. The gate electrode positioned adjacent to the channel, such that an end surface of the gate electrode faces a portion of the channel. The electrically insulating medium is arranged in such a manner that it electrically insulates the gate electrode from the channel. Rendering the channel superconducting by cooling down the device. Next, a voltage difference is applied between the gate electrode and the channel to inject electrons in the channel through the electrically insulating medium and thereby generate a gate current between the gate electrode and the channel. The electrons are injected with an average energy sufficient to modify a critical current IC of the channel.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: November 2, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Andreas Fuhrer Janett, Fabrizio Nichele, Markus Fabian Ritter, Heike Erika Riel
  • Patent number: 11042813
    Abstract: Methods, systems and apparatus for producing quantum circuits with low T gate counts. In one aspect, a method for performing a temporary logical AND operation on two control qubits includes the actions of obtaining an ancilla qubit in an A-state; computing a logical-AND of the two control qubits and storing the computed logical-AND in the state of the ancilla qubit, comprising replacing the A-state of the ancilla qubit with the logical-AND of the two control qubits; maintaining the ancilla qubit storing the logical-AND of the two controls until a first condition is satisfied; and erasing the ancilla qubit when the first condition is satisfied.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: June 22, 2021
    Inventor: Craig Gidney
  • Patent number: 10924095
    Abstract: Systems and techniques that facilitate multi-resonant couplers for preserving ZX interaction while reducing ZZ interaction are provided. In various embodiments, a first qubit can have a first operational frequency and a second qubit can have a second operational frequency, and a multi-resonant architecture can couple the first qubit to the second qubit. In various embodiments, the multi-resonant architecture can comprise a first resonator and a second resonator. In various cases, the first resonator can capacitively couple the first qubit to the second qubit, and a second resonator can capacitively couple the first qubit to the second qubit. In various aspects, the first resonator and the second resonator can be in parallel.
    Type: Grant
    Filed: June 9, 2020
    Date of Patent: February 16, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David C. Mckay, Abhinav Kandala, Srikanth Srinivasan
  • Patent number: 10846608
    Abstract: This application concerns quantum computing and quantum circuits. For example, among the embodiments disclosed herein are codes and protocols to distill T, controlled-S, and Toffoli (or CCZ) gates for use in croantum circuits. Examples of the disclosed codes use lower overhead for a given target accuracy relative to other distillation techniques. In some embodiments, a magic state distillation protocol is generated for creating magic states in the quantum computing device, wherein the magic state distillation protocol includes (a) Reed-Muller codes, or (b) punctured Reed-Muller codes. The quantum computing device can then configured to implement the magic state distillation protocol.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: November 24, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Jeongwan Haah, Matthew Hastings
  • Patent number: 10775173
    Abstract: The present disclosure relates to Superfluid QUantum Interference Devices (SQUIDs) that measure phase differences existing in quasi-particles or matter-wave systems, and the related techniques for their use at room-temperatures. These Bose-Einstein Condensation interferometry techniques include quantum scale metrology devices such as quasi-particle based linear accelerometers, gyroscopes, and Inertial Measurement Units that incorporate such interferometers. In the presence of additive white Gaussian noise, estimates are made for the Bias Instability, Angle Random Walk, and Velocity Random Walk of the device for purposes of quantum inertial sensing. Moreover, this disclosure relates to SQUIDs based on charged quasi-particles that can, in turn, be used to construct quantum computing elements such as quantum transistors, and quasi-particle circuits at room-temperatures. These quasi-particle circuits can be used to build analogs of electronic circuit elements, and offer an alternative to traditional electronics.
    Type: Grant
    Filed: March 19, 2019
    Date of Patent: September 15, 2020
    Inventor: Frederick Ira Moxley, III
  • Patent number: 10496932
    Abstract: Aspects of the present disclosure describe a compact RF driver circuit for Paul traps in trapped ion quantum computers and methods, and structures including same.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: December 3, 2019
    Assignee: Duke University
    Inventors: Jungsang Kim, Geert Vrijsen, Robert Spivey
  • Patent number: 9773208
    Abstract: Quantum information processing apparatus and methods are described. The apparatus comprises a device for defining a qubit and a reflectometry circuit for reading out a state of the qubit. The device comprises a semiconductor nanowire extending along a first direction having first and second obtuse or acute edges running along the first direction, gate dielectric overlying the first and second edges of the nanowire and a split gate running across a section of the nanowire in a second, transverse direction, the split gate comprising first and second gates overlying the first and second edges respectively. The reflectometry circuit comprises a resonator coupled to the first or second gate.
    Type: Grant
    Filed: April 11, 2016
    Date of Patent: September 26, 2017
    Assignee: HITACHI, LTD.
    Inventors: Andreas Betz, Miguel Fernando Gonzalez-Zalba
  • Patent number: 9396440
    Abstract: Systems and methods to solve combinatorial problems employ a permutation network which may be modeled after a sorting network where comparators are replaced by switches that controllably determine whether inputs are swapped or are left unchanged at the outputs. A quantum processor may be used to generate permutations by the permutation network by mapping the state of each switch in the network to the state of a respective qubit in the quantum processor. In this way, a quantum computation may explore all possible permutations simultaneously to identify a permutation that satisfies at least one solution criterion. The Travelling Salesman Problem is discussed as an example of a combinatorial problem that may be solved using these systems and methods.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: July 19, 2016
    Assignee: D-WAVE SYSTEMS INC.
    Inventors: William G. Macready, Edward D. Dahl
  • Patent number: 9276564
    Abstract: A nanomechanical device, operating as a reprogrammable logic gate, and performing fundamental logic functions such as AND/OR and NAND/NOR. The logic function can be programmed (e.g., from AND to OR) dynamically, by adjusting the operating parameters of the resonator. The device can access one of two stable steady states, according to a specific logic function; this operation is mediated by the noise floor which can be directly adjusted, or dynamically tuned via an adjustment of the underlying nonlinearity of the resonator, i.e., it is not necessary to have direct control over the noise floor. The demonstration of this reprogrammable nanomechanical logic gate affords a path to the practical realization of a new generation of mechanical computers.
    Type: Grant
    Filed: May 3, 2013
    Date of Patent: March 1, 2016
    Assignee: THE UNITED STATES OF AMERICA AS REPRESENTED BY THE SECRETARY OF THE NAVY
    Inventors: William L. Ditto, Pritiraj Mohanty, Sudeshna Sinha, Ardeshir R. Bulsara, Diego Guerra, Krishnamurthy Murali
  • Publication number: 20150115998
    Abstract: Systems and methods are provided for generating at least one high fidelity resource state. A classical code and punctured to provide a first set of generators and a second set of generators. The first set of generators is mapped to a set of stabilizer generators, and the second set of generators is mapped to a set of logical operators. A set of resource states are prepared in physical qubits. A decoding process is performed on the resource states according to a quantum code represented by the set of stabilizer generators and the set of logical operators, and qubits corresponding to the stabilizers are measured.
    Type: Application
    Filed: December 29, 2014
    Publication date: April 30, 2015
    Applicant: NORTHROP GRUMMAN SYSTEMS CORPORATION
    Inventor: BRYAN K. EASTIN
  • Patent number: 9018971
    Abstract: Systems and methods are provided for generating at least one high fidelity resource state. A classical code and punctured to provide a first set of generators and a second set of generators. The first set of generators is mapped to a set of stabilizer generators, and the second set of generators is mapped to a set of logical operators. A set of resource states are prepared in physical qubits. A decoding process is performed on the resource states according to a quantum code represented by the set of stabilizer generators and the set of logical operators, and qubits corresponding to the stabilizers are measured.
    Type: Grant
    Filed: February 12, 2013
    Date of Patent: April 28, 2015
    Assignee: Northrop Grumman Systems Corporation
    Inventor: Bryan K. Eastin
  • Patent number: 9007088
    Abstract: Preservation of quantum entanglement in a two-qubit system is achieved by use of the disclosed systems. Three different example two-qubit systems are shown: (1) a system employing a weak measurement, (2) a system in which a generalized amplitude dampening occurs without use of a weak measurement, and (3) an extended system in which the system is prepared in a more robust state less susceptible to decoherence prior to a generalized amplitude dampening.
    Type: Grant
    Filed: April 1, 2013
    Date of Patent: April 14, 2015
    Assignees: Texas A&M University System, King Abdulaziz City for Science and Technology
    Inventors: Zeyang Liao, M. Al-Amri, M. Suhail Zubiary
  • Patent number: 8957699
    Abstract: Systems and methods are provided for generating a high-fidelity Toffoli state from a plurality of low-fidelity single qubit magic states. First and second qubits are prepared in a high-fidelity initial state. N target qubits are prepared in the single qubit magic state. A series of gates are performed on the qubits, such that the system is in a state ½|0001 . . . 0N+½|0101 . . . 0N+½|1001 . . . 0N+½|1111 . . . 1N. A parity check is performed on the N target qubits. The parity check provides at least a first measurement value. The first qubit, the second qubit, and the first target qubit are accepted as the Toffoli state if the measurement values assume the desired values.
    Type: Grant
    Filed: February 12, 2013
    Date of Patent: February 17, 2015
    Assignee: Northrop Grumman Systems Corporation
    Inventor: Bryan K. Eastin
  • Patent number: 8928353
    Abstract: A binary half-adder comprising first and second oscillators, each oscillator being connected to a first input and to a second input, the second oscillator being connected to the first oscillator, wherein the first oscillator is configured to oscillate if the first input is high or the second input is high, the second oscillator is configured to oscillate if the first and the second inputs are high, and wherein the connection between the second oscillator and the first oscillator is configured to suppress oscillation of the first oscillator if the second oscillator is oscillating.
    Type: Grant
    Filed: July 1, 2011
    Date of Patent: January 6, 2015
    Assignee: Manchester Metropolitan University
    Inventors: Stephen Lynch, Jon Borresen
  • Publication number: 20140145751
    Abstract: An electronic device for implementing digital functions comprising a first and a second electrode regions, separated by an interposing region comprising a dielectric region, is described. The first and the second electrode regions comprise at least one first electrode and at least one second electrode, respectively, configured to generate in the interposing region an electric field depending on an electric potential difference applied thereto. In the interposing region, a molecular layer is comprised, which is composed of a plurality of molecules, each being capable of assuming one or more states, in a controllable manner, depending on a sensed electric field. The dielectric region has a spatially variable dielectric profile, to determine a respective spatially variable field profile of the sensed electric field at the molecular layer.
    Type: Application
    Filed: November 25, 2013
    Publication date: May 29, 2014
    Applicant: STMicroelectronics S.r.l.
    Inventor: Alessandro Paolo Bramanti
  • Publication number: 20140118023
    Abstract: Systems and methods are provided for generating at least one high fidelity resource state. A classical code and punctured to provide a first set of generators and a second set of generators. The first set of generators is mapped to a set of stabilizer generators, and the second set of generators is mapped to a set of logical operators. A set of resource states are prepared in physical qubits. A decoding process is performed on the resource states according to a quantum code represented by the set of stabilizer generators and the set of logical operators, and qubits corresponding to the stabilizers are measured.
    Type: Application
    Filed: February 12, 2013
    Publication date: May 1, 2014
    Inventor: Bryan K. Eastin
  • Publication number: 20140118024
    Abstract: Systems and methods are provided for generating a high-fidelity Toffoli state from a plurality of low-fidelity single qubit magic states. First and second qubits are prepared in a high-fidelity initial state. N target qubits are prepared in the single qubit magic state. A series of gates are performed on the qubits, such that the system is in a state ½|0001 . . . 0N+½|0101 . . . 0N+|½|1001 . . . 0N+½|1111 . . . 1N. A parity check is performed on the N target qubits. The parity check provides at least a first measurement value. The first qubit, the second qubit, and the first target qubit are accepted as the Toffoli state if the measurement values assume the desired values.
    Type: Application
    Filed: February 12, 2013
    Publication date: May 1, 2014
    Inventor: BRYAN K. EASTIN
  • Patent number: 8633729
    Abstract: A computing structure is described. The computing structure includes at least one logic gate. The at least one logic gate has an arrangement of nano-particles configured to propagate localized plasmon-polaritons (LLPs). The logic gate may have a gate state and be configured to perform a logic function based on a desired logical output.
    Type: Grant
    Filed: January 27, 2012
    Date of Patent: January 21, 2014
    Assignee: Rockwell Collins, Inc.
    Inventor: Robert G. Brown
  • Patent number: 8610453
    Abstract: Superconducting single flux quantum circuits are disclosed herein, each having at least one Josephson junction which will flip when the current through it exceeds a critical current. Bias current for the Josephson junction is provided by a biasing transformer instead of a resistor. The lack of any bias resistors ensures that unwanted power dissipation is eliminated.
    Type: Grant
    Filed: June 23, 2011
    Date of Patent: December 17, 2013
    Assignee: Northrop Grumman Systems Corporation
    Inventor: Quentin P. Herr
  • Patent number: 8571614
    Abstract: A superconducting integrated circuit, comprising a plurality of superconducting circuit elements, each having a variation in operating voltage over time; a common power line; and a plurality of bias circuits, each connected to the common power line, and to a respective superconducting circuit element, wherein each respective bias circuit is superconducting during at least one time portion of the operation of a respective superconducting circuit element, and is configured to supply the variation in operating voltage over time to the respective superconducting circuit element.
    Type: Grant
    Filed: October 12, 2010
    Date of Patent: October 29, 2013
    Assignee: Hypres, Inc.
    Inventors: Oleg A. Mukhanov, Alexander F. Kirichenko, Dmitri Kirichenko
  • Patent number: 8558571
    Abstract: Illustrative embodiments of all-spin logic devices, circuits, and methods are disclosed. In one embodiment, an all-spin logic device may include a first nanomagnet, a second nanomagnet, and a spin-coherent channel extending between the first and second nanomagnets. The spin-coherent channel may be configured to conduct a spin current from the first nanomagnet to the second nanomagnet to determine a state of the second nanomagnet in response to a state of the first nanomagnet.
    Type: Grant
    Filed: January 6, 2012
    Date of Patent: October 15, 2013
    Assignee: Purdue Research Foundation
    Inventors: Behtash Behin-Aein, Srikant Srinivasan, Angik Sarkar, Supriyo Datta, Sayeef Salahuddin
  • Patent number: 8436637
    Abstract: A nanomechanical device, operating as a reprogrammable logic gate, and performing fundamental logic functions such as AND/OR and NAND/NOR. The logic function can be programmed (e.g., from AND to OR) dynamically, by adjusting the operating parameters of the resonator. The device can access one of two stable steady states, according to a specific logic function; this operation is mediated by the noise floor which can be directly adjusted, or dynamically tuned via an adjustment of the underlying nonlinearity of the resonator, i.e., it is not necessary to have direct control over the noise floor. The demonstration of this reprogrammable nanomechanical logic gate affords a path to the practical realization of a new generation of mechanical computers.
    Type: Grant
    Filed: March 9, 2011
    Date of Patent: May 7, 2013
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: William L. Ditto, Pritiraj Mohanty, Sudeshna Sinha, Ardeshir R. Bulsara, Diego N. Guerra, Krishnamurthy Murali
  • Patent number: 8421060
    Abstract: A logic device includes: a substrate having a channel layer; two input terminal patterns of ferromagnetic material formed on the substrate and spaced apart from each other along a longitudinal direction of the channel layer so as to serve as the input terminals of a logic gate; and an output terminal pattern of ferromagnetic material formed on the substrate and disposed between the two input terminal patterns to serve as an output terminal of the logic gate. The output terminal pattern reads an output voltage by using spin accumulation and diffusion of electron spins which are injected into the channel layer from the input terminal patterns.
    Type: Grant
    Filed: January 8, 2010
    Date of Patent: April 16, 2013
    Assignee: Korea Institute of Science and Technology
    Inventors: Hyun Cheol Koo, Suk Hee Han, Joon Yeon Chang, Hyung Jun Kim, Jang Hae Ku
  • Patent number: 8350587
    Abstract: Methods and systems are disclosed for restoring a state of a qubit transformed by a weak measurement to its original state. Unlike traditional methods, in which, the restoration was carried out by way of another weak measurement, the disclosed method uses an additional qubit, referred to as the ancillary qubit, and appropriate Hadamard and CNOT transformation for restoring the original state. Because the disclosed method avoids a second weak measurement, the time for restoration of the original state is considerably reduced.
    Type: Grant
    Filed: October 21, 2011
    Date of Patent: January 8, 2013
    Assignee: Texas A&M University System
    Inventors: Mohammad Suhail Zubairy, Marlan Scully, Mohammad Al-Amri
  • Patent number: 8169231
    Abstract: A superconducting readout system includes a computation qubit; a measurement device to measure a state of the computation qubit; and a latch qubit that mediates communicative coupling between the computation qubit and the measurement device. The latch qubit includes a qubit loop that includes at least two superconducting inductors coupled in series with each other; a compound Josephson junction that interrupts the qubit loop that includes at least two Josephson junctions coupled in series with each other in the compound Josephson junction and coupled in parallel with each other with respect to the qubit loop; and a first clock signal input structure to couple clock signals to the compound Josephson junction.
    Type: Grant
    Filed: September 23, 2008
    Date of Patent: May 1, 2012
    Assignee: D-Wave Systems Inc.
    Inventor: Andrew Joseph Berkley
  • Patent number: 8138784
    Abstract: In one embodiment, the disclosure relates to a method and apparatus for controlling the energy state of a qubit by bringing the qubit into and out of resonance by coupling the qubit to a flux quantum logic gate. The qubit can be in resonance with a pump signal, with another qubit or with some quantum logic gate. In another embodiment, the disclosure relates to a method for controlling a qubit with RSFQ logic or through the interface between RSFQ and the qubit.
    Type: Grant
    Filed: February 7, 2011
    Date of Patent: March 20, 2012
    Assignee: Northrop Grumman Systems Corporation
    Inventors: John Xavier Przybysz, James E. Baumgardner, Aaron A. Pesetski, Donald Lynn Miller, Quentin P. Herr
  • Patent number: 8022722
    Abstract: Systems and methods are provided for performing a quantum gate operation. A first classical control parameter, configured to tune an associated frequency of a first qubit, is adjusted from a first value to a second value. The first value is selected such that the first qubit is tuned far from a characteristic frequency of an associated resonator, and the second value is selected such that the first qubit is tuned near to the characteristic frequency of the resonator. A second classical control parameter, configured to tune an associated frequency of a second qubit, is adjusted from a third value to a fourth value. The third value is selected such that the second qubit is tuned far from the characteristic frequency of the resonator. The first classical control parameter is returned to the first value. The second classical control parameter is returned to the third value.
    Type: Grant
    Filed: June 4, 2010
    Date of Patent: September 20, 2011
    Assignee: Northrop Grumman Systems Corporation
    Inventors: Aaron A. Pesetski, James E. Baumgardner
  • Patent number: 8018244
    Abstract: An architecture for a quantum processor may include a set of superconducting flux qubits operated as computation qubits and a set of superconducting flux qubits operated as latching qubits. Latching qubits may include a first closed superconducting loop with serially coupled superconducting inductors, interrupted by a split junction loop with at least two Josephson junctions; and a clock signal input structure configured to couple clock signals to the split junction loop. Flux-based superconducting shift registers may be formed from latching qubits and sets of dummy latching qubits. The devices may include clock lines to clock signals to latch the latching qubits. Thus, latching qubits may be used to program and configure computation qubits in a quantum processor.
    Type: Grant
    Filed: October 21, 2010
    Date of Patent: September 13, 2011
    Assignee: D-Wave Systems Inc.
    Inventor: Andrew Joseph Berkley
  • Patent number: 7977964
    Abstract: Superconducting single flux quantum circuits are disclosed herein, each having at least one Josephson junction which will flip when the current through it exceeds a critical current. Bias current for the Josephson junction is provided by a biasing transformer instead of a resistor. The lack of any bias resistors ensures that unwanted power dissipation is eliminated.
    Type: Grant
    Filed: March 5, 2010
    Date of Patent: July 12, 2011
    Assignee: Northrop Grumman Systems Corporation
    Inventor: Quentin P. Herr
  • Patent number: 7906991
    Abstract: Nanotube based logic driver circuits. These include pull-up driver circuits, push-pull driver circuits, tristate driver circuits, among others. Under one embodiment, an off-chip driver circuit includes a differential input having first and second signal links, each coupled to a respective one of two differential, on-chip signals. At least one output link is connectable to an off-chip impedance load, and at least one switching element has an input node, an output node, a nanotube channel element, and a control structure disposed in relation to the nanotube channel element to controllably form and unform an electrically conductive channel between said input node and said output node. The input node is coupled to a reference signal and the control structure is coupled to the first and second signal links. The output node is coupled to the output link, and the channel element is sized to carry sufficient current to drive said off-chip impedance load.
    Type: Grant
    Filed: August 31, 2007
    Date of Patent: March 15, 2011
    Assignee: Nantero, Inc.
    Inventor: Claude L. Bertin
  • Patent number: 7893708
    Abstract: Systems and methods are provided for performing a quantum gate operation. A first classical control parameter is associated with a first qubit and coupled to a resonator. The first classical control parameter is transitioned from a first control value to a second control value. The first classical control parameter is returned from the second control value to the first control value via an adiabatic sweep operation, as to permit a transfer of energy between the first qubit and the resonator that causes a change in the quantum state of the qubit and resonator.
    Type: Grant
    Filed: March 29, 2010
    Date of Patent: February 22, 2011
    Assignee: Northrop Grumman Systems Corporation
    Inventors: James E. Baumgardner, Aaron A. Pesetski
  • Patent number: 7880496
    Abstract: A novel conservative gate especially suiting a Quantum Dot Cellular Automata (QCA) majority voter-based design. The input-to-output mapping of the novel conservative QCA (CQCA) gate is: P=A; Q=AB+BC+AC [MV(A,B,C)]; R=A?B+A?C+BC [MV(A?,B,C)], where A, B, C are inputs and P, Q, R are outputs, respectively. A method of transferring information in a quantum-dot cellular automata device is also provided.
    Type: Grant
    Filed: February 9, 2010
    Date of Patent: February 1, 2011
    Assignee: University of South Florida
    Inventors: Nagarajan Ranganathan, Himanshu Thapliyal
  • Patent number: 7868645
    Abstract: In one embodiment, the disclosure relates to a single flux quantum (SFQ) signal transmission line powered by an AC power source. The AC power source supplies power to a transformer having a primary winding and a secondary winding. The primary winding receives the AC signal and the secondary winding communicates the signal to the SFQ transmission line. The transmission line can optionally include an input filter circuit for receiving the incoming SFQ pulse. The filter circuit can have a resistor and an inductor connected in parallel. In an alternative arrangement, the filter circuit can comprise of an inductor. A first Josephson junction can be connected to the filter circuit and to the secondary winding. The Josephson junction triggers in response to the incoming SFQ pulse and regenerates a pulse signal in response to a power discharge from the secondary winding.
    Type: Grant
    Filed: May 5, 2010
    Date of Patent: January 11, 2011
    Assignee: Northrop Grumman Systems Corporation
    Inventors: Quentin P. Herr, James E. Baumgardner, Anna Y. Herr
  • Patent number: 7852106
    Abstract: In one embodiment, the disclosure relates to a single flux quantum (SFQ) signal transmission line powered by an AC power source. The AC power source supplies power to a transformer having a primary winding and a secondary winding. The primary winding receives the AC signal and the secondary winding communicates the signal to the SFQ transmission line. The transmission line can optionally include an input filter circuit for receiving the incoming SFQ pulse. The filter circuit can have a resistor and an inductor connected in parallel. In an alternative arrangement, the filter circuit can comprise of an inductor. A first Josephson junction can be connected to the filter circuit and to the secondary winding. The Josephson junction triggers in response to the incoming SFQ pulse and regenerates a pulse signal in response to a power discharge from the secondary winding.
    Type: Grant
    Filed: May 4, 2010
    Date of Patent: December 14, 2010
    Assignee: Northrop Grumman Systems Corporation
    Inventors: Quentin P. Herr, James E. Baumgardner, Anna Y. Herr
  • Patent number: 7843209
    Abstract: An architecture for a quantum processor may include a set of superconducting flux qubits operated as computation qubits and a set of superconducting flux qubits operated as latching qubits. Latching qubits may include a first closed superconducting loop with serially coupled superconducting inductors, interrupted by a split junction loop with at least two Josephson junctions; and a clock signal input structure configured to couple clock signals to the split junction loop. Flux-based superconducting shift registers may be formed from latching qubits and sets of dummy latching qubits. The devices may include clock lines to clock signals to latch the latching qubits. Thus, latching qubits may be used to program and configure computation qubits in a quantum processor.
    Type: Grant
    Filed: April 25, 2008
    Date of Patent: November 30, 2010
    Assignee: D-Wave Systems Inc.
    Inventor: Andrew Joseph Berkley
  • Patent number: 7786748
    Abstract: In one embodiment, the disclosure relates to a single-flux quantum logic gate capable of providing output from one of the two inputs, which is also known as the A and NOT B gate. The logic gate includes a first input gate and a second input gate for respectively receiving a first input pulse and a second input pulse. An output gate is wired in parallel with the first input gate. A first Josephson junction and a second Josephson junction are connected to the first input gate and the second input gate, respectively. A cross-coupled transformer is also provided. The cross-coupled transformer diverts the first pulse from the output gate if the second pulse is detected at the second input gate. In an optional embodiment, the first Josephson junction has a first critical current which is selected to be less than the critical current of the second Josephson junction.
    Type: Grant
    Filed: May 15, 2009
    Date of Patent: August 31, 2010
    Assignee: Northrop Grumman Systems Corporation
    Inventor: Quentin P. Herr
  • Patent number: 7782077
    Abstract: In one embodiment, the disclosure relates to a single flux quantum (SFQ) signal transmission line powered by an AC power source. The AC power source supplies power to a transformer having a primary winding and a secondary winding. The primary winding receives the AC signal and the secondary winding communicates the signal to the SFQ transmission line. The transmission line can optionally include an input filter circuit for receiving the incoming SFQ pulse. The filter circuit can have a resistor and an inductor connected in parallel. In an alternative arrangement, the filter circuit can comprise of an inductor. A first Josephson junction can be connected to the filter circuit and to the secondary winding. The Josephson junction triggers in response to the incoming SFQ pulse and regenerates a pulse signal in response to a power discharge from the secondary winding.
    Type: Grant
    Filed: May 7, 2009
    Date of Patent: August 24, 2010
    Assignee: Northrop Grumman Systems Corporation
    Inventors: Quentin P. Herr, James E. Baumgardner, Anna Y. Herr
  • Publication number: 20100182039
    Abstract: Systems and methods are provided for performing a quantum gate operation. A first classical control parameter is associated with a first qubit and coupled to a resonator. The first classical control parameter is transitioned from a first control value to a second control value. The first classical control parameter is returned from the second control value to the first control value via an adiabatic sweep operation, as to permit a transfer of energy between the first qubit and the resonator that causes a change in the quantum state of the qubit and resonator.
    Type: Application
    Filed: March 29, 2010
    Publication date: July 22, 2010
    Inventors: James E. Baumgardner, Aaron A. Pesetski
  • Patent number: 7724020
    Abstract: Superconducting single flux quantum circuits are disclosed herein, each having at least one Josephson junction which will flip when the current through it exceeds a critical current. Bias current for the Josephson junction is provided by a biasing transformer instead of a resistor. The lack of any bias resistors ensures that unwanted power dissipation is eliminated.
    Type: Grant
    Filed: December 13, 2007
    Date of Patent: May 25, 2010
    Assignee: Northrop Grumman Systems Corporation
    Inventor: Quentin P. Herr
  • Patent number: 7714605
    Abstract: A quantum logic gate is formed from multiple qubits coupled to a common resonator, wherein quantum states in the qubits are transferred to the resonator by transitioning a classical control parameter between control points at a selected one of slow and fast transition speeds, relative to the characteristic energy of the coupling, whereby a slow transition speed exchanges energy states of a qubit and the resonator, and a fast transition speed preserves the energy states of a qubit and the resonator.
    Type: Grant
    Filed: January 16, 2009
    Date of Patent: May 11, 2010
    Assignee: Northrop Grumman Systems Corporation
    Inventors: James E. Baumgardner, Aaron A. Pesetski
  • Patent number: 7659750
    Abstract: A thermal electric (TE) binary NOR gate logic circuit is provided with a method for NOR logic gating. The method accepts a first input voltage representing an input binary logic state and generates a first thermal electric (TE) temperature in response to the first input voltage. A second input voltage is accepted representing an input binary logic state, and a second TE temperature is generated in response to the second input voltage. In response to the first and second TE temperatures, a NOR logic state output voltage is generated. More explicitly, a first control voltage is generated in response to the first TE temperature, and a second control voltage is generated in response to the second TE temperature. Then, a third TE temperature is generated in response to the first and second control voltages, which in turn generates the output voltage.
    Type: Grant
    Filed: May 13, 2008
    Date of Patent: February 9, 2010
    Assignee: Applied Micro Circuits Corporation
    Inventor: Joseph Martin Patterson
  • Patent number: 7602218
    Abstract: A thermal electric (TE) binary NAND gate logic circuit is provided with a method for NAND logic gating. The method accepts a first input voltage representing an input binary logic state and generates a first thermal electric (TE) temperature in response to the first input voltage. A second input voltage is accepted representing an input binary logic state, and a second TE temperature is generated in response to the second input voltage. In response to the first and second TE temperatures, a NAND logic state output voltage is generated. More explicitly, a first control voltage is generated in response to the first TE temperature, and a second control voltage is generated in response to the second TE temperature. Then, a third TE temperature is generated in response to the first and second control voltages, which in turn generates the output voltage.
    Type: Grant
    Filed: November 13, 2008
    Date of Patent: October 13, 2009
    Assignee: Applied Micro Circuits Corporation
    Inventor: Joseph Martin Patterson
  • Patent number: 7564267
    Abstract: A thermal electric binary logic circuit is provided along with a method for switching a thermal electric binary logic circuit. The method accepts an input voltage representing an input logic state and generates a thermal electric (TE) temperature value in response to the input voltage. Then, in response to the TE temperature value, a TE voltage is generated and supplied as an output voltage representing an output logic state. In one aspect, a first TE element is connected to the input voltage and to a current source/sink having an intermediate voltage. As a result, the first TE element generates a first temperature reference. A second TE thermally is connected to the first TE, electrically connected to a first voltage reference, and electrically connected to an output to supply the output voltage. As a result, a first voltage varies across the second TE in response to the first temperature.
    Type: Grant
    Filed: February 29, 2008
    Date of Patent: July 21, 2009
    Assignee: Sharp Laboratories of America, Inc.
    Inventor: Joseph Martin Patterson
  • Patent number: 7498832
    Abstract: A quantum logic gate is formed from multiple qubits coupled to a common resonator, wherein quantum states in the qubits are transferred to the resonator by transitioning a classical control parameter between control points at a selected one of slow and fast transition speeds, relative to the characteristic energy of the coupling, whereby a slow transition speed exchanges energy states of a qubit and the resonator, and a fast transition speed preserves the energy states of a qubit and the resonator.
    Type: Grant
    Filed: August 3, 2007
    Date of Patent: March 3, 2009
    Assignee: Northrop Grumman Systems Corporation
    Inventors: James E. Baumgardner, Aaron A. Pesetski
  • Patent number: 7362125
    Abstract: Routing and distribution of radio-frequency (RF) signals is commonly achieved in the analog domain. However, improved performance and simplified circuit architectures may be obtained by first digitizing the RF signal, and then carrying out all routing in the digital domain. A new generation of scalable digital switches has been developed, which routes both the data and clock signals together, this being necessary to maintain the integrity of the digitized RF signal. Given the extremely high switching speeds necessary for these applications (tens of GHz), this is implemented using Rapid-Single-Flux-Quantum (RSFQ) logic with superconducting integrated circuits. Such a digital switch matrix may be applied to either the receiver or transmitter components of an advanced multi-band, multi-channel digital transceiver system, and is compatible with routing of signals with different clock frequencies simultaneously within the same switch matrix.
    Type: Grant
    Filed: June 14, 2006
    Date of Patent: April 22, 2008
    Assignee: Hypres, Inc.
    Inventors: Deepnarayan Gupta, Alexander F. Kirichenko
  • Patent number: 7212026
    Abstract: Spin-orbital quantum cellular automata logic devices and integrated circuits in the form of a substrate having a thin film of material on the substrate having strongly coupled spin-orbital states, the thin film being patterned to define at least one input and at least one output, and to perform at least one logic operation by associated arrangement of the spin-orbital states between the input and the output. The logic devices and integrated circuits further include an input device at each input to define the spin-orbital states at each input, and an output sensor at each output for sensing the spin-orbital states of the thin film at the output. In an integrated circuit, the output of one gate or circuit, in the form of the ferromagnetically aligned spins, can be directly coupled to the next gate or circuit, so that entire circuits can be fabricated and effectively interconnected, only requiring interfacing for overall.
    Type: Grant
    Filed: October 29, 2004
    Date of Patent: May 1, 2007
    Assignee: Intel Corporation
    Inventors: George I. Bourianoff, Dmitri E. Nikonov, Jun-Fei Zheng
  • Patent number: 6734699
    Abstract: A superconducting self-clocked complementary SFQ logic family. The basic element of the circuit is a plurality of Josephson junctions and a control inductance coupled across a pair of voltage rails. An important aspect of the invention relates to the use of voltage biasing for the Josephson junctions, which provides several benefits. First, voltage biasing eliminates the need for biasing resistors as used in constant current mode devices. Such biasing resistors are known to be the dominant source of power dissipation in such logic circuits. Elimination of the biasing resistors thus reduce the power dissipation to the lowest possible value to that of the power dissipation of the switching devices themselves. In addition, the voltage biasing takes advantage of the voltage to frequency relationship of Josephson junctions and automatically establishes a global clock at the Josephson frequency without the need for extra circuitry; thus increasing the practical clock rate.
    Type: Grant
    Filed: July 14, 1999
    Date of Patent: May 11, 2004
    Assignee: Northrop Grumman Corporation
    Inventors: Quentin P. Herr, Arnold H. Silver