Abstract: A low-leakage resistive random access memory cell includes a complementary pair of bit lines and a switch node. A first ReRAM device is connected to a first one of the bit lines. A p-channel transistor has a source connected to the ReRAM device, a drain connected to the switch node, and a gate connected to a bias potential. A second ReRAM device is connected to a second one of the bit lines. An n-channel transistor has a source connected to the ReRAM device a drain connected to the switch node, and a gate connected to a bias potential.

Abstract: A method for an FPGA includes coupling a first electrode of a first resistive element to a first input voltage, coupling a second electrode of a second resistive element to a second input voltage, applying a first programming voltage to a shared node of a second electrode of the first resistive element, a first electrode of the second resistive element, and to a gate of a transistor element, and changing a resistance state of the first resistive element to a low resistance state while maintaining a resistance state of the second resistive element, when a voltage difference between the first programming voltage at the second terminal and the first input voltage at the first terminal exceeds a programming voltage associated with the first resistive element.

Abstract: An electrical grounding device can have a grounding plate and an insulated connecting wire. Having an insulated connecting wire reduces or prevents corrosion of the connecting wire by the surrounding underground soil. A grounding assembly is also provided and can have such a grounding device. The grounding assembly can include additional grounding devices which can also have an insulated connecting wire. A method of measuring resistance to ground of a grounding device of a grounding assembly having a multiple grounding devices and one or more bonding wires routed through a conduit is also disclosed.

Abstract: A circuit arrangement for producing short electrical pulses, including a logic gate (1) with a very short gate transit time and having a clock signal being supplied to a trigger input (2) of the logic gate (1) as a trigger signal. An output signal based on the trigger signal is generated as a short electrical pulse at an output (3) or at one output (3 or 4) or at both outputs (3 and 4) of the logic gate (1).

Abstract: The present invention switches between a first clock signal (CLK0) and a second clock signal (CLK1). Each input signal is buffered by a corresponding tristate buffer (TBUF0, TBUF1). A multiplexer (MUX) receives the tristate buffer outputs and selects one clock signal in response to a multiplexer control signal (MUX_SEL). A control stage (CONTROL) received a clock selection signal (SEL) and provides multiplexer control signal (MUX_SEL). A change in multiplexer control signal (MUX_SEL) is triggered by a next edge of target clock (CLK1) following a delay. This prevents glitches in the output signal.

Abstract: A logic circuit for delaying a signal input thereto by a number of clock cycles X is described. In one embodiment, the logic circuit comprises a demultiplexer (“DEMUX”) which includes an input for receiving the signal and N outputs; a register array comprising at least X registers, wherein each of the N outputs of the DEMUX is connected to a corresponding one of the X registers; and a multiplexer (“MUX”) comprising M inputs, wherein each of the M inputs is connected to one of the registers.

Abstract: Methods and apparatus to provide per die temperature programming for thermally efficient integrated circuit (IC) operation are described. In some embodiments, the junction temperature of an IC component is determined, e.g., to reduce power consumption and/or improve performance. Other embodiments are also described.

Abstract: The invention provides a logic circuit to identify time difference between signals having a variation in delay, and an integrated circuit which can evaluate variations in delay among internal signals. By using a logic circuit which outputs different number of pulse depending on a relationship of delay when a first signal and a second signal which are a pair of digital signals having a time difference are inputted, variations in delay of internal signals of an integrated circuit can be evaluated. Specifically, an output signal is generated by a logical operation of values of the first signal and second signal in a period in which the first signal is High and the second signal is Low, and values of a first signal and a second signal immediately before them by using a latch circuit. Further, by using a delay circuit which can set a delay time of an input signal, time difference between signals can be evaluated quantitavely.

Abstract: By using a first delay circuit that delays by a predetermined time a reference pulse signal having a constant pulse width and a second delay circuit that delays by an arbitrary time the output signal of the first delay circuit, a voltage conversion circuit generates an output pulse signal having a variable pulse period, and varies its output voltage according to the pulse period of this output pulse signal.

Abstract: A logic circuit for delaying a signal input thereto a specified number of clock cycles X, wherein X is between 1 and 2N is described. In one embodiment, the logic circuit comprises a demultiplexer (“DEMUX”) comprising an input for receiving the signal and N outputs; a register array comprising 2N clocked registers, wherein each of a first N of the clocked registers is connected to one of the N outputs of the DEMUX and wherein data is shifted out of one clocked register to a next clocked register on each clock cycle; and a multiplexer (“MUX”) comprising M inputs, wherein each of the M inputs is connected to one of the clocked registers.

Abstract: Systems and methods are disclosed for controlling an associated circuit. A clock waveform that transitions between normally high and low levels over a cycle in a first operating mode is provided to the associated circuit. The clock waveform is modified to include an intermediate level between the normally high and low levels over a cycle in a second operating mode.

Abstract: A method and apparatus for electrical parallel processing logic operations in which one and zero are represented by presence and absence, respectively, of a sinusoidal wavetrain. Different frequency information channels can be handled simultaneously and independently. The form of data representation is strictly preserved from gate input to output thereby ensuring compatibility with conventional memory, counter, register, and other digital logic design. Input impedance is high and output impedance is minuscule, conducive to high fan out. Because arbitrarily sophisticated circuits, including full scale computers, may be essentially entirely built out of Boolean logic gate combinations, the proposed parallel processing logic enables parallel processing in computers without recourse to timesharing, redundant multiprocessor architecture, or still speculative “quantum computer” hardware.

Abstract: A receiver performs on data to clock skew compensation by compensating ISI between signals, the ISI being caused by a bandwidth limitation generated in case of chip-to-chip communications in a digital system. A problem of an attenuation of a high frequency signal may occur due to an attenuation in a channel in case of a transmission of a signal at a high speed in the digital system. Therefore there is a limitation in transmitting data at a high speed. The receiver provides a circuit for applying an equalizing technology at the terminal of the receiver. And by compensating for the attenuation of a high frequency component of the signal by using the circuit, the transmission of a signal at a high speed is realized by over-sampling the signal and compensating the data to clock skew.

Abstract: A cascadable divide-by-two binary counter circuit (120) that has particular application for use as a synchronous divider circuit (50, 54) in a phase lock loop (26). The counter circuit (120) employs a D flip-flop (122) that receives a D input and provides a Q output. A first AND gate (124) is responsive to a P input and a Q input, where the Q input is the output from a preceding counter circuit and the P input is the state of all of the preceding counter circuits. The output of the AND gate (124) is applied to an exclusive-OR gate (126) along with the Q output of the flip-flop (122). The output of the exclusive-OR gate (126) is applied to one input of a second AND gate (128). The other input of the second AND gate (128) is a reset signal and the output of the second AND gate (128) is the D input of the flip-flop (122). A decoder (142) is programmed to provide the reset signal when the desired count is reached.

Abstract: A system for controlling the duty cycle of a clock signal. The system includes a duty cycle adjustment circuit that receives an input clock signal and generates an output clock signal. The duty cycle adjustment circuit charges a capacitor when the input clock signal has a first logic level and discharges the capacitor with the input clock signal has a second logic level. The rates of charge and discharge are controlled by first and second control signals. When the capacitor has been charged to a first transition level, the output clock signal transitions to a first logic level, and when the capacitor has been discharged to a second transition level, the output clock signal transitions to a second logic level. The first and second control signals are supplied by a feedback circuit, which is implemented using an integrator circuit that receives the output clock signal and generates a feedback signal indicative of the duty cycle of the output clock signal.

Abstract: A new family of current mode logic (CML) gates (14) which, in one embodiment includes OR/NOR and AND/NAND gates, as well as more complex logic functions. The circuit uses a complementary signal to drive the gate of a feedback transistor (19) which has the effect of pseudo differential operation. Although it uses only single-ended inputs (A, B), because of this feedback aspect, the circuit has many of the advantages of a differential circuit such as low-voltage operation, higher immunity to noise, and less sensitivity to parasitic elements.

Abstract: A transition splitting apparatus and method reduce a maximum transition rate of a digital signal. The apparatus and method are particularly useful for digital signal processing in communications and for performing digital transition timing testing on a device under test. The apparatus and method split a digital signal into two or more signals, while preserving the relative timing of transitions in the digital signal. A high frequency signal is partitioned by the apparatus and method into a plurality of equivalent lower frequency signals without loss of transition timing information. The apparatus is implemented with readily available components. The maximum transition rate of a digital signal is reduced by a factor of two or more, and is proportional to the number of output signals. A plurality of the apparatuses may be cascaded together into a system to achieve even greater reductions in maximum transition rates.

Abstract: A microprocessor circuit, and a method of monitoring and controlling an outside device using a single pin of a microprocessor, are disclosed. The microprocessor circuit includes a microprocessor having a pin, a first junction and a second junction that are both electrically coupled to the pin, and a capacitor by which the second junction is electrically coupled to the pin. The microprocessor circuit is capable of receiving at the first junction an input signal and providing a related signal to the pin in response to the input signal. The capacitor prevents signals below a certain frequency level from being communicated from the pin to the second junction. The microprocessor is capable of generating a control signal at the pin that includes at least one component that is above the certain frequency level, so that the generating of the control signal produces an output signal at the second junction.

Abstract: A jitter detecting circuit firstly compares a target signal with a reference clock signal to see whether or not a phase difference takes place between the target signal and the reference clock signal, and, thereafter, the phase difference in each clock cycle is compared with the phase difference in the previous clock cycle for producing a detecting signal representative of cycle-to-cycle jitter when the phase difference is varied.

Abstract: A phase dependent splitter/combiner 4-port coupler device is composed of two duplicating stages and a cross-over stage and provides the phase dependent splitting and combining functionality of a 4-port coupler without the ambiguity of the coupling coefficient of coupled mode analysis. The 4-port coupler device receives two input signals and produces two output signals. Each duplicating stage consists of an amplifier and a splitter and produces the two duplicated signals. The cross-over stage receives the four duplicated signals from the two duplicating stages, consists of a phase inverter and two combiners, and produces two output signals. If the combiners are 3 dB couplers, the 4-port coupler device performs a splitter operation or a combiner operation. If the combiners are non-3 dB couplers, the 4-port coupler device performs a replicator operation or a combiner operation. The device can be used for optic, including infrared and ultraviolet, or microwave signals.

Abstract: A data input/output circuit preferably used in a fast interface system such as Rambus™ interface or SyncLink™ interface for transmitting and/or receiving data in synchronization with a supplied clock. The data input/output circuit has a phase locked loop (PLL) circuit for differentially receiving the clock and a reference voltage to generate an internal clock having a predetermined phase delay with respect to the supplied clock, a register for storing setting data for changeably setting the level of the reference voltage, and a level shift circuit for setting the level of the reference voltage to be supplied to the PLL circuit to a predetermined value in accordance with the setting data stored in the register, and performs actual data transmission/reception processing in synchronization with the internal clock.

Abstract: A pulse width modulation circuit utilizes a clock divider to generate a plurality of clocks to be used by a plurality of delay blocks. Each delay block has plurality of delay elements each of which receives one the plurality of clocks. Each delay block receives a delay data, selects a number of the plurality of clocks based on the delay data and activates the respective delay elements for delaying its input signal.

Abstract: Any one of several improved devices capable of implementing microwave phase logic (MPL) operating at gigabits per second rates comprises either at least one of means performing the function of a multigate microwave-monolithic-integrated-circuit (MMIC) field-effect transistor (FET), or a pair of doubly-balanced mixers, in which each of the mixers includes an RF port, a local-oscillator (LO) port and an IF port, and the IF port of a first of the doubly-balanced mixers is directly connected to the IF port of a second of the doubly-balanced mixers.

Abstract: Any one of several improved devices capable of implementing microwave phase logic (MPL) operating at gigabits per second rates comprises either at least one of means performing the function of a multigate microwave-monolithic-integrated-circuit (MMIC) field-effect transistor (FET), or a pair of doubly-balanced mixers, in which each of the mixers includes an RF port, a local-oscillator (LO) port and an IF port, and the IF port of a first of the doubly-balanced mixers is directly connected to the IF port of a second of the doubly-balanced mixers.

Abstract: The present invention is an adaptable pre-matched tuner system and calibration method for measuring reflection factors above ?=0.85 for a DUT. The system includes a first and second large-band microwave tuners connected in series, the first and second large-band tuners being mechanically and electronically integrated; and a controller for controlling the two large-band tuners. The first tuner is adapted to act as a pre-matching tuner and the second tuner is adapted to investigate an area of a Smith Chart that is difficult to characterise with a single tuner, so that the combination of the first and second large-band tuners permits the measurement of reflection factors above ?=0.85. The pre-matched tuner system allows the generation of a very high reflection factor at any point of the reflection factor plane (Smith Chart).