Abstract: A register with data retention includes a master-slave flip-flop, a balloon latch, and a level shifter. The master-slave flip-flop is supplied by a first power voltage. The balloon latch is supplied by a second power voltage. The second power voltage is independent of the first power voltage. The level shifter provides a voltage conversion between the master-slave flip-flop and the balloon latch. A data is stored in the master-slave flip-flop. When the first power voltage is disabled, the balloon latch is configured to temporarily retain the data.

Abstract: The present disclosure relates to a fractional frequency divider, a radio frequency transceiver, and a method of configuring a phase delay in the fractional frequency divider. The fractional frequency divider comprises a counter, a multiplexer, and a delay module. The method is applicable to the fractional frequency divider. The radio frequency transceiver comprises the fractional frequency divider, and the fractional frequency divider adopts the method. According to the aforesaid technical solution, the present disclosure has advantages as follows: the embodiments of the present disclosure can minimize the timing inaccuracy and suppress the output jitter and output spurs; and the embodiments of the present disclosure can effectively extend the operating frequency range of the fractional frequency divider.

Abstract: A system for generating secondary clock signals from a primary clock signal includes a dithered clock divider which has a first input adapted to receive the primary clock signal and a second input adapted to receive a random division ratio. The dithered clock divider provides a dithered clock signal. The system includes a multi-phase clock generator which has a first input adapted to receive the primary clock signal, a second input adapted to receive the dithered clock signal, and a third input adapted to receive a pseudo-random pattern. The multi-phase clock generator provides the secondary clock signals from multiple phases of the dithered clock signal. The system includes a pseudo-random pattern generator which provides the pseudo-random pattern.

Abstract: A hybrid true single-phase clock (H-TSPC) circuit includes a first logic circuit comprising non-ratio (NR) logic, a first mode switching device coupled to an output of the first logic circuit, a second logic circuit comprising ratio (R) logic, the second logic circuit configured to receive an output of the first logic circuit, a second mode switching device coupled to an output of the second logic circuit, a third logic circuit comprising non-ratio (NR) logic, the third logic circuit configured to receive an output of the second logic circuit, and a third mode switching device coupled to an output of the third logic circuit, wherein the first logic circuit, second logic circuit, and third logic circuit are configured in a ring.

Abstract: A counting device, including multiple counting circuit stages and a first logic operation circuit, is provided. The counting circuit stages are serially coupled in sequence. A first counting circuit stage performs a counting action according to a first clock signal and generates a first counting result. Second to Nth counting circuit stages perform counting actions according to a second clock signal, where N is a positive integer greater than 2. The first logic operation circuit provides the first counting result to be the second clock signal according to an indication signal.

Abstract: Disclosed are irrigation systems and methods, which can be used for rectal/anal irrigation. One example system includes a reservoir for an irrigating liquid, a probe for arrangement in a user, tubing providing fluid communication between the reservoir and probe, and an electrical pump for indirectly pumping irrigation liquid from the reservoir to the probe through said tubing. The electrical pump is controllable to assume a plurality of predetermined flow rates. The system includes an electrically operable valve to continuously control a degree of openness of the tubing, a flow sensor to measure an actual flow rate of the irrigation liquid in the probe, and a controller to obtain a desired flow rate, and control the flow rate of the electric pump to one of the plurality of flow rates exceeding the desired flow rate, and to continuously regulate the electrically operable valve based on the measured actual flow rate.

Abstract: A SPI master may configure a set of hardware registers associated with a SPI client with a set of communication parameters. The SPI master may send a message to the SPI client. The SPI master may periodically ping the SPI client until the SPI master receives an acknowledgement message from the SPI client in response to the message from the SPI master. The SPI master may periodically ping the SPI client based upon the set of communication parameters. The SPI client may transmit the acknowledgement message to the SPI master based upon the set of communication parameters. The SPI master may receive the acknowledgement message from the SPI client. The SPI master may determine a status of a read operation or a write operation associated with the message based upon the acknowledgement message.

Abstract: The present invention describes a tag comprising a magnetic element in the form of a microwire of 80-250 microns with giant magnetoimpedance which, when joined to an object, allows for the wireless detection of same by modulating the reflectivity of the microwire. Detection is performed by using a system that emits an electromagnetic wave that has a frequency between 1 and 20 GHz and a low frequency magnetic field (0.01-50 Hz), and detects the modulation of the reflectivity of the microwire. Thus, objects at distances greater than 1 m can be detected.

Abstract: A low power signal generator and a method for generating at least one source signal based on a reference signal having a reference frequency is presented. The signal generator has a divider circuit having a resonant frequency. The generator has an adjuster adapted to adjust the resonant frequency. The divider circuit has an input to receive the reference signal and an output for providing the source signal. The divider circuit is adapted to divide the reference frequency of the reference signal by a coefficient, such that the source signal has a source frequency that is less than the reference frequency.

Abstract: A high linearity phase interpolator (PI) is disclosed. A phase value parameter indicative of a desired phase difference between an output signal and an input clock signal edge may be provided by control logic. A first capacitor may be charged for a first period of time with a first current that is proportional to the phase value parameter to produce a first voltage on the capacitor that is proportional to the phase value parameter. The first capacitor may be further charged for a second period of time with a second current that has a constant value to form a voltage ramp offset by the first voltage. A reference voltage may be compared to the voltage ramp during the second period of time. The output signal may be asserted at a time when the voltage ramp equals the reference voltage.

Abstract: A frequency divider unit to receive an oscillating signal and to update, at an output of the frequency divider unit, a frequency-divided oscillating signal is presented. The frequency divider unit has a first clocked signal inverter to update, clocked based on the oscillating signal, a first intermediate signal at an output of the first clocked signal inverter. The frequency divider unit has a second clocked signal inverter, wherein the output of the first clocked signal inverter may be connected to an input of the second clocked signal inverter, and wherein the second clocked signal inverter updates, clocked based on the oscillating signal, a second intermediate signal at an output of the second clocked signal inverter. The frequency divider unit has a continuously operating signal inverter coupled between the output of the second clocked signal inverter and the input of the first clocked signal inverter.

Abstract: The present disclosure relates to a structure including an adaptive noise canceller circuit which is configured to suppress noise in a feedback sigma-delta modulator circuit and provide real-time tracking of a noise cancellation signal.

Abstract: A frequency generator, includes a control unit, configured to receive an input signal to generate a divisor signal, a phase signal and a circulation signal; a frequency divider, configured to receive the input signal and perform an integer division to the input signal according to the divisor signal, so as to generate a frequency division signal; a circulating delay circuit, coupled to the frequency divider and configured to perform at least one circulating operation to the frequency division signal, and for each circulating operation, generate at least one phase delay signal; a first multiplexer, coupled to the circulating delay circuit and configured to select one signal from the frequency division signal and the at least one phase delay signal according to the phase signal, so as to generate a multiplexed signal; and a retimer, coupled to the first multiplexer and configured to generate an output signal.

Abstract: A radar device for transmitting a signal in a frequency range with a control system and an oscillator. An input of the oscillator is connected to the control system via a converter. The oscillator can be activated by the control system to generate the signal and the signal generated by the oscillator can be tapped at an output of the oscillator, with at least one transmission antenna for transmitting the signal at the output of the oscillator. The transmission antenna is connected to the output of the oscillator, with at least one receive channel for receiving a receive signal, for processing the receive signal and for forwarding the processed receive signal to the control system. The receive channel features at least one receive antenna and a mixer for mixing the receive signal with the signal at the output of the oscillator. The mixer is connected to the output of the oscillator. A frequency divider is provided that feeds signals from the oscillator to a frequency counter.

Abstract: An electronic latch circuit, a 4-phase signal generator, a multi-stage frequency divider and a poly-phase signal generator are disclosed. The electronic latch circuit comprises an output circuit comprising a first output and a second output. The electronic latch circuit further comprises an input circuit comprising a first input, a second input and a clock signal input. The electronic latch circuit is configured to change state based on the input signals' level at the inputs of the input circuit and a present state of the output circuit. The 4-phase signal generator is built with two electronic latch circuits. The multi-stage frequency dividers and poly-phase signal generators comprise a plurality of the electronic latch circuits and 4-phase signal generators.

Abstract: An amplification circuit is provided. The amplification circuit may include an amplification stage configured to amplify a first signal and a second signal, and generate third and fourth signals while in a first operation period. The amplification circuit may include a latch stage configured to latch the third and fourth signals while in a in a second operation period. The amplification circuit may supply a low voltage to the amplification stage during the first operation period, the low voltage to the latch stage during the second operation period, a high voltage to the amplification stage during the first operation period, and the high voltage to the latch stage during the second operation period.

Abstract: A method includes transmitting a first magnetic detection signal at a first magnetic frequency and transmitting a second magnetic detection signal at a second magnetic frequency. The method also includes detecting a first response from a first magnetic material to the first magnetic detection signal and detecting a second response from the second magnetic material to the second magnetic detection signal. Each of the first magnetic material and the second magnetic material is associated with a substrate of the coded tag. The method further includes determining that the coded tag encodes first information based on detecting the first response and determining that the coded tag encodes second information based on detecting the second response.

Abstract: Some embodiments include apparatus and methods using a first latch in a decision feedback equalizer (DFE), a second latch in the DFE, and circuity coupled to the first and second latches. The second latch includes a first input node coupled to an output node of the first latch. The circuitry includes a first input node coupled to the first output node, a second input node coupled to a second output node of the second latch, and an output node to provide information having a first output value based on first values of information at the first and second output nodes and a second output value based on second values of information at the first and second output nodes.

Abstract: A phase continuity architecture is provided to maintain the phase continuity for a post divider output signal from a post divider that post divides a PLL output signal. A pulse swallower removes a pulse from the PLL output signal responsive to an edge is a divided feedback clock signal. A sampler samples the post divider output signal responsive to a detection of the missing pulse to determine a phase relationship between the post divider output signal and the divided feedback clock signal.

Abstract: A stringless portable electronic training device for a stringed instrument, such as a contrabass, has the shape of a fingerboard with just enough neck to provide realistic left hand position, and just enough body to contain actuators corresponding with strings, electronics, a speaker, and an output jack. On the fingerboard are rows of push buttons corresponding with the location of the notes. The push buttons are held down to select notes which are sounded by actuators at a lower end of the fingerboard. Actuating without the pressing of a button produces the note of the open string. The actuators may include a set of flippers that replicate the plucking of strings and a set of elongated buttons that sustain a bowed sound as they are pressed down. The sound is produced electronically through a built-in speaker and/or output jack.

Abstract: A detection system is provided for detecting a musical note played on a string instrument having a fretboard provided with a plurality of conductive frets and conductive strings. The system includes at least one conductor coupled to each of the frets; an inverter having a first terminal coupled to the conductor and a second terminal coupled to the conductive string, the inverter being configured to logically invert a signal transmitted therethrough, such that when the conductive string is pressed against one of the frets allowing thereby for a signal to be transmitted therethrough, the signal is sequentially inverted between two logical states at a frequency being dependent on the distance between the inverter and the fret; a frequency detector configured to measure the frequency; and a controller configured for determining the location of the fret along the fretboard in accordance with the frequency, and to thereby detect the musical note.

Abstract: This disclosure provides an apparatus for generating a spread-spectrum clock, which comprises: a multi-phase clock generator generating a pre-determined number of first clock signals having substantially identical period and different phases; a spread spectrum clock controller producing an instruction signal according to a first pre-determined spread spectrum target; and a clock selector receiving the instruction signal and dynamically selecting a clock signal from the first clock signals according to the instruction signal so as to produce a first spread spectrum signal; wherein the first spread spectrum signal has a spread spectrum corresponding to the first pre-determined spread spectrum target.

Abstract: A three-dimensional integrated circuit having a dual or multiple power domain is capable of less energy consumption operation under a given clock rate, which results in an enhanced power-performance-area (PPA) envelope. Sequential logic operates under a system clock that determines the system throughput, whereas combinational logic operates in a different power domain to control overall system power including dynamic and static power. The sequential logic and clock network may be implemented in one tier of the three-dimensional integrated circuit supplied with a relatively high power supply voltage, whereas the combinational logic may be implemented in another tier of the three-dimensional integrated circuit supplied with a relatively low power supply voltage. Further pipeline reorganization may be implemented to leverage the system energy consumption and performance to an optimal point.

Abstract: A phase interpolator implemented in an integrated circuit to generate a clock signal is described. The phase interpolator comprises a plurality of inputs coupled to receive a plurality of clock signals; a plurality of transistor pairs, each transistor pair having a first transistor coupled to a first output node and a second transistor coupled to a second output node, wherein a first clock signal associated with the transistor pair is coupled to a gate of the first transistor and an inverted first clock signal associated with the transistor pair is coupled to a gate of the second transistor; a first active inductor load coupled to the first output node; and a second active inductor load coupled to the second output node.

Abstract: A multi-stage frequency divider includes a cascaded arrangement of first and second integer dividers configured to collectively divide a frequency of a periodic reference signal by an integer amount equal to a product of (2N+1) and (2M+1), where N and M are unequal positive integers greater than two. A duty cycle enhancement circuit is provided, which is synchronized to the periodic reference signal and configured to generate a periodic signal having 2MN+N+M cycles of high followed by 2MN+N+M+1 cycles of low or vice versa, where a duration of each cycle is equivalent to a period of the periodic reference signal. A duty cycle correction circuit is provided as a final stage and is configured to generate a periodic output signal having a uniform duty cycle from the periodic signal generated by the duty cycle enhancement circuit.

Abstract: A clock signal processor includes a duty cycle corrector, a switch point calculator, and a multiplexer. The duty cycle corrector generates a second clock signal by modifying a duty cycle of a first clock signal. The switch point calculator activates a switch signal at an end of a latency period in which a read command is provided to a non-volatile memory device and an invalid data is read from the non-volatile memory device. The multiplexer outputs one of the first and second clock signals as a third clock signal based on the switch signal.

Abstract: A frequency divider comprises a signal generation stage arranged to employ a clock at a clock frequency to provide a first reference signal and a second reference signal, the second reference signal corresponding to the first reference signal delayed by half a period of the clock signal. A synchronization stage is arranged to generate an output signal having an output frequency divided from the clock frequency by switching between the first reference signal and the second reference signal once per cycle of the output signal.

Abstract: A technique includes controlling a modulus of a programmable divider, including selectively activating and deactivating cells of the divider. The activation for at least one of the cells includes configuring an output signal of the cell to exhibit a predetermined signal state when the cell transitions from a deactivated state to an activated state.

Abstract: Aspects of the disclosure provide a circuit including a logic circuit. The logic circuit is configured to operate without inputs from a first clock signal. The logic circuit is further configured to frequency-divide the first clock signal to generate a second clock signal based on a logic combination of a first pattern provided by a first circuitry driven by the first clock signal, and a second pattern provided by a second circuitry driven by the first clock signal.

Abstract: According to one embodiment, there is provided a fractional frequency dividing circuit including an integral frequency dividing circuit and an adjustment circuit. The integral frequency dividing circuit is configured to convert a reference signal to K (K is a positive integer) phase signals. Each of the K phase signals has a frequency of one nth (n is a positive integer) of the reference signal and has different phases from each other. The adjustment circuit is configured to weighting-add a plurality of signals corresponding to the K phase signals and generate a fractional-frequency-divided signal. The fractional-frequency-divided signal has a frequency of m times (m is a positive integer that is not multiplies of n) of each of the plurality of phase signals.

Abstract: One of the most important RF building blocks today is the frequency synthesizer, or more particularly the programmable frequency divider (divider). Such dividers preferably would support unlimited range with continuous division without incorrect divisions or loss of PLL lock. The inventors present multi-modulus dividers (MMDs) providing extended division range against the prior art and without incorrect divisions as the division ratio is switched back and forth across the boundary between two different ranges. Accordingly, the inventors present MMD frequency dividers without the drawbacks within the prior art.

Abstract: Circuits, architectures, a system and methods for providing quadrature output signals. The circuit generally includes a quadrature signal generator and a plurality of frequency dividers. The plurality of frequency dividers are each configured to receive a plurality of quadrature signal generator outputs at a first frequency and provide a plurality of outputs at a second frequency. The method generally includes providing a plurality of quadrature signals at a first frequency and dividing the first frequency of the quadrature signals by n, wherein n is an odd integer of at least 3, thereby providing a plurality of divided-by-n quadrature outputs at a second frequency, wherein the second frequency is about equal to the first frequency divided by n. The present disclosure further advantageously improves quadrature signal generation accuracy, reliability and/or performance.

Abstract: A digital fractional frequency divider for fractionally dividing a digital frequency signal can include a plurality of clock division counter modules, a plurality of sampling modules, and a summing module. The plurality of clock division counter modules can each receive an input clock signal that is phase-shifted from a remaining plurality of input clock signals. Each clock division counter module can generate a long periodic pulse from the received input clock signal. Each sampling module can couple to an output of one of the plurality of clock division counter modules and can generate a short periodic pulse from the long periodic pulse. The summing module can sum the plurality of short periodic pulses to generate a fractional frequency clock signal.

Abstract: Various embodiments implement apparatuses and methods for conversion of radio frequency (RF) signals to intermediate frequency (IF) signals. More particularly, some embodiments are directed toward down conversion of RF signals to IF signals in a multi-band radio receiver, such as a satellite receiver, using a single oscillator for different frequency bands. For example, some of the apparatuses and methods presented are suitable for integration into monolithic RF integrated circuits in low-cost satellite receivers for home entertainment use.

Abstract: A mixer includes an input stage to convert an RF input signal to an output signal, and a mixer core to mix the output signal from the input stage with a local oscillator signal. The input stage may include an input cell having a first differential pair of cross-connected transistors, and a linearizer coupled to the input cell. The linearizer may include a second differential pair of transistors having first and second inputs coupled to the input terminals and first and second outputs coupled to the output terminals.

Abstract: An oscillation signal generator includes a quadrature voltage-controlled oscillator (QVCO), a phase corrector and a frequency adjusting circuit. The QVCO provides multiple oscillation signals having difference phases. The phase corrector selects one of the oscillation signals as a first oscillation signal and outputs the first oscillation signal from a first output terminal, and selects one of the oscillation signals as a second oscillation signal and outputs the second oscillation signal from a second output terminal. A phase difference between the first and second oscillation signals satisfies a predetermined relationship. The frequency adjusting circuit is coupled to the phase corrector, and generates a quadrature signal and an in-phase signal according to the oscillation signals. The frequency of the oscillation signals is a non-integral multiple of the frequencies of the quadrature and in-phase signals.

Abstract: An apparatus includes a glitchless divider and a glitchless multiplexer. The glitchless divider may be configured to generate a first system clock in response to a divider value and a clock signal received from a first source. The divider value changes from a first value to a second value in a predetermined number of steps. The glitchless multiplexer may be configured to select between said first system clock and a second system clock in response to a control signal.

Abstract: Adaptive scaling digital techniques attempt to place the system close to the timing failure so as to maximize energy efficiency. Rapid recovery from potential failures is usually by slowing the system clock and/or providing razor solutions (instruction replay.) These techniques compromise the throughput. This application presents a technique to provide local in-situ fault resilience based on dynamic slack borrowing. This technique is non-intrusive (needs no architecture modification) and has minimal impact on throughput.

Abstract: A method and system for synchronizing the output signal phase of a plurality of frequency divider circuits in a local-oscillator (LO) or clock signal path is disclosed. The LO path includes a plurality of frequency divider circuits and a LO buffer for receiving a LO signal coupled to the plurality of frequency divider circuits. The method and system comprise adding offset voltage and setting predetermined state to each of the frequency divider circuits; and enabling the frequency divider circuits. The method and system includes enabling the LO buffer to provide the LO signal to the frequency divider circuits after they have been enabled. When the LO signal drives each of the frequency divider circuits, each of the frequency divider circuits starts an operation. Finally the method and system comprise removing the offset voltage from each of the frequency divider circuits to allow them to effectively drive other circuits.

Abstract: An electronic sub-integer frequency divider circuit, including: a phase rotator circuit, a clock circuitry, a pulse generator which is configured to: (a) receive a plurality of signals having a period TP and of different phases; (b) based on a control command, to process a second clock signal and one or more of the plurality of signals, to produce a second signal which includes S pulses in each period TP; and (c) process the second signal and a first clock signal to produce a regulating signal by which the phase rotator circuit is controlled; and an output interface configured to provide a sub-integer output signal whose frequency is responsive to the regulating signal.

Abstract: Described is an apparatus comprising a plurality of logic units arranged in a ring, wherein an output terminal of each logic unit from the plurality of logic units is coupled to an input terminal of a next logic unit from the plurality of logic units, wherein the plurality of logic units includes a first multiple input logic unit having input nodes coupled to at least two output terminals of logic units from the plurality of logic units; and a plurality of latch units coupled to the output terminals of the plurality of logic units.

Abstract: Several methods and circuits configured to mitigate signal interference of at least one aggressor circuit operable on a first clock signal within an interfering frequency range of at least one victim circuit in an IC are disclosed. In an embodiment, a signal interference mitigation circuit is configured to be associated with the aggressor circuit and includes a clock divider circuit and a control circuit. The clock divider circuit is configured to generate the first clock signal based on a second clock signal and a division factor pattern. The control circuit is coupled with the clock divider circuit and configured to determine the division factor pattern and provide the division factor pattern to the clock divider circuit. The division factor pattern comprises a plurality of division factors selected randomly based on a plurality of random numbers, and is configured to control a throughput frequency associated with the signal interference mitigation circuit.

Abstract: In a synchronization system, a frequency divider circuit generates a divided clock by dividing a reference clock in a first division ratio. First and second devices operate in synchronization with the reference clock and the divided clock. A division ratio detection circuit, for each period of the divided clock, detects a division ratio of the divided clock based on a count value counted in synchronization with the reference clock and output the division ratio as a second division ratio. A decoder generates a strobe signal, which is for controlling a timing at which the first device transmits and receives a signal to and from the second device, based on the count value and the second division ratio. The first device communicates with the second device through a bus, which operates in synchronization with the divided clock, based on the strobe signal.

Abstract: According to some embodiments, a method and apparatus are provided to vary a clock signal frequency for a first time period between a lower limit of a range of problematic frequencies and a frequency lower than the lower limit, and vary the clock signal frequency for a second period of time between an upper limit of the range of problematic frequencies and a frequency greater than the upper limit.

Abstract: This invention is a means to definitively establish the occurrence of various clock edges used in a design, balancing clock edges at various locations within an integrated circuit. Clocks entering from outside sources can be a source of on-chip-variations (OCV) resulting in unacceptable clock edge skewing. The present invention arranges placement of the various clock dividers on the chip at remote locations where these clocks are used. This minimizes the uncertainty of the edge occurrence.

Abstract: According to one embodiment, there is provided a fractional frequency dividing circuit including an integral frequency dividing circuit and an adjustment circuit. The integral frequency dividing circuit is configured to convert a reference signal to K (K is a positive integer) phase signals. Each of the K phase signals has a frequency of one nth (n is a positive integer) of the reference signal and has different phases from each other. The adjustment circuit is configured to weighting-add a plurality of signals corresponding to the K phase signals and generate a fractional-frequency-divided signal. The fractional-frequency-divided signal has a frequency of m times (m is a positive integer that is not multiplies of n) of each of the plurality of phase signals.

Abstract: An oscillator may output phased signals to a phase interpolator which is to generate an adjustable output clock signal having a phase offset relative to at least one of the phased signals received from the oscillator. A divider may then divide the frequency of the output signal generated by the phase interpolator by an integer factor.

Abstract: Embodiments of an apparatus are disclosed that may allow for changing the frequency of a clock coupled to a functional block within an integrated circuit. The apparatus may include a plurality of clock dividers and a multiplex circuit. Each of the plurality of clock dividers may divide the frequency of a base clock signal be a respective one of a plurality of divisors. The multiplex circuit may be configured to receive a plurality of selection signals, select an output from one of the plurality of clock dividers dependent upon the received selection signals, and coupled the selected output of the plurality of clock dividers to the functional block.

Abstract: In a first clock frequency multiplier, multiple injection-locked oscillators (ILOs) having spectrally-staggered lock ranges are operated in parallel to effect a collective input frequency range substantially wider than that of a solitary ILO. After each input frequency change, the ILO output clocks may be evaluated according to one or more qualifying criteria to select one of the ILOs as the final clock source. In a second clock frequency multiplier, a flexible-injection-rate injection-locked oscillator locks to super-harmonic, sub-harmonic or at-frequency injection pulses, seamlessly transitioning between the different injection pulse rates to enable a broad input frequency range. The frequency multiplication factor effected by the first and/or second clock frequency multipliers in response to an input clock is determined on the fly and then compared with a programmed (desired) multiplication factor to select between different frequency-divided instances of the frequency-multiplied clock.

Abstract: A digital-to-time converter includes a first node, a second node configured to receive a reference signal, and a digital-to-analog signal converter configured to couple a passive impedance to the first node. The passive impedance is selected according to the digital code. The digital-to-time converter also includes a first switch configured to selectively couple the first node to a second reference signal in response to the input signal and a comparator configured to generate the output signal based on a first signal on the first node and the reference signal on the second node. The digital-to-time converter may include a second switch configured to selectively couple the first node to a third reference signal in response to a first control signal.