Abstract: A driving method for a multiple frequency coupling generator is provided. The method includes: in normal operations, interpreting an input digital control signal transmitted from a digital signal processor into an interpreted digital control signal; interpreting the interpreted digital control signal into a plurality of magnetic coupling signals by a magnetic coupling switch circuit; performing signal recovery and differential delay on the magnetic coupling signals by an interlocking circuit for reducing time difference and signal loss of the magnetic coupling signals; and when the interlocking circuit determines that the magnetic coupling signals have substantially no time difference and no signal loss, transforming the magnetic coupling signals into a first driving signal and a second driving signal by a switch circuit, a driver circuit and an output pad group to drive a backend driving loop.

Abstract: A device comprises first and second qubits, and a qubit coupler coupled between the first and second qubits. The second qubit comprises first and second modes with the first mode configured to store data. The qubit coupler comprises first and second modes, and operates in a first state or second state. In the first state, the first qubit is exchange coupled to the first mode of the qubit coupler, and the second mode of the second qubit is exchange coupled to the second mode of the qubit coupler, to suppress interaction between the first and second qubits. In the second state, the first qubit and the first mode of the second qubit are exchange coupled to both the first and second modes the qubit coupler, to enable interaction between the first and second qubits for an entanglement gate operation in response to a control signal applied to the qubit coupler.

Abstract: A delay circuit includes an inverting receiving circuit, a reference point generating circuit, a first buffer gate and a first inverter. An inverting receiving circuit includes a first transistor and a first switching circuit. The reference point generating circuit includes a compensation resistor, a capacitor element, and a first current source. In response to the input signal being at a first potential, a voltage of the output node starts to decrease from a voltage reference point. In response to at least one of a manufacturing process, the first reference voltage, and a temperature being changed, the compensation resistor is configured to correct the voltage reference point.

Abstract: A method for dithering a fractional clock divider includes generating a first clock enable sequence based on a seed pattern of M ones and N minus M zeros, selecting a cyclic rotation of the seed pattern after N input clock cycles, and generating a second clock enable sequence based on the cyclic rotation. A clock gate receives the input clock signal and the clock enable sequences and outputs M clock cycles for every N input clock cycles. A random number generator indicates the cyclic rotation of the seed pattern. The seed pattern can be replaced with an updated seed pattern of M ones and N minus M zeros in a different order. In some examples, the clock enable sequence is generated using a cyclic shift register containing the seed pattern and a multiplexor. In other examples, the clock enable sequence is generated using a modulo N counter and a comparator.

Abstract: A linearizer includes: a branch circuit having an input transmission line connected between an input terminal and a branch point, a first output transmission line connected between the branch point and a first output terminal, and a second output transmission line connected between the branch point and a second output terminal; a diode having an anode connected to the branch point and a cathode; and a bias circuit biasing the diode.

Abstract: A method for preventing nonlinear interference in an optical communication system. The method may include selecting an optical signal of a first optical channel. The method may include determining an estimate of inter-channel nonlinear interference to the optical signal of the first optical channel. The inter-channel nonlinear interference may be generated by one or more optical signals transmitted over a second optical channel in the optical communication system. The method may include determining one or more linear filters based on the estimate of the inter-channel nonlinear interference. The method may include pre-distorting an optical signal for transmission over the second optical channel using the one or more linear filters. The pre-distorted optical signal may be configured for reducing the inter-channel nonlinear interference to the first optical signal of the first optical channel.

Abstract: A linear triangular wave generator with stray effect compensation includes a linear triangular wave generating module, a negative impedance converting module, an impedance sensing module and a switch module. The linear triangular wave generator charges/discharges a physical capacitor by a first current source to generate a triangular wave signal, and generates a stray component due to a stray effect. The negative impedance converting module is electrically connected to the linear triangular wave generating module, and includes a negative matching impedance. The switching module is electrically connected to the negative impedance converting module and the impedance sensing module to allow the impedance sensing module to sense an impedance value of the negative matching impedance, so as to calibrate the negative matching impedance and compensate the stray effect to further generate a linear triangular wave signal.

Abstract: A driving circuit for driving half bridge connected electrically controlled power switches with a near zero interlock delay time between on-states of the power switches, wherein the driving circuit is configured to receive an input signal and to generate: —a first drive signal being adapted to switch a first power switch between the on and off state, —a second drive signal being adapted to switch a second power switch between the on and off state, wherein the signal curve of the first drive signal generated in response to a rising and falling edge of said input signal is mirrored with respect to the signal curve of the second drive signal along a time axis of a mirroring voltage value within a transition time, wherein the mirroring voltage value is adjusted such to be within the cutoff region of the power switches.

Abstract: A device for signal processing. The device includes a signal generator, a signal detector, and a processor. The signal generator generates an original waveform. The signal detector detects an affected waveform. The processor is coupled to the signal detector. The processor receives the affected waveform from the signal detector. The processor also compares at least one portion of the affected waveform with the original waveform. The processor also determines a difference between the affected waveform and the original waveform. The processor also determines a value corresponding to a unique portion of the determined difference between the original and affected waveforms. The processor also outputs the determined value.

Abstract: A bipolar junction transistor (BJT) may be used in a power stage DC-to-DC converter, such as for LED-based light bulbs. The BJT may be switched on and off from a controller coupled to two terminals of the BJT. Through the two terminals, the control IC may dynamically adjust a reverse recovery time period of the BJT. The reverse recovery time period may be adjusted by changing an amount of base charge that accumulates on the BJT. Additional, the reverse recovery may be controlled through the use of a reverse base current source applied to the BJT after beginning switching off the BJT.

Abstract: A voltage-controlled oscillator (VCO) comprises a supply voltage node, configured to receive a supply voltage, a VCO output capacitor, configured to provide an oscillating output voltage across the capacitor, a discharge switch configured to discharge the capacitor according to an oscillation frequency of the oscillating output voltage, and a comparator circuit configured to provide, to a control terminal of the discharge switch, a control signal that is determined based on a comparison of the output voltage and a specified threshold voltage. The oscillating output voltage includes a pulse having a ramp slope that is determined as a function of a magnitude of the supply voltage, and is capable of being adjusted independently of the oscillation frequency.

Abstract: A ramp signal generation circuit 21 comprises a plurality of unit circuits 221 to 22N, each including a capacitor 26 having one end 26a held at a fixed potential and a current source 27 connected to the other end 26b of the capacitor 26, while the other ends 26b of the capacitors 26 in the plurality of unit circuits 221 to 22N are connected to each other with a wiring member W.

Abstract: A triangular waveform generator includes a square waveform clock circuit and an integrating circuit. The integration circuit receives input from the square waveform clock circuit and generates a triangular waveform output. A feedback circuit is operatively connected to the integrating circuit to reduce the audio band noise content in the triangular waveform output. The feedback circuit acts as a DC balance without significant sacrifice in the linearity of the triangular waveform output.

Abstract: A method for generating a ramp comprises providing a voltage reference source, providing a summing amplifier, providing n switched capacitor elements coupled in parallel between the voltage reference source and the summing amplifier, and selectively activating a predetermined number of the switched capacitor elements to first store charge on each activated switched capacitor element and then to measure the sum of the charges on the activated capacitor switch elements in each of a fixed-integer number of time slots in a cyclical manner, the predetermined number being between 0 and n.

Abstract: A signal processing arrangement including a signal processing stage that divides an input signal (Vin) applied to a signal input (In) of the signal processing stage into at least two subsignals (Vin_a, Vin_b) as a function of a signal amplitude (A) of the input signal (Vin), wherein the signal processing stage is designed for parallel signal processing of the subsignals (Vin_a, Vin_b), and a reconstruction stage connected to the signal processing stage and provides an output signal (Vout) by weighting and combining the at least two processed subsignals (Vin_a, Vin_b).

Abstract: A non-linear power amplifier generates an amplified output signal based on a pre-distorted signal generated by a digital pre-distorter (DPD) based on an input signal. A feedback path generates a feedback signal based on the amplified output signal. The feedback signal is aligned with the input signal, or vice versa, and the aligned signals are used to adaptively update the DPD processing. In particular, a linear FIR filter is estimated to minimize a cost function based on the input and feedback signals. Depending on how the filter is generated, the filter is applied to the input signal or to the feedback signal to generate the aligned input and feedback signals.

Abstract: A triangular waveform generator includes a square waveform clock circuit and an integrating circuit. The integration circuit receives input from the square waveform clock circuit and generates a triangular waveform output. A feedback circuit is operatively connected to the integrating circuit to reduce the audio band noise content in the triangular waveform output. The feedback circuit acts as a DC balance without significant sacrifice in the linearity of the triangular waveform output.

Abstract: In one embodiment, an analog-to-digital converter (ADC) includes a comparator and a supply circuit. The comparator is configured to compare an input signal to a reference signal. The supply circuit is configured to supply the reference signal. The supply circuit is configured to provide different circuit configurations for supplying the reference signal during different stages of analog-to-digital conversion such that the reference signal is scaled in substantially a same manner during at least two of the stages.

Abstract: A circuit and method are provided for a power converter to select one from a plurality of current limit signals as a final current limit signal according to the present duty ratio of a power switch for the pulse width modulation of the next cycle, so that the duty ratio of the power switch in the next cycle is prevented from acute variation to eliminate sub-harmonic which otherwise may happen.

Abstract: A system includes a laser generator, and a signal distortion generator circuit inline with the laser generator modulation signal and configured to generate distortion vectors in any of four distortion vector quadrants.

Abstract: Mixer topologies that have sufficiently high IIP2 and sufficiently low quadrature error to make zero IF receivers possible without special calibration techniques. This simplifies the receiver, avoids circuit startup delay and provides more stable performance over time and temperature. The methodology to achieve this performance in preferred embodiments consists of as many as three elements: (a) a high power local oscillator buffer circuit capable of driving low impedance loads coupled to the bases of the bipolar mixer transistors, (b) an optimized bias block for the mixer core and (c) incorporating two or more electronically programmable quad sections and selecting the best quad for use. Other types of transistors may also be used.

Abstract: Methods and apparatus (100) for composing, generating and transmitting information-bearing optical signals are provided. An information-bearing electrical signal is composed (108) having desirable spectral properties, preferably configured to ensure that undesired interference between electrical spectral components generated in a square-law direct detection process (120) at a corresponding optical receiver (104) is substantially avoided. Predistortion (110) is advantageously applied to transmitted signals, in order to account for a nonlinear relationship arising in a modulation process (114) between electrical signal amplitude and corresponding optical field amplitude. Orthogonal frequency division multiplexing (OFDM) techniques may be applied to composed signals having the desired characteristics, and additionally may facilitate the application of frequency domain equalisation (128) in order to mitigate transmission impairments, including dispersion.

Abstract: A spread spectrum clock generator is provided which improves the spread spectrum effect with little increasing the circuit cost by modifying the shape of a triangular wave used for frequency modulation by a simple method. The output signal of the modulation waveform generating circuit has such a modulation waveform as indicated by solid lines in FIG. 2A. The modulation waveform is input to a VCO (voltage-controlled oscillator). In response to the modulation waveform, the oscillation frequency of the VCO is modulated, and the output clock that varies its frequency as illustrated in FIG. 2B is obtained. The frequency transition of the output clock involves such temporal variations as indicated by solid lines in FIG. 2C.

Abstract: A low power servo-controlled single clock ramp generator (100) includes a fast switched comparator (102), charge pump (110) and voltage-to-current converter (120) connected to provide a feedback control mechanism under control of a pulse comparison clock signal (pulse_comp) and a reset pulse clock signal (rst_pulse) that are generated from a single input clock signal (clkin) so that there are well defined time intervals between pulses in the pulse comparison clock signal and the reset pulse clock signal, thereby providing a ramp signal (Vramp_out) having a stable, frequency-independent amplitude that is not limited by the reference voltage.

Abstract: A method of contact lithography includes predicting distortions likely to occur in transferring a pattern from a mold to a substrate during a contact lithography process; and modifying the mold to compensate for the distortions. A contact lithography system includes a design subsystem configured to generate data describing a lithography pattern; an analysis subsystem configured to identify one or more distortions likely to occur when using a mold created from the data; and a mold modification subsystem configured to modify the data to compensate for the one or more distortions identified by the analysis subsystem.

Abstract: An accurate intermittent triangular wave signal without waveform distortion is generated by a triangular wave generation circuit 1 including a rectangular wave generation circuit 111 for generating an intermittent rectangular wave signal in which a rectangular wave interval and a direct current interval of a predetermined level are repeated; an integration circuit 12 for generating an intermittent triangular wave signal in which a triangular wave interval and a direct current interval are repeated based on a reference signal and the intermittent rectangular wave signal generated by the rectangular wave generation circuit 111; and a triangular wave correcting circuit 112 for correcting waveform distortion of the intermittent triangular wave signal based on a differential voltage between a starting point and an ending point of the direct current interval of the intermittent triangular wave signal output from the integration circuit 12.

Abstract: A system and method for generating a reduced transition time ramp waveform signal are disclosed. Two offset, synchronized ramp waveform signals are generated. Each ramp waveform signal has a repeating sequence including a linear development segment, an upper transition segment, a return segment, and a lower transition segment. The ramp waveform signals are offset synchronized such that the linear development segment of each ramp waveform signal begins before the linear development segment of the other ramp waveform signal ends. Each ramp waveform signal is sampled during its linear development segment to generate a reduced transition time ramp waveform signal.

Abstract: Zero crossings for a non-symmetrical VIN may be determined by first amplifying and clipping VIN to create a non-symmetrical square wave whose zero crossings are those of VIN. A selected polarity edge of the non-symmetrical square wave may be taken as a 0° indicator and is used to create a fundamental sawtooth ramp of the same frequency and in phase with VIN. The fundamental sawtooth ramp starts at zero volts, linearly ramps to some peak and is AC coupled to a comparator whose other input is zero volts. That creates a square wave that is symmetrical as to its half-cycles, and whose every other edge is synchronous with the start of the fundamental sawtooth ramp, and whose intervening edges occur in the middle of the ramp. The intervening edge is detected and taken as a 180° indicator.

Abstract: A waveform generating circuit is provided which generates a modified triangular wave signal suitable for being input to a frequency modulation circuit such as a voltage-controlled oscillator (VCO). The waveform generating circuit includes a triangular generator, an offset generator for generating first and second offset component signals, a combiner for adding the triangular wave signal generated by the triangular wave generator and the offset component signals, and an output for delivering an output signal resulting from the addition by the combiner.

Abstract: A bank of complex gain elements is used to provide a step-wise approximation of an arbitrary complex-gain predistortion function for a nonlinear transmitter. The bank of gain elements is in an adaptive loop realizing adaptive control. The adaptive loop is closed between an Input of the gain bank and an output of the transmitter through a linear receiver at an adaptive controller composed of a bank of proportional-integral (PI) controllers. The real and imaginary parts of each predistortion gain element are controlled by a corresponding adaptive PI controller. The signals processed by the adaptive controller are represented in orthogonal coordinates in terms of real and imaginary number pairs of complex numbers. The adaptive controller achieves unconditionally stable operation independently from the arbitrary phase rotation in the input signal or the adaptive loop.

Abstract: Circuitry for ramping a voltage across a load 506 includes a charging circuit 500 for charging a capacitor 501 to generate a ramp-up wave form. Circuitry 511 selectively decouples a first driver 510 from load 506 during a ramping up mode and couples first driver 510 to load 506 during a normal operating mode. Ramp up driver 507a is selectively coupled to the load 506 during the ramp-up mode for ramping up the voltage across load 506 in response to the ramp-up wave form generated by charging circuitry 500. A discharge circuit 503d, 514a,b discharges capacitor 501 to generate a power-down wave form. Circuitry 511 selectively decouples a first driver 501 from output load 506 during the ramping down of the voltage across output load 506. A ramp-down driver 507b selectively ramps-down the voltage across output load 506 in response to the ramp-down wave form generated by discharge circuitry 503d, 514a,b.

Abstract: In a method for prescribing an essentially linear ramp with a prescribable slope by a quantity, and which is clock-pulse-controlled and which describes the ramp by an increment per clock interval, the ramp is described by a number of regular increments and by at least one first and one second irregular increment. The regular increments exhibit a value corresponding to the prescribable slope. The irregular increments exhibit a value deviating from the prescribable slope. The first irregular increment is a first increment describing the ramp and the second irregular increment is a last increment describing the ramp.

Abstract: An in-line distortion generator for coupling in-line with a non-linear device (NLD) produces an output signal of useful amplitude, but with low composite triple beat and cross modulation distortions. The distortion generator comprises an instant controlled non-linear attenuator which utilizes the non-linear current flowing through a pair of diodes to provide the proper amount of signal attenuation over the entire frequency bandwidth. The distortion generator circuitry is always matched to the NLD, thereby ensuring a frequency response that is predictable and predefined. The distortion generator may also include a temperature compensation circuit to ensure consistent operation throughout a wide temperature range.

Abstract: An electrical circuit tracing device comprising a transmitter that includes a pocket for storing the receiver is disclosed. The transmitter further comprises a storage compartment for maintaining a plurality of pre-wired connectors, and a clip which can be used to attach the transmitter to a pocket, a belt, or another carrying device.

Abstract: A system and method of integrating switching amplifiers into systems with low amplitude front-end tuners to eliminate shielding and EMI filtering associated with signals, power and ground. An adaptive frequency programmable pulse frame rate switching amplifier scheme using either look-up tables or appropriate algorithms, ensures by design, the elimination of critical interference frequency generation.

Abstract: Simplifying functions representing raised sine or cosine curves to functions representing simple sine or cosine curves makes it possible to implement an electrical equivalent circuit for a ramp generator. The core of the ramp generator with an output power level controller is second-order direct-form feedback structure (60), which forms a digital sinusoidal oscillator. The initial values of two state variables x2(n), x2(n+1) of the oscillator are chosen so that they both contain a predetermined first constant value. This first constant value will emerge as the amplitude value of the pure sine wave generated by the oscillator. Particularly the first constant value is equal to the desired nominal level A of the ramp minus the starting level. A second constant value (A+dc) is added to the oscillator output. The added result is scaled (66) so that the nominal power level is A. A multiplexer (67) keeps the power level between the ramps constant.

Abstract: A linear ramp generating and control circuit finding particular applicability in a time interval measurement system. The linear ramp circuit includes a hold capacitor which may be linearly discharged during one operating mode of the circuit by coupling a constant current source to the capacitor. The voltage on the hold capacitor is linearly discharged away from a baseline voltage level to a data voltage level which is subsequently passed to an analog-to-digital converter of the time interval measurement system for further processing. The hold capacitor voltage is returned to the baseline voltage level during a recovery mode of circuit operation by a recovery or recharge network. The recharge network may include an active-feedback circuit which implements an approximately second-order voltage response to the hold capacitor during the recovery mode of operation.

Abstract: A first capacitor 7, a resistor 5, and a second capacitor 6 are connected in series between an output node A and a first power supply line 22. In addition, a first switch 8 is connected between the connected point of the first capacitor 7 and the resistor 5 and a second power supply line. A second switch 9 is connected in parallel with the second capacitor 6. The first and second switches 8 and 9 are opened or closed corresponding to the level of the input signal.

Abstract: A device for correcting the linearity of ramps of a saw-tooth signal provided across a capacitor, charged by a first current source and periodically discharged at a desired frequency. The device modulates the charging current of the capacitor by a correction current to render the ramps of the signal not linear. In addition, the device includes circuitry to render the correction current proportional to the current provided by the first current source.

Abstract: An integrated detection circuit (10) linearly charges capacitors (14) and (16) over time in response to particular states of an input signal (12). Outputs from the integrated detection circuit (10) are generated by differential pairs (39) when the charge on either of the capacitors (14) or (16) is equal to or greater than a reference voltage input to the differential pairs (39).

Abstract: An improved system and method of determining the linearity of a ramp signal, including a ramp generator (11) for generating a ramp signal and a vernier delay (15) to provide scan stop signals where the samples are peak detected (17) and stored (21). The ramp generator (11) outputs are divided into equal sections controlled by a precise crystal controlled oscillator (25). The stored signals are processed and compared to detect errors.

Abstract: An integrated circuit pulse generator for per pin testing of electronic circuits. The pulse generator allows for independent adjustment of the slew rates of the rising and falling edges of the pulses. The pulse edges are generated by summing two separately controlled falling edge ramp generators. The circuit design of the pulse generator is structured to allow implementation with NPN transistors. The falling edge ramp generators operate by discharging a capacitor with a current source. The slew rates are varied by incrementally adding capacitance to the capacitor being discharged.

Abstract: An ultra-linear chirp generator includes a voltage controlled oscillator (VCO) having a tuning characteristic which is naturally nonlinear, a linear ramp generator which generates a linearly ramping output signal having a linear slope characteristic with respect to time, a polynomial correction waveform generator which generates a polynomial correction signal, and a summer which is responsive to and sums the linearly ramping output signal and the polynomial correction signal. The summer generates a VCO tuning signal for tuning the VCO. The tuning signal corresponds to the linearly ramping output signal predistorted with a nonlinearity opposite to the natural nonlinearity of the VCO tuning characteristic. The linear chirp generator also includes a phase locked loop which is responsive to the output signal of the VCO and which has a reference frequency which is related to the repetition rate of the output signal of the VCO.

Abstract: A sawtooth generates a sawtooth wave having a high response speed and good linearity with a simple arrangement in converting a change in phase of an input signal into a linear level change. A signal interpolating apparatus uses this sawtooth wave to output a predetermined signal (interpolation signal) every predetermined phase change of the input signal with a simple arrangement. An arithmetic operation section receives two sinusoidal signals A and B having equal periods and phases which are offset by 90.degree. and with respect to each other, obtain a signal X=A/(B+a) and a signal Y=A/(B+B) using constants .alpha. and .beta. respectively satisfying B+.alpha..apprxeq.0 and B+.beta..apprxeq.0. A switching unit selects the linear ramp portions of the signals X and Y to output a continuous sawtooth wave. On the basis of the value of this sawtooth wave, a desired interpolation signal is output from a memory which stores predetermined data.

Abstract: An automatic compensation circuit for the horizontal deflection of a multifrequency computer monitor includes a transformer which has a primary winding and a secondary winding, a reverse coil which is reversely wired with respect to the secondary winding of the transformer being connected to the secondary winding of the transformer, a capacitor being serially connected between the reverse coil and a ground, a voltage/current converting circuit electrically connected to the first winding of the transformer, and a frequency/voltage converter being electrically connected between a computer monitor and the voltage/current converting circuit for converting the horizontal frequency of the computer monitor to a corresponding voltage and transmitting the converted voltage to the voltage/current circuit.

Abstract: A generalized frequency dependent predistortion circuit for nonlinear optic devices such as semiconductor lasers and light emitting diodes includes a pre-filter and post-filter associated with a linearizer (distorter). A multi-channel sub-carrier electrical signal is input to a splitter which provides on a primary path a signal to a time delay and hence to a coupler to the secondary paths. In the first secondary path, a pre-filter provides a signal to a second order distorter. This signal is then subject to a post-filter and then to a variable attenuator. In the second secondary path, a third order distorter again has an associated pre-filter and post-filter with a variable attenuator downstream of the post-filter. The variable attenuators in each path provide frequency independent attenuation. In one version the distorters in both paths are nonlinear diode circuits. The second secondary path provides very low fundamental leak-through.

Abstract: A scanning waveform generator for operation at a first or a second scanning frequency comprises a source of a parabolic shaped signal having a frequency selectable between the first or second scanning frequency. A means for generating a switching signal indicative of a video signal operating at one of a first or a second scanning frequency. A means for generating a sawtooth shaped waveform is coupled to the switching signal for switching between the first or the second scanning frequency. A means for generating an S correction signal is coupled to the source and to the sawtooth generating means. A means for filtering the parabolic signal is controllably coupled to the switching signal generator, and is also coupled to the S correction signal generating means. The filtered parabolic signal has an substantially the same shape during the first or second scanning frequency.

Abstract: A geometry correction waveform synthesizer includes a plurality of DC controlled multipliers each coupled to respective sources of complimentary geometry correction signals. The DC controlled multipliers are coupled to respective gain control voltage sources as well as null adjustment voltage sources to provide a variable amplitude and polarity correction signal output. The individual correction signal outputs of the DC controlled multipliers are combined to form a composite geometry correction signal which is applied to a gain control circuit. The individual gain control signals used by the DC controlled multipliers are added to form a combined gain control signal which is used to control the composite correction signal amplitude and maintain correction signal amplitude within a predetermined range. An overall gain control couples the composite geometry correction signal to the scan system.