Abstract: In start-up, current is sourced by a current source to a first plate of a first capacitor while a second capacitor is maintained at zero charge. In a subsequent first operating phase, current is sourced to a first plate of the second capacitor while a second plate of the first capacitor is connected to the first plate of the second capacitor. At the end of the first operating phase, the first capacitor is discharged. In a subsequent second operating phase, current is sourced to the first plate of the first capacitor while a second plate of the second capacitor is connected to the first plate of the first capacitor. At the end of the second operating phase, the second capacitor is discharged. Steady state operation of the circuit involves an alternation of the first and second operating phases interleaved with transition phases where the first and second capacitors are discharged.

Abstract: A system for detecting object movement including a sensory network having at least one sensory device using modulated radar for detecting an object in proximity to the sensory network. The sensory network including wireless transmission means and a base station having computer processing means located remote from the sensory network and including wireless transmission means to communicate with the sensory network. The base station having computer readable program code means for causing the computer processing means to analyze data received from the sensory network to determine motion characteristics of the object in proximity to the sensory network.

Abstract: A fully integrated ramp generator circuit includes a first current generator that sources current to first capacitor through a first transistor that is gate controlled by the complement of a periodic signal. The ramping voltage stored on the first capacitor is buffered to an output node as a ramp output signal. A second transistor couples the output node to the first current generator and is gate controlled by the periodic signal. The periodic signal is generated at the output of a flip-flop that receives an input clock signal and reset signal. The reset signal is generated by a comparator circuit operable to compare the voltage on a second capacitor to a reference. The second capacitor is charged by a second current source and discharged by a third transistor that is gate controlled by the periodic signal.

Abstract: A ramp output control device includes a driver configured to receive at least two inputs from a microcontroller. The driver includes a time duration register configured to store a current clock count until a preset time duration is reached. The driver also includes a ramp output register configured to store a current output value at an output of the device. The driver also includes a calculation block configured to determine whether to increase the current output value at the output based on the at least two inputs.

Abstract: A sawtooth wave generating circuit that outputs a sawtooth wave signal after calibration and a switch mode power supply device including the sawtooth wave generating circuit is disclosed. The sawtooth wave generating circuit includes a capacitor, a calibration circuit, a charging circuit, discharging circuit and a control unit. The calibration circuit feedbacks a sawtooth wave signal, generates a plurality of voltage signals based on the sawtooth wave signal, and selects one of the voltage signals to generate a calibration output signal. Therefore, the sawtooth wave generating circuit generates a stable sawtooth wave signal regardless of operating conditions.

Abstract: Provided are a method and apparatus (receiver) of receiving and processing a radio signal in a transmitter-receiver environment. The radio signals are transmitted across a wireless interface using Ultra Wideband (UWB) pulses. A transmitted reference approach is utilized. The radio signal include pairs of UWB pulses with each pair of pulses separated by a fixed time delay. The two pulses are then combined to provide for improved noise immunity.

Abstract: The sawtooth wave generation circuit includes: a switch circuit configured to switch a connection state thereof between a first connection state, in which a current from a current source is flowed from a first terminal of the output capacitor to a second terminal of the output capacitor, and a second connection state, in which a current from the current source is flowed from the second terminal of the output capacitor to the first terminal of the output capacitor; a switch control circuit configured such that, in each connection state of the switch circuit, if an output voltage has reached a predetermined threshold which is set in relation to an intermediate voltage, the switch control circuit controls the switch circuit to switch the connection state to the other connection state at least during a part of a predetermined period thereafter.

Abstract: The invention includes a method for transmitting and detecting high speed Ultra Wideband pulses across a wireless interface. The transmitter includes a serializer and pulse generator. The receiver comprises a fixed delay line, multiplier, local serializer (with a sequence matching the transmitter), digital delay lines, low noise amplifier and logic fan-out buffer along with an array of D flip-flop pairs. Each flip-flop pair is enabled, at fixed time increments, to detect signals at a precise time; the timing is controlled by the pseudo-random sequence generated by the local serializer. A local tunable oscillator is controlled by detecting the phase change of the incoming signal and applying compensation to maintain the phase alignment and clock synchronization of the receiver to the clock reference of the transmitter. The invention uses a pair of pulses with a fixed delay and then relies on mixing the two to provide better noise immunity.

Abstract: An integrated circuit includes a saw-tooth generator including a saw tooth node configured to have a saw-tooth voltage generated thereon; and a first switch having a first end connected to the saw tooth node. The integrated circuit further includes a second switch coupled between an output node and an electrical ground, wherein the first switch and the second switch are configured to operate synchronously. A first current source is connected to the saw tooth node. A second current source is connected to the output node.

Abstract: A signal detector and a signal detection method adapted for detecting a voltage signal are provided. According to a digital signal converted from a low voltage full wave or half wave signal and/or a mains AC signal inputted thereto, the signal detector and the signal detection method are capable of detecting a voltage level, and/or a frequency, and/or a zero point, and/or a phase of the low voltage full wave or half wave signal and/or the mains AC signal inputted thereto, and determining whether the detected factor is abnormal, and is further capable of outputting an interrupt signal for subsequent processing.

Abstract: An integrated circuit includes a saw-tooth generator including a saw tooth node configured to have a saw-tooth voltage generated thereon; and a first switch having a first end connected to the saw tooth node. The integrated circuit further includes a second switch coupled between an output node and an electrical ground, wherein the first switch and the second switch are configured to operate synchronously. A first current source is connected to the saw tooth node. A second current source is connected to the output node.

Abstract: A phase shift circuit includes an on signal generator, an off signal generator, and a channel signal generator. The on signal generator generates an on signal having a rising edge shifted by a predetermined phase based on a pulse width modulation (PWM) signal, the off signal generator generates an off signal based on the PWM signal and the on signal, and the channel signal generator generates a channel signal that is enabled in response to the rising edge of the on signal and disabled in response to a rising edge of the off signal.

Abstract: The frequency characteristic of a voltage-feedback class-D amplifier circuit for driving an output load is improved. A triangular-wave correction circuit which compensates a gradient of a triangular wave is provided to a triangular-wave signal generator which supplies a triangular wave signal used as a PWM carrier to a comparison circuit for performing PWM modulation of an input signal. In an area where a duty of a command value for an output circuit drive becomes about 50%, a slew rate (gradient) of the triangular wave is decreased.

Abstract: A circuit includes a pulse transformer having primary and secondary windings. An oscillating waveform is applied to the primary winding to induce an oscillating waveform at the secondary winding. A transistor in series with a first resistor is coupled between the secondary winding and the ground. An R-C network formed by a second and a third resistor and a capacitor is coupled to a base junction of the transistor. The R-C network causes a slow, tapered linear pinch off of the transistor's conductance to enable the circuit to output a triangular waveform, which is characterized by a relatively short linear rise time followed by a substantially long linear fall time. The R-C network is coupled to the secondary winding via a first and a second diode, respectively.

Abstract: A low power servo-controlled single clock ramp generator (100) includes a fast switched comparator (102), charge pump (110) and voltage-to-current converter (120) connected to provide a feedback control mechanism under control of a pulse comparison clock signal (pulse_comp) and a reset pulse clock signal (rst_pulse) that are generated from a single input clock signal (clkin) so that there are well defined time intervals between pulses in the pulse comparison clock signal and the reset pulse clock signal, thereby providing a ramp signal (Vramp_out) having a stable, frequency-independent amplitude that is not limited by the reference voltage.

Abstract: An integrated circuit includes a phase step generator and a clock circuit. The phase step generator generates an input clock signal based on a reference clock and the clock circuit generates an output clock signal based on the input clock signal. Additionally, the clock circuit generates a feedback clock signal based on the output clock signal and locks a phase of the feedback clock signal with a phase of the input clock signal. In response to an assertion of a trigger signal, the phase step generator extends a phase of the input clock signal by inserting a phase step into the reference clock signal. A bandwidth of the clock circuit is determined based on the output clock signal after assertion of the trigger signal.

Abstract: In a triangular-wave generating apparatus including an output terminal adapted to output an output voltage, an incorporated capacitor connected to the output terminal, a first variable current source adapted to charge the incorporated capacitor and a second variable current source adapted to discharge the incorporated capacitor, a charging/discharging current setting circuit sets a charging current in the first variable current source and sets a discharging current in the second variable current source. A level determining circuit determines whether or not the output voltage reaches one of predetermined voltages, to generate timing signals. A reference clock signal generating circuit generates a reference clock signal for defining a frequency of the output voltage. A charging/discharging current adjusting circuit adjusts the charging current and the discharging current in accordance with the timing signals and the reference clock signal.

Abstract: A triangle waveform generator is set forth that comprises a capacitive element, a regulator, and a control circuit. The regulator is configured to charge the capacitive element in responsive to a first control signal and to discharge the capacitive element in response to a second control signal. The control circuit is responsive to a reference waveform to generate the first and second control signals. In one example, the control circuit generates the first and second control signals in response to the amplitude, frequency, phase, and symmetry of the reference waveform.

Abstract: A triangle wave generator with function of spreading frequency spectrum is provided. The triangle wave generator includes a switch control circuit, a current generator, an integrator, and a spread spectrum control circuit. The switch control circuit provides an internal clock and a switch control signal. The current generator is coupled to the switch control circuit and provides charge current according to the switch control signal. The integrator is coupled to the current generator and provides a triangle wave signal. The spread spectrum control circuit is coupled to the switch control circuit and the current generator for providing a current control signal according to the internal clock.

Abstract: A ramp generation circuit including, a charge supply unit which generates predetermined charges every predetermined time, an integration circuit which accumulates the charges generated from the charge supply unit and converts the charges into a voltage, and, an attenuation unit which outputs, to an output terminal, a voltage obtained by attenuating a noise value of an output voltage from the integration circuit.

Abstract: Zero crossings for a non-symmetrical VIN may be determined by first amplifying and clipping VIN to create a non-symmetrical square wave whose zero crossings are those of VIN. A selected polarity edge of the non-symmetrical square wave may be taken as a 0° indicator and is used to create a fundamental sawtooth ramp of the same frequency and in phase with VIN. The fundamental sawtooth ramp starts at zero volts, linearly ramps to some peak and is AC coupled to a comparator whose other input is zero volts. That creates a square wave that is symmetrical as to its half-cycles, and whose every other edge is synchronous with the start of the fundamental sawtooth ramp, and whose intervening edges occur in the middle of the ramp. The intervening edge is detected and taken as a 180° indicator.

Abstract: A double frequency signal generator to which a synchronization signal having a duty cycle of 1% to 999% is inputted. The synchronization signal is used for triggering of a switching component at positive and negative edges to generate a triangular-wave signal. An average of voltages of the triangular-wave signal is acquired and compared with the triangular-wave signal at a comparator to generate a square-wave having a duty cycle of 50%. Then, the square-wave signal is used for triggering at positive and negative edges to generate a double frequency signal. As such, the high cost issue and the limitation of a square-wave input signal occurred in the prior art may be efficiently overcome.

Abstract: A control device having a forced operation function has an output circuit that operates in response to an output control signal generated within the control device and a terminal for feeding a signal from the output circuit to outside the control device. The control device further has a signal detection circuit that outputs a forced operation signal when a predetermined signal is fed from the outside to that terminal. The output control signal generated within the control device and the forced operation signal produced by the signal detection circuit are fed through an OR circuit to the output circuit. This circuit configuration makes it possible to reduce the number of terminals to be provided in a control device having a forced operation function and thereby reduce its costs.

Abstract: An oscillation apparatus is provided with a signal input unit for supplying a pulse sequence consisting of pulses sequentially continuously occurred; a state quantity generating unit for generating state quantity having a value which is monotonously increased with the passage of time; a state quantity transition unit for transferring a value of state quantity in the course of generation in said state quantity generating unit to a value changed by a predetermined amount in a varying direction of the value of the state quantity with respect to a present value of the state quantity, whenever one pulse is fed from said signal input unit to said state quantity transition unit; a state quantity reset unit for comparing the present value of the state quantity generated in said state quantity generating unit with a predetermined threshold value, and resetting the present value of the state quantity generated in said state quantity generating unit to a predetermined initial value when the present value reaches the thr

Abstract: A precision oscillator circuit having a wide adjustable operating frequency range and an adjustable duty cycle. The precision oscillator use a window comparator circuit for monitoring a voltage of a capacitive element. The window comparator circuit has a first operating voltage edge and a second operating voltage edge wherein the first operating voltage edge latches an output signal of the window comparator circuit at one level when the voltage of the capacitive element is greater than the first operating voltage edge. The second operating voltage edge brings the output signal of the window comparator circuit back to an initial level when the voltage of the capacitive element is greater than the second operating voltage edge. A precision current reference source is coupled to the capacitive element and to the window comparator circuit. The precision current reference is used for generating currents which are insensitive to temperature, supply voltage, and process variations.

Abstract: A low-power differential switching amplifier (200, 210, 220, 230) is provided which utilizes a unique technique of generating interlaced ramps. The interlacing of the ramps causes the ramp discharge time to be effectively zero, which produces exceptionally accurate sawtooth waveforms with virtually no distortion. The timing of the differential switching amplifier circuitry can be synchronized with an external clock. A voltage null point is produced in the differential amplifier where zero voltage at the input of the amplifier produces essentially zero power dissipation within the load, even if the load is low-Q or substantially resistive. Also, by use of a phase balancing technique, residual errors resulting from component mismatches, which would otherwise have imposed power losses upon the load, are nulled out automatically during the operation of the amplifier.

Abstract: An improved system and method of determining the linearity of a ramp signal, including a ramp generator (11) for generating a ramp signal and a vernier delay (15) to provide scan stop signals where the samples are peak detected (17) and stored (21). The ramp generator (11) outputs are divided into equal sections controlled by a precise crystal controlled oscillator (25). The stored signals are processed and compared to detect errors.

Abstract: A low power consumption switch interface circuit (100) includes a current source (109) for providing switch current (144) having a magnitude dependent on a state of a current range signal (135). An input terminal (142) is provided to conduct the switch current (144) to an external switch (102). A circuit (101, 103, 119) for detecting a signal (141) present at the input terminal (142) provides a measured pulse (127) when the signal (141) is detected. A current range selector (129), coupled to the current source (109), outputs a first state of the current range signal (135) while the measured pulse (127) is outputted from the circuit (101, 103, 119), and a second state of the current range signal (135) while the measured pulse (127) is not outputted from the circuit (101, 103, 119).

Abstract: An improved timer oscillation circuit capable of synchronizing an oscillation frequency, which is determined by a time constant of a resistance and a capacitance, to a clock signal, which includes a first voltage comparator, controlled by a clock signal, for charging a first voltage on a second capacitance and for outputting a result obtained by comparing the charged voltage on the second capacitance and a voltage from the first capacitance; and a second voltage comparator, controlled by the clock signal, for charging a voltage outputted from the first capacitance on a third capacitance and for outputting a result by comparing the charged voltage and an electric potential of the second voltage, so that it can be advantageously adopted to a digital circuit by outputting an oscillation signal having a cycle determined by a time constant of a resistance and a capacitance and which is synchronized to a clock signal.

Abstract: A graphics engine is disclosed which can be used in a color desktop publishing system. The graphics engine accepts 32-bit RGBM data and performs pixel level calculations under computer control to output processed 32-bit RGBM data The engine comprises a render processor interface, a run controller including a ramp generator, and a control unit. Interpolators are provided for each color (RGB) and cascaded with corresponding compositors. A transparency interpolator and matte combiner alter the matte plane of the video image. The engine can output data suitable for rendering by a color laser printer for a full size A3 page at 400 dots per inch.

Abstract: An oscillator for generating a varying amplitude feed forward power factor correction (PFC) modulation ramp signal includes a clock generating circuit and a ramp generating circuit. The PFC ramp signal generated by the ramp generating circuit is used within a power factor correction circuit of a switching mode power converter. The timing capacitor used within the ramp generating circuit is charged from the full wave rectified line input voltage so that the amplitude of the generated ramp output signal will follow the full wave rectified input signal, thereby maintaining the current loop bandwidth at a constant value and improving the transient response of the circuit. A one-shot circuit is coupled between the discharge transistor of the clock generating circuit and the discharge transistor of the ramp generating circuit for synchronizing the clock and ramp reference signals generated by the oscillator so that the frequency of the ramp reference signal is equal to the frequency of the clock signal.

Abstract: A ramp generator has an integrator, which provides a ramp output, and a counter, which counts a clock signal during the rise period. The counter and clock are arranged so that when the actual rise time is equal to the desired rise time, the counter overflows and returns to zero. If the rise time is too slow, the counter will contain a count at the end of the rise period. A register is connected to receive this count and an adder adds the contents of the register to the contents of the adder repeatedly each time a clock pulse is generated. The adder has an output connected to the input of the integrator and, each time the adder overflows, supplies a correction pulse to the integrator so that its rise rate is increased.